A memory access method, device, chip and computer readable storage medium
By obtaining memory configuration information in a dual-core MCU and dynamically adjusting the address mapping relationship between memory blocks and the kernel, the problems of low memory access efficiency and bus conflicts are solved, achieving more efficient memory access.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN HANGSHUN CHIP TECH DEV CO LTD
- Filing Date
- 2022-08-31
- Publication Date
- 2026-06-26
AI Technical Summary
Existing technologies in dual-core MCUs suffer from bus conflicts and low memory access efficiency due to improper memory address configuration. In particular, software configuration is required at the MCU factory, which increases development difficulty and hinders subsequent modifications.
By obtaining memory configuration information, and based on the memory decoding mode bits and memory access validity bits, the address decoding mapping relationship between the kernel and memory blocks is determined, and the memory access mode is dynamically adjusted to avoid the kernel accessing the same memory block at the same time.
It reduces the difficulty of software compilation, decreases the probability of bus conflicts, improves memory access efficiency, and simplifies the memory configuration process.
Smart Images
Figure CN115422096B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, specifically to a memory access method, apparatus, chip, and computer-readable storage medium. Background Technology
[0002] With the increasing demands on MCUs from applications such as the Internet of Things (IoT), industrial control, and automotive electronics, the use of dual-core and multi-core MCUs is becoming more widespread. There are many ways to implement a dual-core MCU, such as heterogeneous dual-core, homogeneous dual-core, and dual-core secure mode. Regardless of the implementation method, a dual-core MCU typically uses multiple RAM blocks to form the memory of the dual-core system. The virtual address is decoded and mapped to the physical address using the same mapping method to select the target RAM to operate on. To ensure the operation of the dual-core system, some RAM is usually allocated to each of the two cores, while some RAM can be shared between them. This RAM allocation can be achieved by setting the base address of the RAM for each core during software design. However, if the allocated address is not aligned with the physical address of the RAM, it may cause both cores to access the same RAM block simultaneously, reducing memory access speed. The current solution is to set each RAM to the system's RAM base address during software compilation, without considering the base address of each kernel's RAM. Then, by loading an offset address, a fixed-size offset is added to the virtual address accessed by one of the kernels to perform memory access. This ensures that when two kernels are running, there will be no conflict caused by both kernels accessing the same physical address of RAM at the same time, thus affecting memory access efficiency.
[0003] In conceiving and implementing this application, the inventors discovered at least the following problems: Although the prior art can ensure that two cores will not access the same physical address of RAM at the same time during operation, this method requires writing the offset address of the core at the factory of the MCU and loading it into the offset address module after power-on after writing to the flash memory. This requires developers to perform software configuration at the factory of the MCU, which not only increases the workload of software development and the difficulty of software compilation, but also makes it difficult to modify the configuration later. In addition, the prior art is also prone to bus conflicts caused by improper configuration, which affects the efficiency of system memory access.
[0004] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention
[0005] To address the aforementioned technical problems, this application provides a memory access method, apparatus, chip, and computer-readable storage medium that determines the mapping relationship between different memory blocks and their corresponding virtual addresses in each kernel based on memory configuration information. This reduces the difficulty of software compilation, lowers the probability of bus conflicts caused by improper configuration, and thus improves the efficiency of memory access.
[0006] To address the aforementioned technical problems, this application provides a memory access method, comprising the following steps:
[0007] In response to a reset request, obtain memory configuration information, which includes at least memory decoding mode bits and memory access valid bits;
[0008] Based on the memory configuration information, the address decoding mapping relationship between the kernel and memory blocks is determined;
[0009] Based on the address decoding mapping relationship and the kernel's virtual address, the kernel is controlled to initiate memory access.
[0010] Optionally, after responding to the reset request and before obtaining the memory configuration information, the memory access method further includes:
[0011] Obtain memory configuration data from flash memory, and extract the corresponding memory configuration information from the memory configuration data.
[0012] Optionally, prior to responding to the reset request, the memory access method further includes:
[0013] Multiple memory blocks are classified and labeled as shared memory blocks and non-shared memory blocks.
[0014] Optionally, determining the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information includes:
[0015] According to the preset configuration rules, the memory decoding mode bit and memory access valid bit in the memory configuration information are identified;
[0016] Based on the memory decoding mode bits, memory access validity bits, and kernel virtual addresses, the address decoding mapping relationship of each memory block corresponding to the virtual addresses of different kernels is determined.
[0017] Optionally, determining the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels based on the memory decoding mode bit, the memory access valid bit, and the kernel's virtual address includes:
[0018] If the memory decoding mode bit is the first preset value and all memory access valid bits are valid values, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the first preset mapping relationship;
[0019] If the memory decoding mode bit is the second preset value, and all memory access valid bits are valid values, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the second preset mapping relationship;
[0020] If the memory decoding method bit is the first preset value, and any memory access valid bit is invalid, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the third preset mapping relationship;
[0021] If the memory decoding mode bit is the second preset value, and any memory access valid bit is valid, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the fourth preset mapping relationship.
[0022] Optionally, determining the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels based on the memory decoding mode bit, the memory access valid bit, and the kernel's virtual address further includes:
[0023] Obtain multiple virtual addresses from different kernels, and number and sort each memory block.
[0024] Optionally, controlling the kernel to initiate memory access based on the address decoding mapping relationship and the kernel's virtual address includes:
[0025] Obtain the virtual addresses of each kernel;
[0026] Based on the address decoding mapping relationship, determine the address decoding corresponding to the virtual address of each kernel;
[0027] The address decoding controls each kernel's access to the corresponding memory block.
[0028] Accordingly, this application also provides a memory access device, including:
[0029] The acquisition module is used to respond to a reset request and acquire memory configuration information, which includes at least memory decoding mode bits and memory access valid bits.
[0030] The mapping module is used to determine the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information.
[0031] The control module is used to control the kernel to initiate memory access based on the address decoding mapping relationship and the kernel's virtual address.
[0032] This application also proposes a chip including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the memory access method described above.
[0033] This application also proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the memory access method described above.
[0034] Implementing the embodiments of this application has the following beneficial effects:
[0035] As described above, this application provides a memory access method, apparatus, chip, and computer-readable storage medium. The method includes: responding to a reset request and obtaining memory configuration information, which includes at least memory decoding mode bits and memory access valid bits; determining the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information; and controlling the kernel to initiate memory access according to the address decoding mapping relationship and the kernel's virtual address. The memory access scheme in this application determines the mapping relationship between different memory blocks and their corresponding virtual addresses in each kernel based on the memory configuration information, and controls the kernel to initiate memory access according to the mapping relationship. It does not require consideration of the base address information of the memory blocks the kernel needs to access, nor does it require consideration of the offset address corresponding to the kernel. Programs can be compiled according to the base address of the system memory blocks, thus reducing the difficulty of software compilation, reducing the probability of bus conflicts caused by improper configuration, and improving the efficiency of memory access. Attached Figure Description
[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.
[0037] Figure 1 This is a flowchart illustrating the first implementation of the memory access method provided in this application.
[0038] Figure 2 This is a flowchart illustrating a second implementation of the memory access method provided in this application.
[0039] Figure 3 This is a flowchart illustrating a third implementation of the memory access method provided in this application.
[0040] Figure 4 This is a flowchart illustrating the fourth implementation of the memory access method provided in this application.
[0041] Figure 5 This is a schematic diagram of the structure of the memory access device provided in the embodiments of this application;
[0042] Figure 6 This is a schematic diagram of the structure of the memory access system provided in the embodiments of this application;
[0043] Figure 7 This is a schematic diagram of the chip structure provided in the embodiments of this application;
[0044] Figure 8 This is a schematic block diagram of the device provided in the embodiments of this application.
[0045] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation
[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0047] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.
[0048] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word “if” as used herein may be interpreted as “when…” or “in response to determination”. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or,” “and / or,” “including at least one of the following,” etc., as used in this application may be interpreted as inclusive, or mean any one or any combination thereof. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C." Similarly, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C." Exceptions to this definition only occur when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.
[0049] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.
[0050] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”
[0051] It should be noted that step designations such as S1 and S2 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the protection scope of this application.
[0052] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0053] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.
[0054] To better understand the embodiments of this application, the following are relevant technical terms and their explanations.
[0055] MCU: Micro Control Unit;
[0056] RAM: Random Access Memory;
[0057] CORE: kernel;
[0058] Virtual address: The address sent by the CPU core to read program data;
[0059] Physical address: The address used when accessing a peripheral device;
[0060] Address mapping: a method for translating virtual addresses into physical addresses;
[0061] Dual-core MCU: The MCU integrates two cores, which can be the same core or different cores.
[0062] First, this application introduces the application scenarios that can be provided, such as providing a memory access method, device, chip, and computer-readable storage medium, which determines the mapping relationship between different memory blocks and the virtual addresses corresponding to each kernel based on memory configuration information, reduces the difficulty of software compilation, reduces the probability of bus conflicts caused by improper configuration, and thus improves the efficiency of memory access.
[0063] Please see Figure 1 , Figure 1 This is a flowchart illustrating a memory access method provided in an embodiment of this application. Specifically, the memory access method may include:
[0064] S1. Respond to the reset request and obtain memory configuration information, which includes at least the memory decoding mode bit and the memory access valid bit.
[0065] Specifically, for step S1, in response to the reset request, after the multi-core system completes the reset operation according to the reset request received, it obtains memory configuration information, which includes at least the memory decoding mode bit and the memory access validity bit corresponding to multiple kernels.
[0066] The memory decoding mode bit can be 16 or more data register bits, which can be obtained by loading from flash memory or by software configuration. Each data register bit corresponds to a physical memory block in a multi-core system. When the data register bit is 1, it means that the address mapping methods of the multiple cores corresponding to the memory block are different. When the data register bit is 0, it means that the address mapping methods of the multiple cores corresponding to the memory block are the same.
[0067] The memory access valid bits can be 16 bits or more of data register bits, which can be obtained by loading from flash memory or by software configuration. Each data register bit corresponds to a physically existing memory block in a multi-core system, representing the access permissions of different kernels to that memory block. When the data register bit is 1, it means that the target kernel can access the memory block corresponding to that data register bit; when the data register bit is 0, it means that the target kernel cannot access the memory block corresponding to that data register bit. It should be noted that the memory access valid bits in this embodiment include at least two kernel memory access valid bits.
[0068] Optionally, in some embodiments, after responding to a reset request and before obtaining memory configuration information, the memory access method may further include:
[0069] Retrieve memory configuration data from flash memory and extract the corresponding memory configuration information from the memory configuration data.
[0070] Specifically, after the multi-core system responds to the reset request and before obtaining the memory configuration information, it also includes obtaining the memory configuration data in the flash memory. First, by loading the memory configuration data in the flash memory, the corresponding built-in configuration information, including the memory decoding mode bit and the memory access valid bit corresponding to multiple kernels, is extracted from the memory configuration data according to the preset extraction rules.
[0071] Optionally, in some embodiments, the memory access method may further include, prior to responding to a reset request:
[0072] Multiple memory blocks are classified and labeled as shared memory blocks and non-shared memory blocks.
[0073] Specifically, before the multi-core system responds to the reset request, it is necessary to classify multiple memory blocks according to the specific address information of the memory blocks in the multi-core system before the chip starts up, to determine which memory blocks are shared memory blocks and which are non-shared memory blocks, to mark the classified shared memory blocks and non-shared memory blocks, and to configure the specific address information of the shared memory blocks and non-shared memory blocks into the flash memory, so that the flash memory option data is automatically loaded into the memory configuration information after the multi-core system performs a reset action.
[0074] S2. Based on memory configuration information, determine the address decoding mapping relationship between the kernel and memory blocks.
[0075] Specifically, for step S2, based on the acquired memory configuration information, the memory access configuration device determines the address decoding mapping relationship between multiple kernels and different memory blocks according to the memory configuration information, that is, determines the mapping relationship between different memory blocks and the corresponding virtual addresses of each kernel.
[0076] Optionally, in some embodiments, step S2 may specifically include:
[0077] S21. Identify the memory decoding mode bit and memory access valid bit in the memory configuration information according to the preset configuration rules;
[0078] S22. Based on the memory decoding mode bit, the memory access valid bit, and the kernel's virtual address, determine the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels.
[0079] Specifically, since the memory configuration information is obtained by automatically loading flash option data according to preset configuration rules after the system reset, before determining the mapping relationship, it is first necessary to identify the memory decoding mode bit and memory access valid bit in the memory configuration information according to the preset configuration rules. Then, based on the memory decoding mode bit and memory access valid bit, combined with the virtual addresses corresponding to multiple kernels, the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined.
[0080] Optionally, in some embodiments, step S22 may further include: obtaining multiple virtual addresses of different kernels, and numbering and sorting each memory block.
[0081] Specifically, before determining the address decoding mapping relationship of each memory block to the virtual address of different kernels, we first obtain multiple virtual addresses of all kernels in the multi-core system, then list all memory blocks in the multi-core system, assign them numbers, and sort them according to the number order.
[0082] Optionally, in some embodiments, step S22 may specifically include:
[0083] If the memory decoding mode bit is the first preset value and all memory access valid bits are valid values, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the first preset mapping relationship.
[0084] If the memory decoding mode bit is the second preset value and all memory access valid bits are valid values, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the second preset mapping relationship;
[0085] If the memory decoding mode bit is the first preset value, and any memory access valid bit is invalid, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the third preset mapping relationship;
[0086] If the memory decoding mode bit is the second preset value, and any memory access valid bit is valid, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the fourth preset mapping relationship.
[0087] Specifically, this embodiment also provides address decoding mapping relationships in four cases, taking two kernels CORE0 and CORE1 as examples.
[0088] When the value of the memory decoding mode bit is the first preset value, which is a high value, and when it is determined that the memory access validity bits of kernel CORE0 and CORE1 are both valid values, that is, kernel CORE0 and CORE1 can access the target memory block, the decoding modes of the two kernels are different. The virtual address sent by kernel CORE0 is decoded in a low-to-high manner, that is, the sequence number of the memory block corresponding to the low-to-high virtual address is also decoded in a low-to-high manner; the virtual address sent by kernel CORE1 is decoded in a high-to-low manner, that is, the sequence number of the memory block corresponding to the low-to-high virtual address is decoded in a high-to-low manner.
[0089] When the value of the memory decoding mode bit is the second preset value, the second preset value is a low value, and when it is determined that the memory access validity bits of kernel CORE0 and CORE1 are both valid values, that is, kernel CORE0 and CORE1 can access the target memory block, kernel CORE0 and CORE1 will use the same address decoding mapping method, that is, the sequence number of the memory block corresponding to the virtual address from low to high is also decoded from low to high.
[0090] When the value of the configured memory decoding mode bit is the first preset value, and any or both of the memory access validity bits of kernel CORE0 or CORE1 are invalid, it will be considered that both CORE0 and CORE1 accesses are valid, that is, the value of the RAM decoding mode has higher priority.
[0091] When the memory decoding mode bit is configured to the second preset value, if the memory access validity bit of kernel CORE0 is valid, decoding is performed by ascending the sequence number of the memory block corresponding to the virtual address, and only the virtual address issued by kernel CORE0 is decoded; if the memory access validity bit of kernel CORE1 is valid, decoding is performed by descending the sequence number of the memory block corresponding to the virtual address, and only the virtual address issued by kernel CORE1 is decoded.
[0092] For step S2, this embodiment sets different decoding methods and kernel memory access validity bits according to the different access requirements of multi-core systems for memory blocks, thereby determining the address decoding mapping relationship of each memory block corresponding to the virtual address of different kernels and performing decoding mapping.
[0093] S3. Based on the address decoding mapping relationship and the kernel's virtual address, control the kernel to initiate memory access.
[0094] Specifically, for step S3, based on the address decoding mapping relationship between multiple kernels and different memory blocks, and the virtual addresses corresponding to multiple kernels, the target kernel is controlled to initiate memory access.
[0095] Optionally, such as Figure 2 As shown, in some embodiments, step S3 may specifically include:
[0096] S31. Obtain the virtual addresses of each kernel;
[0097] S32. Determine the address decoding corresponding to the virtual address of each kernel according to the address decoding mapping relationship;
[0098] S33. Control each kernel to access the corresponding memory block based on address decoding.
[0099] Specifically, in this embodiment, all virtual addresses issued by each kernel are first obtained. Based on the determined address decoding mapping relationship between multiple kernels and different memory blocks, the address decoding corresponding to all virtual addresses of each kernel is determined. Finally, based on the address decoding, each kernel is controlled to initiate memory access and access the corresponding memory block. This way, the software program does not need to consider the base address of the memory used by CORE0 and CORE1, and can be compiled according to the base address RAM_BASE of the multi-core system memory. It also does not need to consider the offset address corresponding to each kernel. Therefore, the difficulty of software compilation is reduced, the probability of bus conflicts caused by improper configuration is reduced, and the efficiency of system memory access is improved.
[0100] Specifically, this embodiment also provides another implementation of the memory access method. The specific process includes: after the system reset is completed, the system flash option data is automatically loaded into the memory decoding mode bit and the memory access valid bit of kernel CORE0 and CORE1. After the data is loaded, kernel CORE0 and CORE1 simultaneously initiate access to their respective memory blocks. Based on the virtual address initiated by kernel CORE0 and CORE1, combined with the above-mentioned memory decoding mode bit and the memory access valid bit of kernel CORE0 and CORE1, the memory block access address is decoded and mapped to the corresponding memory block. Kernel CORE0 and CORE1 access different memory blocks by sending the same virtual address, and simultaneously obtain the target data of the memory block.
[0101] To better understand the memory access scheme of this application, the following provides specific implementation methods under two different scenarios. Please refer to [link / reference]. Figure 3 and Figure 4 .
[0102] (1) As Figure 3 As shown, the dual-core system has four independent memory blocks (RAM0, RAM1, RAM2, and RAM3), all shared by both cores. Assume each memory block is 32KB. The system RAM base address is 0x20000000. Based on the system requirements, the RAM decoding mode selection bit is set in the flash memory byte options. Since the system has only four independent RAM blocks, the lower four bits are set to be valid. The memory access validity bits for kernels CORE and CORE1 are optional. To ensure both cores can run normally, each core can be configured to use two RAM blocks (64KB of space). CORE0 uses a program written for the application, with its compilation base address set to 0x20000000; CORE1 also uses a program written for the application, with its compilation base address also set to 0x20000000. After compilation, the programs are downloaded to their respective flash memory spaces. After power-on reset, each program is executed. When kernel CORE0 and CORE1 simultaneously access RAM, that is, when they access the 64KB space above 0x20000000, because the address decoding and mapping module and RAM decoding mode selection work simultaneously, CORE0 accesses RAM0 (32KB) and RAM1 (32KB); although CORE1 accesses the same virtual address space, it accesses RAM3 and RAM2.
[0103] (2) Figure 4As shown, the dual-core system has three memory blocks, with sizes RAM0-32KB, RAM1-16KB, and RAM3-32KB respectively. RAM1 is shared RAM, used for data exchange between cores CORE0 and CORE1. RAM0 is the memory RAM for CORE0, and RAM2 is the memory RAM for CORE1. The starting address of the system RAM is 0x20008000. Based on the above system information, the memory decoding mode selection bit is set in the flash option data. The system has three RAM blocks: RAM0 is allocated to CORE0, RAM2 is allocated to CORE1, and RAM1 is shared by both CORE0 and CORE1. Therefore, the memory decoding mode is set to "lower 3 bits valid", with a value of 'b101. Simultaneously, the lower 3 bits of the access validity bits for CORE0 and CORE1 can be configured to be 'b111'. This means that CORE0 initiates access to RAM0 starting at address 0x20008000; accesses RAM1 starting at address 0x20010000; and accesses RAM2 starting at address 0x20014000. Similarly, CORE1 initiates access to RAM0 starting at address 0x20014000; accesses RAM1 starting at address 0x20010000; and accesses RAM2 starting at address 0x20008000.
[0104] After implementing the above scheme, the software only needs to write programs according to the applications of each core, compiling the programs according to the RAM base address 0x20008000 and downloading them to their respective flash memory. When the two cores start executing their respective programs, although they all access the RAM at 0x20008000, they access different RAM physical modules, reducing the probability of software errors, reducing bus conflicts, and improving memory access efficiency.
[0105] As can be seen from the above, the memory access method provided in this application includes: responding to a reset request and obtaining memory configuration information, which includes at least memory decoding mode bits and memory access valid bits; determining the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information; and controlling the kernel to initiate memory access according to the address decoding mapping relationship and the kernel's virtual address. The memory access scheme in this application determines the mapping relationship between different memory blocks and their corresponding virtual addresses in each kernel based on the memory configuration information, and controls the kernel to initiate memory access according to the mapping relationship. It does not require consideration of the base address information of the memory blocks the kernel needs to access, nor does it require consideration of the offset address corresponding to the kernel. Programs can be compiled according to the base address of the system memory blocks, thus reducing the difficulty of software compilation, reducing the probability of bus conflicts caused by improper configuration, and improving the efficiency of memory access.
[0106] Accordingly, this application also provides a memory access device; please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of the memory access device provided in this application, which may specifically include an acquisition module 100, a mapping module 200, and a control module 300.
[0107] The acquisition module 100 is used to respond to a reset request and acquire memory configuration information, which includes at least memory decoding mode bits and memory access valid bits.
[0108] Specifically, the acquisition module 100 is used to respond to reset requests. After the multi-core system completes the reset operation based on the reset request received by the reset, it acquires memory configuration information. This memory configuration information includes at least the memory decoding mode bit and the memory access validity bit corresponding to multiple kernels.
[0109] The mapping module 200 is used to determine the address decoding mapping relationship between the kernel and memory blocks based on memory configuration information.
[0110] Specifically, the mapping module 200 is used to determine the address decoding mapping relationship between multiple kernels and different memory blocks based on the acquired memory configuration information, through the memory access configuration device, that is, to determine the mapping relationship between different memory blocks and the corresponding virtual addresses of each kernel.
[0111] Optionally, in some embodiments, the mapping module 200 may further include:
[0112] The identification unit is used to identify the memory decoding mode bit and memory access valid bit in the memory configuration information according to the preset configuration rules;
[0113] The mapping determination unit is used to determine the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels based on the memory decoding mode bit, the memory access valid bit, and the kernel's virtual address.
[0114] The sorting unit is used to obtain multiple virtual addresses from different kernels and to sort the memory blocks after numbering them.
[0115] Optionally, in some embodiments, the mapping determination unit may further include:
[0116] The first mapping subunit is used to determine the address decoding mapping relationship of each memory block in different kernels as the first preset mapping relationship if the memory decoding mode bit is the first preset value and each memory access valid bit is a valid value.
[0117] The second mapping subunit is used to determine the address decoding mapping relationship of each memory block in different kernels as the second preset mapping relationship if the memory decoding mode bit is the second preset value and each memory access valid bit is a valid value.
[0118] The third mapping subunit is used to determine the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels as the third preset mapping relationship if the memory decoding mode bit is the first preset value and any memory access valid bit is invalid.
[0119] The fourth mapping subunit is used to determine the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels as the fourth preset mapping relationship if the memory decoding mode bit is the second preset value and any memory access valid bit is a valid value.
[0120] The control module 300 is used to control the kernel to initiate memory access based on the address decoding mapping relationship and the kernel's virtual address.
[0121] Specifically, the control module 300 is used to control the target kernel to initiate memory access based on the address decoding mapping relationship between multiple kernels and different memory blocks, as well as the virtual addresses corresponding to multiple kernels.
[0122] Optionally, in some embodiments, the control module 300 may further include:
[0123] The address acquisition unit is used to acquire the virtual addresses of each kernel.
[0124] The address decoding unit is used to determine the address decoding corresponding to the virtual address of each kernel according to the address decoding mapping relationship;
[0125] The access unit is used to control each kernel to access the corresponding memory block based on address decoding.
[0126] Optionally, in some embodiments, the memory access device may further include:
[0127] The extraction module is used to obtain memory configuration data from flash memory and extract the corresponding memory configuration information from the memory configuration data.
[0128] The classification module is used to classify multiple memory blocks and mark them as shared memory blocks and non-shared memory blocks.
[0129] In summary, the memory access device provided in this application embodiment involves the acquisition module 100 responding to a reset request and acquiring memory configuration information, which includes at least memory decoding mode bits and memory access valid bits; the mapping module 200 determining the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information; and the control module 300 controlling the kernel to initiate memory access based on the address decoding mapping relationship and the kernel's virtual address. Therefore, the memory access device in this application embodiment determines the mapping relationship between different memory blocks and their corresponding virtual addresses in each kernel based on the memory configuration information, and controls the kernel to initiate memory access based on the mapping relationship. It does not require consideration of the base address information of the memory blocks the kernel needs to access, nor does it require consideration of the offset address corresponding to the kernel. Programs can be compiled according to the base address of the system memory blocks, thus reducing the difficulty of software compilation, reducing the probability of bus conflicts caused by improper configuration, and improving the efficiency of memory access.
[0130] To facilitate a further understanding of the memory access method of this application, embodiments of this application also provide a memory access system, such as... Figure 6 As shown, this memory access system is integrated within a multi-core system and includes a RAM configuration auto-loading device and an address decoding and mapping device. The RAM configuration auto-loading device configures the address mapping method of the system's physical RAM (memory) blocks. Initial values can be automatically loaded from flash memory or configured via software. This device outputs corresponding data based on the number of physical RAM blocks in the system, with each bit corresponding to one RAM block. It also outputs CORE0 RAM configuration bits and CORE1 RAM configuration bits, which can be used to configure which CORE owns a RAM block. The address decoding and mapping device determines whether each RAM block belongs to CORE0, CORE1, or is jointly owned, based on the output of the configuration device. Then, based on these ownership determinations, it determines the address mapping method of the RAM blocks for each CORE. This way, when software applications are written for their respective COREs, it is not necessary to consider the base address of the RAM corresponding to each CORE; the starting address of the system RAM can be used as the base address of memory during compilation. This reduces RAM access conflicts caused by improper software configuration and improves the efficiency of bus memory access.
[0131] This application embodiment also provides a chip, including a memory 10 and a processor 20, the schematic diagram of which is shown below. Figure 7As shown. The memory 10 stores a computer program, and when the processor 20 executes the computer program, it implements a memory access method as described above, including: responding to a reset request, obtaining memory configuration information, which includes at least memory decoding mode bits and memory access valid bits; determining the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information; and controlling the kernel to initiate memory access according to the address decoding mapping relationship and the kernel's virtual address.
[0132] This application also provides a device, which may be a server, and its structural diagram is shown below. Figure 8 As shown. The device includes a processor, memory, network interface, and database connected via a system bus. The processor is designed to provide computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data such as memory access methods. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a memory access method. The memory access method includes: responding to a reset request, obtaining memory configuration information, which includes at least memory decoding mode bits and memory access valid bits; determining the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information; and controlling the kernel to initiate memory access according to the address decoding mapping relationship and the kernel's virtual address.
[0133] One embodiment of this application also provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements a memory access method, including the steps of: responding to a reset request and obtaining memory configuration information, the memory configuration information including at least a memory decoding mode bit and a memory access valid bit; determining the address decoding mapping relationship between the kernel and memory blocks based on the memory configuration information; and controlling the kernel to initiate memory access according to the address decoding mapping relationship and the kernel's virtual address.
[0134] The memory access method described above determines the mapping relationship between different memory blocks and their corresponding virtual addresses in each kernel based on memory configuration information, and controls the kernel to initiate memory access according to the mapping relationship. It does not need to consider the base address information of the memory block to be accessed by the kernel, nor does it need to consider the offset address corresponding to the kernel. The program can be compiled according to the base address of the system memory block. Therefore, it can reduce the difficulty of software compilation, reduce the probability of bus conflicts caused by improper configuration, and improve the efficiency of memory access.
[0135] It is understood that the above scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0136] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0137] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.
[0138] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.
[0139] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.
[0140] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0141] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.
[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, controlled terminal, or network device, etc.) to execute the methods of each embodiment of this application.
[0143] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, storage disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).
[0144] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A memory access method, characterized in that, Includes the following steps: In response to a reset request, the system retrieves memory configuration data from the flash memory and extracts corresponding memory configuration information from the memory configuration data. The memory configuration information includes at least memory decoding mode bits and memory access valid bits. Each data register bit of the memory decoding mode bits corresponds to a physically existing memory block and is used to indicate whether the address mapping methods of multiple kernels corresponding to the memory block are the same. Each data register bit of the memory access valid bits corresponds to a physically existing memory block and is used to indicate the access permissions of different kernels to the memory block. According to the preset configuration rules, the memory decoding mode bit and memory access valid bit in the memory configuration information are identified; Based on the memory decoding mode bits, memory access valid bits, and kernel virtual addresses, the address decoding mapping relationship of each memory block corresponding to the virtual addresses of different kernels is determined; Based on the address decoding mapping relationship and the kernel's virtual address, the kernel is controlled to initiate memory access.
2. The memory access method according to claim 1, characterized in that, Prior to responding to the reset request, the memory access method further includes: Multiple memory blocks are classified and labeled as shared memory blocks and non-shared memory blocks.
3. The memory access method according to claim 1, characterized in that, The step of determining the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels based on the memory decoding mode bits, memory access valid bits, and kernel virtual addresses includes: If the memory decoding mode bit is the first preset value and all memory access valid bits are valid values, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the first preset mapping relationship; If the memory decoding mode bit is the second preset value, and all memory access valid bits are valid values, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the second preset mapping relationship; If the memory decoding method bit is the first preset value, and any memory access valid bit is invalid, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the third preset mapping relationship; If the memory decoding mode bit is the second preset value, and any memory access valid bit is valid, then the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels is determined to be the fourth preset mapping relationship.
4. The memory access method according to claim 1, characterized in that, The step of determining the address decoding mapping relationship of each memory block corresponding to the virtual address in different kernels based on the memory decoding mode bits, memory access valid bits, and kernel virtual addresses further includes: Obtain multiple virtual addresses from different kernels, and number and sort each memory block.
5. The memory access method according to claim 1, characterized in that, The step of controlling the kernel to initiate memory access based on the address decoding mapping relationship and the kernel's virtual address includes: Obtain the virtual addresses of each kernel; Based on the address decoding mapping relationship, determine the address decoding corresponding to the virtual address of each kernel; The address decoding controls each kernel's access to the corresponding memory block.
6. A memory access device, characterized in that, include: The acquisition module is used to respond to a reset request, acquire memory configuration data in flash memory, and extract corresponding memory configuration information from the memory configuration data. The memory configuration information includes at least memory decoding mode bits and memory access valid bits. Each data register bit of the memory decoding mode bits corresponds to a physically existing memory block and is used to indicate whether the address mapping methods of multiple kernels corresponding to the memory block are the same. Each data register bit of the memory access valid bits corresponds to a physically existing memory block and is used to indicate the access permission information of different kernels to the memory block. The mapping module is used to identify the memory decoding mode bit and memory access valid bit in the memory configuration information according to preset configuration rules; and to determine the address decoding mapping relationship of each memory block corresponding to the virtual address of different kernels based on the memory decoding mode bit, memory access valid bit and the kernel virtual address. The control module is used to control the kernel to initiate memory access based on the address decoding mapping relationship and the kernel's virtual address.
7. A chip comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the memory access method according to any one of claims 1 to 5.
8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the memory access method according to any one of claims 1 to 5.