A multi-constrained impedance optimization method for 2.5-dimensional integrated circuits based on kernel particles

Abstract

The application discloses a kind of multi-constraint impedance optimization methods of 2.5-dimensional integrated circuit based on core particle, comprising the following steps: constructing the equivalent circuit model of 2.5-dimensional integrated circuit comprising multiple parasitic parameters, obtaining the impedance matrix of equivalent circuit model;According to target impedance Z target,f And impedance matrix constructs impedance target function;According to equivalent circuit model, construct first constraint, second constraint and third constraint;According to impedance target function, first constraint, second constraint and third constraint, construct mixed target function;According to mixed target function and the PDN parameter of equivalent circuit model, determine the minimum value of mixed target function and the target position of corresponding core particle, the target capacitance quantity in interposer and the position of target capacitance.The optimization method of the application reduces system impedance, further reduces the synchronous switching noise of system, and improves the performance of 2.5-dimensional integrated circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a multi-constraint impedance optimization method for a 2.5-dimensional integrated circuit based on a core particle. BACKGROUND

[0002] In the past decade, the process of small-scale integration of integrated circuits has gradually slowed down, so the industry has begun to seek alternative solutions to the "beyond Moore" scheme. Chip stacking technologies such as 2.5-dimensional integrated circuits (2.5-D IC) and 3-dimensional integrated circuits (3-D IC) have developed rapidly in recent years. At the same time, these multi-chip systems are the most cost-effective alternatives to single-chip systems (also known as 2-dimensional systems), because the decomposition of a chip into multiple chips can alleviate the problems of low yield and insufficient production capacity of large 2-dimensional chips. In a 2.5-dimensional integrated circuit, a single SoC (System-on-Chip) is divided into multiple functional modules, called "core particles", and each core particle is integrated in an interposer. All interconnections and signal transmissions between core particles are carried out in the interposer.

[0003] Currently, in 2.5-dimensional integrated circuits, with the increase of data volume and the increase of frequency, the influence of simultaneous switching noise on the circuit cannot be ignored. Reducing system impedance is the most effective and most intuitive method to eliminate simultaneous switching noise (SSN), and decoupling capacitors are the most convenient and effective solution to reduce the impedance of the power distribution network. In the traditional board-level and three-dimensional integrated circuit power distribution network (PDN) engineering, there are various optimal decoupling design methods, which discuss the placement of capacitors to reduce system impedance. For example, H. Park et al. in the article "Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D / 3-D ICs," (DOI: 10.1109 / TCPMT.2020.2972019.) S. Piersanti et al. in the article "Decoupling Capacitors Placement for a Multichip PDN by a Nature-Inspired Algorithm," (DOI: 10.1109 / TEMC.2017.2770089) discuss the distribution of decoupling capacitors for 3-dimensional integrated circuit interposer and on-chip, I. Erdin et al. in the article "Multi-Objective Optimization of Decoupling Capacitors for Placement and Component Value," (DOI: 10.1109 / TCPMT.2019.2930565) J. Wang et al. in the article "Multiport PDN Optimization With the Newton-Hessian Minimization Method," (DOI: 10.1109 / TMTT.2021.3057236) discuss the distribution of board-level decoupling capacitors. However, due to the existence of the core particles, for 2.5-dimensional integrated circuits, only considering the placement of capacitors leads to poor system performance. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides a multi-constraint impedance optimization method for a 2.5-dimensional integrated circuit based on core particles. The technical problem to be solved by the application is solved by the following technical scheme:

[0005] A multi-constraint impedance optimization method for a 2.5D integrated circuit based on a core particle, comprising the following steps:

[0006] An equivalent circuit model of a 2.5D integrated circuit containing multiple parasitic parameters is constructed, and an impedance matrix of the equivalent circuit model is obtained; the impedance matrix is a set of actual impedances Z f corresponding to a set of working frequencies Γ;

[0007] An impedance objective function is constructed according to a target impedance Z target,f and the impedance matrix; the target impedance Z target,f is the maximum self-impedance allowed on the load side of the core particle corresponding to the working frequency;

[0008] A first constraint, a second constraint and a third constraint are constructed according to the positions of the core particles of the 2.5D integrated circuit and the positions of the ports on the core particles; the first constraint indicates a constraint based on the minimization of the sum of the lengths of multiple interconnection lines between the ports between the core particles; the second constraint indicates a single interconnection line length constraint based on a preset maximum length constraint of the interconnection line; the third constraint indicates a distance constraint based on a minimum distance constraint between two adjacent core particles;

[0009] A hybrid objective function is constructed according to the impedance objective function, the first constraint, the second constraint and the third constraint;

[0010] The minimum value of the hybrid objective function and the target positions of the core particles, the target number of capacitors in the interposer and the positions of the target capacitors are determined according to the hybrid objective function and the PDN parameters of the equivalent circuit model.

[0011] In an embodiment of the present application, the impedance objective function is represented by formula (3):

[0012]

[0013] Wherein, ψ1 represents the sum of the differences between the actual impedances Z f corresponding to the set of working frequencies Γ and the target impedance Z target,f , when the actual impedance Z f is always less than the target impedance Z target,f , ψ1=0; ψ2 represents the number of decoupling capacitors placed in the interposer; ψ3 is the sum of all actual impedances Z f in the impedance matrix; respectively represent the weight coefficients of ψ1, ψ2 and ψ3;

[0014]

[0015] ψ2=N C (5)

[0016]

[0017] and the impedance objective function satisfies the constraints of formulas (7)-(13):

[0018]

[0019]

[0020]

[0021]

[0022]

[0023] C unit ≥ 0 (12)

[0024] N C ∈ N + (13)

[0025] wherein X i , Y i represent the coordinates at the midpoint of the i-th core particle, X j , Y j represent the coordinates at the midpoint of the j-th core particle, a i , β i represent the length of the i-th core particle in the horizontal coordinate axis direction and the vertical coordinate axis direction, a j , β j represent the length of the j-th core particle in the horizontal coordinate axis direction and the vertical coordinate axis direction, A, B represent the length of the interposer in the horizontal coordinate axis direction and the vertical coordinate axis direction; C unit represents the capacitance value of the decoupling capacitor placed in the interposer; N + represents a positive integer.

[0026] In an embodiment of the present application, the first constraint is represented as formula (14):

[0027]

[0028] wherein λ1 represents the first constraint, represents the length of the interconnection line between the p-th port on the i-th core particle and the q-th port on the j-th core particle, and Q represents the set of all ports on all core particles of the 2.5-dimensional integrated circuit;

[0029]

[0030] x i,p , y i,p represent the coordinates of the p-th port on the i-th core particle, xj,q y j,q represents the coordinate of the qth port on the jth core particle.

[0031] In an embodiment of the present application, the second constraint is represented as formula (16):

[0032]

[0033] wherein λ2 represents the second constraint, represents the maximum length of the preset interconnection line.

[0034] In an embodiment of the present application, the third constraint is represented as formula (17):

[0035]

[0036] wherein λ3 represents the third constraint;

[0037]

[0038]

[0039] k represents the minimum distance constraint between two adjacent core particles, represents the penalty of the minimum distance constraint k in the horizontal coordinate axis direction, represents the penalty of the minimum distance constraint k in the vertical coordinate axis direction;

[0040] if then χ1, χ2 = 0;

[0041] if then χ1, χ2 = 0;

[0042] if then χ1 = 1, χ2 = 0;

[0043] if then χ1 = 0, χ2 = 1.

[0044] In an embodiment of the present application, the hybrid objective function is represented as formula (20):

[0045]

[0046] wherein Λ represents the penalty function, and θ represents the weight of the penalty function;

[0047]

[0048] represents the weight coefficient of λ1, λ2, and λ3.

[0049] In an embodiment of the present application, the determining the minimum value of the hybrid objective function and the corresponding target core particle position, the target capacitor number in the interposer and the target capacitor position according to the PDN parameters of the hybrid objective function and the equivalent circuit model comprises:

[0050] updating the speed and position of the particle in the PSO algorithm according to the PDN parameters of the hybrid objective function and the equivalent circuit model; the particle comprises the position of the core particle, the capacitor number in the interposer and the position of the capacitor;

[0051] updating the particle outside the boundary by the Metropolis criterion;

[0052] updating the optimal position of the particle and the optimal value of the hybrid objective function in the PSO algorithm;

[0053] performing mutation operation on the chromosome in the DE algorithm;

[0054] performing crossover operation on the chromosome in the DE algorithm;

[0055] updating the chromosome outside the boundary by the Metropolis criterion;

[0056] updating the optimal position of the particle and the optimal value of the hybrid objective function in the PSO algorithm until the termination condition is reached, and outputting the target function value of the hybrid objective function and the corresponding target position of the core particle, the target capacitor number in the interposer and the target capacitor position; wherein the target function value is the minimum value of the hybrid objective function.

[0057] Advantages of the present application:

[0058] The present application constructs a hybrid objective function through an impedance objective function, a first constraint, a second constraint and a third constraint. The impedance objective function is a nonlinear function about the core particle position, the capacitor layout, the actual impedance and the target impedance. By determining the minimum value of the hybrid objective function, the corresponding core particle and capacitor layout can be obtained, so that the optimal layout of the 2.5-dimensional integrated circuit is obtained. The optimization method of the present application reduces the system impedance, further reduces the synchronous switching noise of the system and improves the performance of the 2.5-dimensional integrated circuit.

[0059] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0060] Figure 1 is a flowchart of a multi-constraint impedance optimization method of a 2.5-dimensional integrated circuit based on a core particle provided by an embodiment of the present application;

[0061] Figure 2aPDN structure used by the core particle provided by the embodiment of the present application;

[0062] Figure 2b PDN structure used by the inserter provided by the embodiment of the present application;

[0063] Figure 2c PDN structure used by the TSV array provided by the embodiment of the present application;

[0064] Figure 2d Equivalent circuit model provided by the embodiment of the present application;

[0065] Figure 3 Relationship diagram of target impedance and working frequency provided by the embodiment of the present application;

[0066] Figure 4a Schematic diagram of the first constraint provided by the embodiment of the present application;

[0067] Figure 4b Schematic diagram of the second constraint provided by the embodiment of the present application;

[0068] Figure 4c Schematic diagram of the third constraint provided by the embodiment of the present application;

[0069] Figure 5 Flow chart of the MDP algorithm provided by the embodiment of the present application;

[0070] Figure 6a Cross-sectional view of the structure of the 2.5-dimensional PDN of the simulation experiment of the embodiment of the present application;

[0071] Figure 6b Top view of the structure of the 2.5-dimensional PDN of the simulation experiment of the embodiment of the present application;

[0072] Figure 7 Comparison of iteration efficiency of four algorithms using specific examples;

[0073] Figure 8 Schematic diagram of the optimization result of the simulation experiment of the embodiment of the present application. DETAILED DESCRIPTION

[0074] The present application will be further described in detail below with specific embodiments, but the embodiments of the present application are not limited thereto.

[0075] Embodiment one

[0076] As shown in the following, Figure 1 a multi-constraint impedance optimization method of a 2.5-dimensional integrated circuit based on a core particle, comprising the following steps:

[0077] Step 101, an equivalent circuit model of a 2.5D integrated circuit containing multiple parasitic parameters is constructed, and an impedance matrix of the equivalent circuit model is obtained; the impedance matrix is a set of actual impedances Z corresponding to a set of working frequencies Γ f .

[0078] Step 102, an impedance target function is constructed according to a target impedance Z target,f and the impedance matrix; the target impedance Z target,f is the maximum self-impedance allowed on the load side of the die in correspondence with the working frequency.

[0079] Step 103, a first constraint, a second constraint and a third constraint are constructed according to the positions of the dies of the 2.5D integrated circuit and the positions of the ports on the dies; the first constraint indicates a constraint based on the minimization of the sum of the lengths of multiple interconnection lines between the ports between the dies; the second constraint indicates a length constraint based on the maximum length constraint of the interconnection lines; and the third constraint indicates a distance constraint based on the minimum distance constraint between two adjacent dies.

[0080] Step 104, a mixed target function is constructed according to the impedance target function, the first constraint, the second constraint and the third constraint.

[0081] Step 105, the minimum value of the mixed target function and the target positions of the dies, the target number of capacitors in the interposer and the positions of the target capacitors are determined according to the PDN parameters of the equivalent circuit model of the mixed target function.

[0082] The present application constructs a mixed target function through an impedance target function, a first constraint, a second constraint and a third constraint, the mixed target function is a nonlinear function about the die positions, the capacitor layout, the actual impedance and the target impedance, by determining the minimum value of the mixed target function, the layout of the corresponding dies and capacitors is obtained, so that the optimal layout of the 2.5D integrated circuit is obtained, the optimization method of the present application reduces the system impedance, further reduces the synchronous switching noise of the system, and improves the performance of the 2.5D integrated circuit.

[0083] Embodiment two

[0084] A multi-constraint impedance optimization method for a die-based 2.5D integrated circuit, comprising the following steps:

[0085] Step 201, an equivalent circuit model of a 2.5D integrated circuit containing multiple parasitic parameters is constructed, and an impedance matrix of the equivalent circuit model is obtained; the impedance matrix is a set of actual impedances Z corresponding to a set of working frequencies Γ f .

[0086] 2.5D integrated circuit, the complete PDN is composed of PDN (Power distribution network) in interposer, PDN in die, TSV (Through Silicon Via) array, C4 ball array, micro ball array, decoupling capacitor, etc. Each part of the 2.5D integrated circuit is modeled, and then through a hierarchical cascading method, the Z parameter matrix of the whole circuit is obtained through matrix multiplication operation, as shown in Figure 2a , as shown in Figure 2b , as shown in Figure 2c , and as shown in Figure 2d . For specific modeling process, refer to the content in the prior art: J. Kim et al.,“Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method,”in IEEE Transactions on Advanced Packaging, vol. 33, no. 3, pp. 647-659, Aug. 2010. The Z parameter matrix is the impedance matrix of the equivalent circuit model. The interposer is a adapter board.

[0087] A mixed objective function is constructed by constraint analysis of the 2.5D integrated circuit, specifically, including steps 202-204:

[0088] Step 202, impedance target function is constructed according to target impedance Z target,f and impedance matrix; target impedance Z target,f is the maximum self-impedance allowed by the load side of the die corresponding to the working frequency.

[0089] The target impedance is composed of two parts, as shown in Figure 3 . The flat area is based on formula (1), and after point f knee , it is a slope area, and the target impedance curve increases at a rate of 20dB / dec.

[0090]

[0091]

[0092] Wherein, Z target represents the flat area of the target impedance, V ripple represents the ripple voltage of the load on the die, f knee represents the inflection point frequency, I represents the working current of the load on the die, and T rNoise signal period representing an equivalent circuit model.

[0093] In step 201, the impedance of the whole system is modeled by using the cascading method, and the impedance objective function Ψ is represented by formula (3):

[0094]

[0095] Wherein, ψ1 represents the sum of the difference between the actual impedance Z f and the target impedance Z target,f , when the actual impedance Z f is always less than the target impedance Z target,f , ψ1=0; ψ2 represents the number of decoupling capacitors placed in the interposer; ψ3 is the sum of all actual impedances Z f in the impedance matrix;

[0096] respectively represent the weight coefficients of ψ1, ψ2, ψ3;

[0097]

[0098] ψ2=N C (5)

[0099]

[0100] Formulas (7)-(13) are constraints in the analysis process to keep the core particle placement from exceeding the interposer boundary, prevent the core particle placement from overlapping, ensure the coordinate value is positive, etc.

[0101]

[0102]

[0103]

[0104]

[0105]

[0106] C unit ≥0 (12)

[0107] N C ∈N + (13)

[0108] Wherein, X i ,Y i represent the coordinates at the midpoint of the i-th core particle, X j ,Y j represent the coordinates at the midpoint of the j-th core particle, and αi ,β i represents the length of the i-th core particle in the horizontal coordinate axis direction (x direction) and the vertical coordinate axis direction (y direction), a j ,β j represents the length of the j-th core particle in the horizontal coordinate axis direction and the vertical coordinate axis direction, the length of the core particle in the horizontal coordinate axis direction and the vertical coordinate axis direction is the length and width of the core particle, A, B represents the length of the interposer in the horizontal coordinate axis direction and the vertical coordinate axis direction, that is, the length and width of the interposer; C unit represents the capacitance value of the decoupling capacitor placed in the interposer; N + represents a positive integer. The coordinates include horizontal coordinates and vertical coordinates, and the coordinates are positions.

[0109] Step 203, constructing a first constraint, a second constraint and a third constraint according to the positions of the core particles of the 2.5-dimensional integrated circuit and the positions of the ports on the core particles.

[0110] First, for a 2.5-dimensional chip system, a plurality of core particles are placed on an interposer, and the core particles communicate through a redistribution layer (RDL) in the interposer. The main goal in the core particle placement process is to minimize the total bus length between the core particles to reduce manufacturing costs, and the placement position of the core particles directly affects the total bus length of the wiring between the core particles. Therefore, in the impedance optimization process, the total length of the wire is a very necessary constraint condition.

[0111] The wiring plane in the silicon interposer can be regarded as a rectangular wiring plane based on a grid (set as Manhattan wiring method). The line length between any two core particles and the total length of the wiring can be represented as (14) and (15). The wiring between the ports of any two core particles is an interconnection line, and the sum of the lengths of all interconnection lines is the total length of the wiring. λ1 can also be understood as a penalty based on the constraint of minimizing the total length of the wiring.

[0112]

[0113] wherein the first constraint λ1 represents a constraint based on the constraint of minimizing the total length of the wiring, λ1 is the total length of the wiring. represents the length of the interconnection line between the p-th port on the i-th core particle and the q-th port on the j-th core particle, the length of the interconnection line is the Manhattan wiring distance, Q represents a set of all ports on all core particles of the 2.5-dimensional integrated circuit;

[0114]

[0115] x i,p ,y i,p represents the coordinates of the p-th port on the i-th core particle, which is connected to another core particle through RDL, x j,q ,y j,qrepresents the coordinate of the qth port on the jth die.

[0116] Secondly, besides the total length of the interconnects mentioned above, the length of a single interconnect also affects the signal transmission in 2.5D integrated circuit system. A single interconnect should not be too long to meet the propagation time constraint and the rise time constraint. Therefore, the length of a single interconnect is also an important constraint when placing the dies. The maximum length of the interconnects is preset, which is the length of a single interconnect, and can be preset according to actual needs. The second constraint indicates the length constraint of a single interconnect based on the preset maximum length of the interconnects, which is referred to as the single-line length constraint. λ2 can also be understood as the single-line length penalty based on The second constraint λ2 is represented as formula (16):

[0117]

[0118] In 2.5D circuit system, as more and more dies are integrated on a single interposer, the compact multi-die placement will cause heat dissipation problems. In order to meet the critical thermal requirements, the minimum distance between adjacent dies is set to k. (17), (18), (19) represent the distance constraint equations generated by the heat dissipation problem. λ3 represents the distance constraint based on the minimum distance constraint between two adjacent dies. λ3 can also be understood as the distance penalty based on the minimum adjacent distance constraint.

[0119] The third constraint λ3 is represented as formula (17):

[0120]

[0121] wherein,

[0122]

[0123]

[0124] k represents the minimum distance constraint between two adjacent dies, represents the penalty of the minimum distance constraint k in the horizontal coordinate axis direction, represents the penalty of the minimum distance constraint k in the vertical coordinate axis direction; and

[0125] If then χ1, χ2 = 0;

[0126] If then χ1, χ2 = 0;

[0127] If then χ1 = 1, χ2 = 0;

[0128] If then χ1= 0, χ2= 1.

[0129] For better understanding, three constraints are shown in Figure 4a , Figure 4b , Figure 4c Figure 1, 2, 3 represent different core particles, which are connected by interconnect lines, and the dotted line part represents the three constraints.

[0130] Step 204, constructing a hybrid objective function according to the impedance objective function, the first constraint, the second constraint and the third constraint; the hybrid objective function is represented as formula (20):

[0131]

[0132] Wherein, Λ represents a penalty function, and θ represents the weight of the penalty function;

[0133]

[0134] The subscripts λ1, λ2, λ3 represent the weight coefficients of λ1, λ2, λ3.

[0135] Ψ is a nonlinear function about the core particle position, capacitor layout, actual impedance and target impedance. In order to constrain the other negative effects caused by the layout process to the 2.5-dimensional system in the impedance optimization process, the constraints λ1, λ2, λ3 are considered, and the penalty function Λ is adopted in (21), therefore, combined with Ψ and Λ, the in formula (20) represents a new hybrid objective function, which contains the impedance objective function and the penalty function. The optimization process of is meaningful for finding the best layout of the 2.5-D system, while balancing between the layout, the actual impedance, the target impedance and the constraints.

[0136] Step 205, determining the minimum value of the hybrid objective function and the target position of the core particle, the target number of capacitors in the interposer and the position of the target capacitor according to the PDN parameters of the equivalent circuit model of the hybrid objective function.

[0137] There are many excellent meta-heuristic algorithms in the prior art, and each single meta-heuristic algorithm has its own advantages and disadvantages. In the particle swarm optimization (PSO) algorithm, each particle is constantly searching and is affected by other particles. In the iteration process, each particle is updated by two extreme values, one is the optimal solution found by the particle itself, called local extreme value, and the other is the optimal solution found by the whole population, called global extreme value. For the traditional PSO algorithm, if some particles fall into local extreme values too early, the whole particle swarm will quickly converge, and this phenomenon is called premature phenomenon. In the differential evolution (DE) algorithm, highly differentiated individuals can be obtained through mutation, crossover and selection operations. The differential evolution particle swarm optimization (DEPSO) algorithm combines the DE algorithm and the PSO algorithm to obtain an algorithm with a more diverse population. Note that, whether it is the PSO, DE or DEPSO algorithm, after the population is updated, some particles may exceed the boundary condition. For these boundary particles, the usual operation is to randomly update them again or directly assign a boundary value to them, which wastes the original algorithm's update mechanism.

[0138] The simulated annealing (SA) algorithm accepts degenerate solutions with a certain probability, which improves the reliability of obtaining the global optimal solution. The Metropolis sampling criterion is the core of SA, which accepts new solutions with a probability, rather than following a completely deterministic rule. Therefore, on the basis of DEPSO, the Metropolis method is used to process the boundary particles, which can further optimize the algorithm.

[0139] Therefore, a Metropolis-based differential particle swarm optimization (MDP) algorithm can be composed by combining the PSO, DE and the Metropolis criterion in SA. The minimum value of the mixed objective function can be found by the MDP algorithm, which can be expressed as The MDP algorithm outputs the target position of the core particle, the number of target capacitors in the interposer and the position of the target capacitor to realize the impedance optimization of the 2.5-dimensional integrated circuit based on the chip. When the MDP method is iterated, multiple values of the mixed objective function can be obtained, and the value of the mixed objective function is better.

[0140] As shown in Figure 5 , the specific steps of step 205 include:

[0141] Step 2051, input the hybrid objective function and the PDN parameters of the equivalent circuit model;

[0142] Step 2052, initialize the MDP;

[0143] Step 2053, initialize the population and the annealing temperature;

[0144] Step 2054, update the speed and position of the particle in the PSO algorithm according to the hybrid objective function and the PDN parameters of the equivalent circuit model; the particle includes the position of the core particle, the number of capacitors in the interposer and the position of the capacitor; the PDN parameters of the equivalent circuit model include the line width, the pitch, the minimum unit, the number of the core particle PDN, the line width, the pitch, the minimum unit, the number of the PDN on the interposer, the diameter, the pitch, the height, the number of the TSV, the diameter, the pitch, the height, the number of the solder ball and other parameters.

[0145] Step 2055, update the particle outside the boundary by the Metropolis criterion;

[0146] Step 2056, after the particle outside the boundary is updated, update the optimal position of the particle and the optimal value of the hybrid objective function in the PSO algorithm;

[0147] Step 2057, after the optimal position of the particle and the optimal value are updated, perform mutation operation on the chromosome in the DE algorithm; the chromosome in the DE algorithm is also the particle in the PSO algorithm.

[0148] Step 2058, perform crossover operation on the chromosome in the DE algorithm after the mutation operation;

[0149] Step 2059, update the chromosome outside the boundary by the Metropolis criterion after the crossover operation;

[0150] Step 2060, after the chromosome outside the boundary is updated, update the optimal position of the particle and the optimal value of the hybrid objective function in the PSO algorithm;

[0151] Step 2061, judge whether the termination condition is met;

[0152] In this step, it is judged whether the maximum number of iterations is reached.

[0153] Step 2062, if yes, output the objective function value of the hybrid objective function and the target position of the core particle, the target number of capacitors in the interposer and the position of the target capacitor;

[0154] If no, return to step 2054 and continue to perform steps 2054-2060 until the termination condition is met.

[0155] Wherein, the target function value is the minimum value of the hybrid target function. At this time, the target position of the core particle, the target number of capacitors in the interposer and the position of the target capacitor corresponding to the output target function value are also the optimal layout scheme of the 2.5-dimensional integrated circuit.

[0156] In the present application, a 2.5-dimensional integrated circuit example based on a core particle is used to test the optimization method of the embodiment of the present application. The parameters of the test structure are shown in Table 1, and the structure diagram is shown in Figure 6a and Figure 6b .

[0157] First, we test the comparison of MDP algorithm with PSO, DE, DEPSO algorithm, set the parameters θ = 1.5, k = 3 μm, the number of interconnections between each chip is set to 5, and the port is the center of each chip. The hybrid target function is input into each algorithm, Figure 7 The results of various algorithms are compared. It can be seen that the MDP method can obtain smaller function value and further obtain better impedance optimization layout of the 2.5-dimensional integrated circuit in the impedance optimization problem.

[0158] Then, set the parameters θ = 1.5, use MDP algorithm to optimize the target impedance function, and the optimal layout obtained is shown in Figure 8 , including the layout of the core particle and the decoupling capacitor and the wiring of the interconnection.

[0159] Table 1

[0160]

[0161] In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms “center”, “longitudinal”, “transverse”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise” and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0162] In addition, the terms “first” and “second” are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “multiple” is two or more, unless otherwise specifically limited.

[0163] In the present application, unless specifically defined otherwise, the terms "mounting", "connected", "connecting", "fixed", "fixedly connected", "connection", "fixedly connected", "connected", "fixed", and the like should be construed broadly, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0164] In the present application, unless specifically defined otherwise, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is higher in horizontal height than the second feature. The first feature "under", "below" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the first feature is lower in horizontal height than the second feature.

[0165] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present application.

[0166] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or replacements can also be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A method for multi-constrained impedance optimization of a 2.5-dimensional integrated circuit based on a kernel, characterized in that, The method comprises the following steps: Constructing an equivalent circuit model of a 2.5-dimensional integrated circuit containing multiple parasitic parameters, obtaining an impedance matrix of the equivalent circuit model; the impedance matrix is a set of working frequencies Corresponding actual impedance Set According to the target impedance And the impedance matrix constructs the impedance target function; the target impedance The maximum self-impedance allowed on the load side of the core particle corresponding to the working frequency; constructing a first constraint, a second constraint and a third constraint according to positions of the core particles of the 2.5-dimensional integrated circuit and positions of ports on the core particles; wherein the first constraint indicates a constraint based on minimization of a sum of lengths of a plurality of interconnection lines between ports between the core particles; the second constraint indicates a single interconnection line length constraint based on a preset maximum length constraint of the interconnection lines; and the third constraint indicates a distance constraint based on a minimum distance constraint between two adjacent core particles; constructing a hybrid objective function according to the impedance objective function, the first constraint, the second constraint and the third constraint; determining a minimum value of the hybrid objective function and target positions of the core particles, a target number of capacitors in the interposers and positions of the target capacitors according to the hybrid objective function and PDN parameters of the equivalent circuit model.

2. The method of claim 1, wherein, The impedance objective function is represented by formula (3): wherein denotes the set of working frequencies corresponding actual impedances in the impedance matrix and the sum of the differences between the actual impedances and the target impedance when the actual impedances are always smaller than the target impedance , denotes the number of decoupling capacitors placed in the interposer; is the sum of all actual impedances , , , respectively denote the weight coefficients of , , . The impedance objective function satisfies the constraints of formulae (7)-(13): wherein , represents the coordinate at the midpoint of the th core particle, represents the coordinate at the midpoint of the th core particle, represents the length of the th core particle in the horizontal coordinate axis direction and the vertical coordinate axis direction, represents the length of the th core particle in the horizontal coordinate axis direction and the vertical coordinate axis direction, represents the length of the inserter in the horizontal coordinate axis direction and the vertical coordinate axis direction; represents the capacitance value of the decoupling capacitor placed in the inserter; represents a positive integer.

3. The method of claim 2, wherein the method is a multi-constrained impedance optimization method for a 2.5D integrated circuit based on a core particle, and the method comprises the steps of: The first constraint is represented by formula (14): ​ wherein, denotes a first constraint, denotes a second constraint, denotes a third constraint, denotes a fourth constraint, denotes a fifth constraint, denotes a length of an interconnect line between a first port on a first corelet and a second port on a second corelet, denotes a set of all ports on all corelets of a 2.5-dimensional integrated circuit; , denotes the coordinates of the first port on the first core particle, denotes the coordinates of the first port on the first core particle, , denotes the coordinates of the first port on the first core particle. denotes the coordinates of the first port on the first core particle.​​ 4. The method of claim 3, wherein the method is a multi-constrained impedance optimization method for a 2.5-dimensional integrated circuit based on a kernel. The second constraint is represented by formula (16): wherein, represents a second constraint, represents a preset maximum length of the interconnection line.

5. The method for multi-constrained impedance optimization of a 2.5D integrated circuit based on a kernel according to claim 4, wherein, The third constraint is represented by formula (17): wherein represents a third constraint; denotes a minimum distance constraint between two adjacent core particles, denotes a penalty for a minimum distance constraint in the horizontal coordinate axis direction denotes a penalty for a minimum distance constraint in the vertical coordinate axis direction denotes a penalty for a minimum distance constraint in the vertical coordinate axis direction​ If <0, then =0; If X <0, then =0; If > > 0, then = 1, = 0; If > > 0, then = 0, = 1.

6. The method of claim 5, wherein the method is a multi-constrained impedance optimization method for a 2.5-dimensional integrated circuit based on a kernel. The hybrid objective function is represented by formula (20): wherein represents a penalty function, represents a weight of the penalty function; , , respectively represent weight coefficients of , , .

7. The method for multi-constrained impedance optimization of a 2.5D integrated circuit based on a kernel according to claim 5, wherein, The determination of the minimum value of the hybrid objective function and the target positions of the core particles, the target number of capacitors in the interposers and the positions of the target capacitors according to the hybrid objective function and the PDN parameters of the equivalent circuit model comprises: updating speeds and positions of particles in the PSO algorithm according to the hybrid objective function and the PDN parameters of the equivalent circuit model; the particles comprise the positions of the core particles, the number of capacitors in the interposers and the positions of the capacitors; updating particles outside the boundary by the Metropolis criterion; updating optimal positions of the particles and an optimal value of the hybrid objective function in the PSO algorithm; performing a mutation operation on a chromosome in the DE algorithm; performing a crossover operation on the chromosome in the DE algorithm; updating chromosomes outside the boundary by the Metropolis criterion; updating the optimal positions of the particles and the optimal value of the hybrid objective function in the PSO algorithm until a termination condition is reached, and outputting a target function value of the hybrid objective function and the target positions of the core particles, the target number of capacitors in the interposers and the positions of the target capacitors; wherein the target function value is the minimum value of the hybrid objective function.

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