A chip defect detection method and system based on TensorRT accelerated reasoning

Abstract

The present invention belongs to the technical field of chip defect detection, and specifically relates to a chip defect detection method and system based on TensorRT accelerated reasoning; the method comprises: obtaining a chip image dataset and preprocessing the dataset; using the chip image dataset to train an improved YOLOv5 model to obtain multiple target detection models; converting all target detection models into TensorRT models and splicing the TensorRT models; using the spliced ​​TensorRT model to process the image of the chip to be detected to obtain an inference result; performing dimensionality reduction and de-redundancy processing on the inference result to obtain a defect detection result of the chip to be detected; the present invention fundamentally solves the shortcomings of existing equipment in quality inspection speed and accuracy, has higher detection efficiency and faster speed, saves labor costs, and is highly practical.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip defect detection, and specifically relates to a chip defect detection method and system based on TensorRT accelerated reasoning. Background Art

[0002] In recent years, with my country's economic growth and the advent of the era of artificial intelligence, all industries have joined the ranks of digital transformation. Electronic devices have gradually become an indispensable part of people's work and life. Because chips are the core of the normal operation of various electronic devices, the demand for chips is also constantly rising. Once chip quality problems occur, it will cause huge losses. Therefore, suppliers cannot ignore the control of chip quality inspection. Object detection technology has been a research hotspot in the field of computer vision in recent years. With the rapid development of deep learning technology, object detection has made great progress. This technology uses convolutional neural networks to train network parameters using pre-labeled data sets, automatically extract potential features from targets, and ultimately complete target classification and location.

[0003] Due to the recent industrial transformation towards intelligent manufacturing, object detection technology has become widely used in production line quality inspection. Initially, manual inspections were time-consuming and labor-intensive, but now automated inspection (AOI) equipment is replacing manual labor, improving mechanization. However, AOI equipment's inspection algorithms are overly simplistic, resulting in low efficiency and accuracy. Furthermore, different batches have different acceptance criteria, resulting in poor generalization and failing to maximize the efficiency of manual review. Therefore, the combination of deep learning and object detection technology, applied to chip quality inspection, has significantly improved production line quality inspection efficiency and product quality.

[0004] Currently, deep learning-based object detection algorithms are mainly divided into single-stage detection algorithms and two-stage detection algorithms. Among them, single-stage detection algorithms mainly include YOLO and SSD. They are called single-stage detection algorithms because they generate prediction boxes and perform classification and regression operations at the same time during training. Two-stage detection methods mainly include the RCNN series, which first generates a series of regions of interest through the RPN network and then feeds these regions of interest into a convolutional neural network for classification and regression operations.

[0005] As deep learning-based object detection technology develops, quantization technology is also maturing. Quantization involves converting trained models into low-precision representations and computations. Commonly used software tools include NVIDIA's TensorRT, a deep learning inference engine that provides a comprehensive suite of tools, from model acquisition to optimization and compilation to deployment. TensorRT supports popular frameworks such as PyTorch, TensorFlow, and Caffe.

[0006] As the demand for chips increases day by day, quality requirements cannot be ignored, so industrial production line quality inspection has higher requirements for detection speed and accuracy. Therefore, inventing a chip defect detection method that can ensure detection speed while taking into account detection accuracy is a problem to be solved. Summary of the Invention

[0007] To address the shortcomings of the existing technology, the present invention proposes a chip defect detection method and system based on TensorRT accelerated reasoning, which includes:

[0008] S1: Obtain a chip image dataset and preprocess it to obtain a processed chip image dataset;

[0009] S2: Use the chip image dataset to train the improved YOLOv5 model to obtain multiple target detection models;

[0010] S3: Convert all object detection models into TensorRT models and splice the TensorRT models;

[0011] S4: Obtain the image of the chip to be tested, use the spliced ​​TensorRT model to process the image of the chip to be tested, and obtain the inference result;

[0012] S5: Perform dimensionality reduction processing on the inference results; use the improved NMS algorithm to perform redundancy processing on the inference results after dimensionality reduction processing to obtain the defect detection results of the chip to be detected.

[0013] Preferably, the process of training the improved YOLOv5 model includes: the improved YOLOv5 model includes a backbone network, a neck network and a head network;

[0014] The backbone network uses deformable convolution to extract features, and the backbone network is used to process chip images to obtain feature maps of different sizes;

[0015] The neck network fuses feature maps of different sizes to obtain a fused feature map;

[0016] The head network processes the fused feature map to obtain the prediction result;

[0017] The total loss function is used to adjust the parameters of the improved YOLOv5 model to obtain a trained improved YOLOv5 model.

[0018] Furthermore, the formula for extracting features using deformable convolution is:

[0019]

[0020] Among them, y(p0) represents the position of point p0 on the output feature map, w(p n ) represents the weight of the position point Pn, R represents the regular grid, Δp n represents the offset, ω n Indicates the offset Δp n The weight of , x() represents the position of the point on the input feature map.

[0021] Furthermore, the total loss function is:

[0022] Loss = w1·loss cls +w2·loss reg +w3·loss obj

[0023] Among them, loss cls Represents classification loss, loss reg Represents positioning loss, loss obj Represents confidence loss, w1, w2, and w3 correspond to the weights of the three losses respectively.

[0024] Furthermore, the classification loss is:

[0025]

[0026]

[0027] Among them, n represents the total number of samples, x represents the sample, and y gt Indicates the label, y p Represents the predicted output, x represents the sample; ω1 represents the first adjustment weight, ω2 represents the second adjustment weight, and sample() represents the summation.

[0028] Preferably, the formula for dimensionality reduction processing of the inference result is:

[0029] length=box num *box pram_num *memory_size+1

[0030] Among them, length represents the length of the array storing the inference results after dimensionality reduction, box num Indicates the number of prediction boxes, box pram_num Indicates the number of parameters in the prediction box, and memory_size indicates the size of the data type in memory.

[0031] Preferably, the inference result includes multiple prediction box information, and the prediction box information includes the coordinates, length, width and confidence of the prediction box.

[0032] Preferably, the process of using the improved NMS algorithm to remove redundancy from the inference results after dimensionality reduction includes:

[0033] Set the overlap rate threshold, calculate the overlap rate between the prediction box with the maximum confidence and other prediction boxes, and remove the prediction boxes whose overlap rate with other boxes is greater than the overlap rate threshold;

[0034] Set the size ranges of small, medium, and large targets; divide the defects in the chip image dataset into small, medium, and large targets based on their longest side lengths; and take the minimum side size of all defects falling under the three types of targets as the small target threshold size, medium target threshold size, and large target threshold size, respectively.

[0035] Select the prediction box with the highest confidence among the remaining prediction boxes, compare the minimum side of the prediction box with the threshold size closest to the minimum side, and if the minimum side is smaller than the threshold size, expand the minimum side of the prediction box to the threshold size;

[0036] Calculate the overlap ratio between the expanded prediction box and the remaining prediction box. If the overlap ratio is greater than the overlap ratio threshold, remove the prediction box with an overlap ratio greater than the overlap ratio threshold in the remaining prediction box.

[0037] A chip defect detection system based on TensorRT accelerated inference, including: an image processing module, a target detection module, an inference result reprocessing module, and a detection result display module;

[0038] The image processing module is used to preprocess the image of the chip to be detected;

[0039] The target detection module is used to perform defect detection on the preprocessed chip image to be detected to obtain an inference result;

[0040] The inference result reprocessing module is used to reprocess the inference result, remove redundant prediction boxes, and obtain defect detection results;

[0041] The detection result display module analyzes the defect detection result according to the chip qualification standard and outputs the analysis result.

[0042] The beneficial effects of the present invention are as follows: the present invention transforms ordinary convolution into deformable convolution to enhance the network's ability to extract features, converts the target detection model in the .pt format under the pytorch framework into a TensorRT model in the .engine format, thereby accelerating the detection speed; utilizes multiple .engine models for inference detection to improve detection accuracy; the present invention combines deep learning, target detection technology and an accelerated inference framework to accurately detect chip defects in real time, fundamentally solving the shortcomings of existing equipment in quality inspection speed and accuracy, with higher detection efficiency and faster speed, saving labor costs and high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a flow chart of the chip defect detection method based on TensorRT accelerated reasoning in the present invention. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0045] The present invention proposes a chip defect detection method and system based on TensorRT accelerated reasoning, such as Figure 1 As shown, the method includes the following contents:

[0046] S1: Obtain a chip image dataset and preprocess it to obtain a processed chip image dataset.

[0047] Chip images can be obtained from the production line, and defect targets in the images can be annotated using annotation tools. A data set can be created in VOC format. The data set is then divided into a training set and a test set according to the ratio. The training set image data is preprocessed and the image is scaled to a size suitable for the network structure to obtain a chip image data set. The chip images in the data set have the same length and width.

[0048] S2: Use the chip image dataset to train the improved YOLOv5 model to obtain multiple target detection models.

[0049] The traditional YOLOv5 model is an improvement based on the YOLOv3 model publicly released by Ultralytics on June 9, 2020; the present invention improves the traditional YOLOv5 model. The improved YOLOv5 model includes a backbone network (backbone network, used for feature extraction), a neck network (neck, used to connect the backbone and the head) and a head network (head, for final output prediction); first, the chip image dataset obtained after preprocessing is input into the backbone to extract features. The backbone extracts feature maps of different scales by performing convolution pooling operations on the processed image. The feature maps of different scales are then input into the neck part for feature fusion. Finally, the fused features are input into the head part for classification and bounding box regression to obtain the prediction box. Deformed convolution is used in the backbone network to extract features; specifically, the present invention changes the 3*3 ordinary convolutions of the last three layers of the backbone network part to deformed convolution to extract features. Deformed convolution is based on using additional offsets to increase the spatial sampling position in the module and learning the offsets from the target task without the need for additional supervision. Adding a 2D offset to the regular grid sampling locations in the standard convolution enables the sampling network to form free-form deformations. The offset is learned from the previous feature map through additional convolutional layers. Therefore, the deformation affects the input features in a local, dense and adaptive manner.

[0050] The input feature map X, i.e., the chip image data, is sampled using a regular grid R, which defines the size and expansion of the receptive field:

[0051] R={(-1,-1),(-1,0),......,(0,1),(1,1)}

[0052] For the position on the output map y of the deformed convolution, we have:

[0053]

[0054] Among them, y(p0) represents the position of point p0 in the output feature map, x() represents the initial position of a point on the input feature map; Pn represents the nth position in R, and Pn enumerates the positions in R; w(p n ) represents the weight of the nth position in Pn, x(p0+p n ) represents the position of p0 on the input feature map with respect to each point in the receptive field R. In the deformable convolution, the regular grid R increases the offset {Δp n|n=1,2,...,N}, where N=|R|. The offset is calculated in an extra convolutional layer. A normal convolution kernel is used on the original image to obtain 2N offsets, that is, N in the x-direction and N in the y-direction. A convolutional layer dedicated to calculating the offset is added to the convolutional network before the deformable convolution. The two convolutional layers are calculated for the two directions respectively, and Δp is obtained. n =p(Δx n ,Δy n ), the above formula becomes:

[0055]

[0056] Sampling is done at irregular and offset positions Pn+ΔPn. Since the offset is often a decimal, bilinear interpolation is used to decompose the offset into integers in the x and y directions:

[0057]

[0058] Among them, P represents an arbitrary position, q enumerates all the integral spatial positions of the feature map X, G() is the bilinear interpolation kernel, and G is a two-dimensional kernel that is divided into two one-dimensional kernels.

[0059] G(p,q)=g(q x ,p x )·g(q y ,p y )

[0060] g(a,b)=max(0,1-|ab|)

[0061] Since G(q,p) is non-zero only for a few q, the computation of x(p) is very fast.

[0062] The offset is obtained by applying a convolutional layer on the same input feature map, with the convolution kernel having the same spatial resolution and expansion as the current convolution layer. The output offset field has the same spatial resolution as the input feature map. During the training process, the convolution kernel and offset that generate the output features are learned simultaneously. A weight parameter is introduced for each offset. When extracting features, the probability value of the extracted roi (region of interest) is compared with the ground truth box, and the probability value of the roi representing the ground truth box is used as Δp n The weight coefficient ω n , so the expression for calculating the feature map after convolution becomes:

[0063]

[0064] After the chip image is processed by the backbone network, feature maps of different sizes are obtained; the neck network fuses the feature maps of different sizes to obtain a fused feature map that contains both rich position information and rich semantic information.

[0065] The head network processes the fused feature map to obtain a prediction result; the prediction result is multiple prediction box information, including the coordinates, length, width and confidence of the prediction box. In this section, the total loss function is used to adjust the parameters of the improved YOLOv5 model; the total loss function is divided into three parts, namely: the classification loss for calculating whether the anchor box and the corresponding real box are correctly classified, the positioning loss for calculating the error between the prediction box and the real box, and the confidence loss for calculating the confidence of the network; the classification loss and confidence loss are calculated using the cross entropy loss function, and the positioning loss is calculated using the IOU (Intersection over Union) loss function; the loss value is obtained through the loss function, and then the model parameters are updated through back propagation to obtain a trained improved YOLOv5 model, namely the target detection model, and multiple different target detection models can be obtained using different training data. The present invention improves the classification loss and confidence loss, and the improved classification loss is:

[0066]

[0067]

[0068]

[0069] Among them, loss cls Represents classification loss, loss obj Represents confidence loss, n represents the total number of samples, x represents a sample, and one sample is one input; y gt Indicates the label, y p Represents the predicted output, q o Represents the confidence score of the predicted output, p iou Represents the iou (overlap rate) value of the predicted box and the corresponding target box; ω1 is the first adjustment weight, ω2 is the second adjustment weight, ω1, ω2 are used to adjust the weights of positive and negative samples, positive samples represent predicted boxes identified as defects, and negative samples represent predicted boxes identified as non-defects; used to reconcile the balance between positive and negative samples, where sample() represents summation, sample(y p ) represents all predicted outputs y p Summation.

[0070] The localization loss is:

[0071] loss reg =1-IOU

[0072] Among them, IOU represents the intersection-over-union ratio of two prediction boxes, that is, the ratio of the intersection area of ​​the two prediction boxes to the union area of ​​the two prediction boxes.

[0073] The total loss function is:

[0074]

[0075] The original cross entropy loss function treats positive and negative samples equally. When there is an imbalance between positive and negative samples, for example, when the negative sample is smaller than the positive sample, the total loss of the positive sample will be much greater than the total loss of the negative sample. In this way, the learning of the model will gradually favor the positive sample without considering the influence of the negative sample. The present invention improves the loss function and adds weight parameters to adjust and reconcile the imbalance between positive and negative samples. ω1 changes with the trend of (1-a), and ω2 changes with the trend of a (a represents the confidence score of the predicted label or predicted output). For example, when the output is a positive sample and the value of a is large, it means that it is an easy-to-classify positive sample. At this time, due to the trend of ω1 with (1-a), the loss of the easy-to-classify positive sample will be reduced, thereby suppressing the number of positive samples; thereby making the prediction results of the model more accurate.

[0076] S3: Convert all object detection models into TensorRT models and concatenate the TensorRT models.

[0077] Converting a .pt object detection model to a .engine TensorRT model completes the inter-layer fusion and precision calibration required for optimization during the conversion process. During the inter-layer fusion phase, the tensors of each layer in the PyTorch framework are used as input, and layers are merged horizontally or vertically. Horizontal merging combines convolution, bias, and activation functions into a CBR structure, occupying only one CUDA core. Vertical merging combines layers with the same structure but different weights into a wider layer, also occupying only one CUDA core. Inter-layer fusion will reduce the number of layers, because during model inference, the calculation operations of each layer are actually completed by the GPU by calling different CUDA cores. Although CUDA calculates tensors very quickly, time will be wasted on starting the CUDA core and reading and writing operations on each layer of tensors, which will cause insufficient space. Therefore, inter-layer fusion is needed to improve the calculation speed; the precision calibration process is automatically completed by tensor rt. In this process, the tensors used by many frameworks are 32-bit precision floating point numbers. After the network training is completed, there is no backpropagation process in the inference process. Therefore, the present invention sets the precision to 16 bits, reduces the tensor precision, occupies less memory, and lightweights the model.

[0078] After the multiple target detection models trained in step S2 are converted into TensorRT models, the multiple TensorRT models are spliced ​​together. Specifically,

[0079] 1. Read different .engine files in sequence and deserialize them;

[0080] 2. Create a two-dimensional engine object, and then store the deserialized files into the two-dimensional engine object. When loading a single model, the data structure used is a one-dimensional pointer. Change it to a two-dimensional dynamic array to achieve model splicing.

[0081] 3. Create a context and create an interface for the model input;

[0082] 4. Create a buffer and allocate cache space on the GPU for the input and output of the data to be detected;

[0083] S4: Obtain the image of the chip to be detected, use the spliced ​​TensorRT model to process the image of the chip to be detected, and obtain the inference result.

[0084] The chip to be tested is input into the spliced ​​TensorRT model for processing and outputs the inference result; the inference result includes multiple prediction box information, and the prediction box information includes the coordinates, length, width and confidence of the prediction box.

[0085] Use a two-dimensional array to store the inference results. Expand the inference results, calculate the number of inference results corresponding to each TensorRT model, and then concatenate the inference results of the next model.

[0086] S5: Perform dimensionality reduction processing on the inference results; use the improved NMS algorithm to perform redundancy processing on the inference results after dimensionality reduction processing to obtain the defect detection results of the chip to be detected.

[0087] Reprocess the inference results and remove redundant frames. First, perform dimensionality reduction on the inference results. Specifically, the formula for dimensionality reduction on the inference results is:

[0088] length=box num *box pram_num *memory_size+1

[0089] Among them, length represents the length of the array storing the inference results after dimensionality reduction, box num Indicates the number of prediction boxes, box pram_num Indicates the number of parameters in the prediction box, and memory_size indicates the size of the data type in memory.

[0090] The one-dimensional array after dimensionality reduction is passed into the NMS (Non-Maximum Suppression) algorithm. At this time, the array length needs to be recalculated in the NMS algorithm. Because the original technology uses single-model inference, the length of the output after inference is specified. The array includes some memory that does not store the inference results, resulting in long inference time and space waste. However, since the present invention uses multiple models for inference, the storage structure changes, and operations such as model splicing and dimensional expansion are performed. When performing the NMS operation, calculations are only performed based on the existing detection results, avoiding space waste and saving time costs.

[0091] Specifically, the process of further processing the inference results after dimensionality reduction using the improved NMS algorithm includes:

[0092] Set the overlap rate threshold, calculate the overlap rate iou between the prediction box with the maximum confidence and other prediction boxes, that is, the ratio of the intersection to the union of the two prediction boxes, and then remove the prediction boxes in other boxes whose overlap rate is greater than the overlap rate threshold;

[0093] Set the size ranges of small, medium, and large targets; divide the defects in the chip image dataset into small, medium, and large targets based on their longest side lengths; and take the minimum side size of all defects falling under the three types of targets as the small target threshold size, medium target threshold size, and large target threshold size, respectively.

[0094] Select the prediction box with the highest confidence among the remaining prediction boxes, compare the minimum side of the prediction box with the threshold size closest to the minimum side, and if the minimum side is smaller than the threshold size, expand the minimum side of the prediction box to the threshold size;

[0095] Calculate the overlap ratio between the expanded prediction box and the remaining prediction box. If the overlap ratio is greater than the overlap ratio threshold, remove the prediction box with an overlap ratio greater than the overlap ratio threshold in the remaining prediction box.

[0096] After processing with the traditional NMS algorithm, the current IOU threshold setting cannot remove more redundant frames. To address this problem, the present invention uses an improved NMS algorithm to change the size of the predicted frame and recalculate the IOU. This removes frames that were retained by the traditional algorithm because their IOU values ​​were slightly below the set threshold, thereby removing more redundant frames. After processing with the improved NMS algorithm, the defect detection results of the chip to be tested are obtained; the defect detection results of the chip to be tested are analyzed according to the chip qualification standards to obtain an analysis result, including whether the chip has a defect, the size and location of the defect, and whether the chip is qualified.

[0097] The present invention also proposes a chip defect detection system based on TensorRT accelerated reasoning, which is used to execute the above-mentioned chip defect detection method based on TensorRT accelerated reasoning, including: an image processing module, a target detection module, an inference result reprocessing module and a detection result display module;

[0098] The image processing module is used to preprocess the image of the chip to be detected;

[0099] The target detection module is used to perform defect detection on the preprocessed chip image to be detected to obtain an inference result;

[0100] The inference result reprocessing module is used to reprocess the inference result, remove redundant prediction boxes, and obtain defect detection results;

[0101] The detection result display module analyzes the defect detection result according to the chip qualification standard and outputs the analysis result.

[0102] The process of this system executing the chip defect detection method based on TensorRT accelerated reasoning is similar to the above-mentioned chip defect detection method based on TensorRT accelerated reasoning implementation process, and will not be repeated here.

[0103] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation plans of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip defect detection method based on TensorRT accelerated reasoning, characterized in that: include: S1: Obtain a chip image dataset and preprocess it to obtain a processed chip image dataset; S2: Use the chip image dataset to train the improved YOLOv5 model to obtain multiple target detection models; The process of training the improved YOLOv5 model includes: the improved YOLOv5 model includes a backbone network, a neck network, and a head network; The backbone network uses deformable convolution to extract features, and the backbone network is used to process chip images to obtain feature maps of different sizes; The neck network fuses feature maps of different sizes to obtain a fused feature map; The head network processes the fused feature map to obtain the prediction result; The total loss function is used to adjust the parameters of the improved YOLOv5 model to obtain a trained improved YOLOv5 model; S3: Convert all object detection models into TensorRT models and splice the TensorRT models; S4: Obtain the image of the chip to be tested, use the spliced ​​TensorRT model to process the image of the chip to be tested, and obtain the inference result; S5: Perform dimensionality reduction processing on the inference result; use the improved NMS algorithm to perform redundancy removal processing on the inference result after dimensionality reduction processing to obtain the defect detection result of the chip to be detected; the process of using the improved NMS algorithm to perform redundancy removal processing on the inference result after dimensionality reduction processing includes: Set the overlap rate threshold, calculate the overlap rate between the prediction box with the maximum confidence and other prediction boxes, and remove the prediction boxes whose overlap rate with other boxes is greater than the overlap rate threshold; Set the size ranges of small, medium, and large targets; divide the defects in the chip image dataset into small, medium, and large targets based on their longest side lengths; and take the minimum side size of all defects falling under the three types of targets as the small target threshold size, medium target threshold size, and large target threshold size, respectively. Select the prediction box with the highest confidence among the remaining prediction boxes, compare the minimum side of the prediction box with the threshold size closest to the minimum side, and if the minimum side is smaller than the threshold size, expand the minimum side of the prediction box to the threshold size; Calculate the overlap ratio between the expanded prediction box and the remaining prediction box. If the overlap ratio is greater than the overlap ratio threshold, remove the prediction box with an overlap ratio greater than the overlap ratio threshold in the remaining prediction box.

2. The chip defect detection method based on TensorRT accelerated reasoning according to claim 1 is characterized in that: The formula for extracting features using deformable convolution is: Among them, y(p0) represents the position of point p0 on the output feature map, w(p n ) represents the weight of the position point Pn, R represents the regular grid, Δp n represents the offset, ω n Indicates the offset Δp n The weight of , x() represents the position of the point on the input feature map.

3. The chip defect detection method based on TensorRT accelerated reasoning according to claim 1 is characterized in that: The total loss function is: Loss=w1·loss cls +w2·loss reg +w o ·loss obj Among them, loss cls Represents classification loss, loss reg Represents positioning loss, loss obj Represents confidence loss, w1, w2, and w3 correspond to the weights of the three losses respectively.

4. The chip defect detection method based on TensorRT accelerated reasoning according to claim 3 is characterized in that: The classification loss is: Among them, n represents the total number of samples, x represents the sample, and y gt Indicates the label, y p Represents the predicted output, x represents the sample; ω1 represents the first adjustment weight, ω2 represents the second adjustment weight, and sample() represents the summation.

5. The chip defect detection method based on TensorRT accelerated reasoning according to claim 1 is characterized in that: The formula for dimensionality reduction of inference results is: length=box num *box pram_num *memory_size+1 Among them, length represents the length of the array storing the inference results after dimensionality reduction, box num Indicates the number of prediction boxes, box pram_num Indicates the number of parameters in the prediction box, and memory_size indicates the size of the data type in memory.

6. The chip defect detection method based on TensorRT accelerated reasoning according to claim 1 is characterized in that: The inference result includes multiple prediction box information, including the coordinates, length, width and confidence of the prediction box.

7. A chip defect detection system based on TensorRT accelerated reasoning, the system being used to execute the chip defect detection method based on TensorRT accelerated reasoning according to any one of claims 1 to 6, characterized in that: include: Image processing module, target detection module, reasoning result reprocessing module and detection result display module; The image processing module is used to preprocess the image of the chip to be detected; The target detection module is used to perform defect detection on the preprocessed chip image to be detected to obtain an inference result; The inference result reprocessing module is used to reprocess the inference result, remove redundant prediction boxes, and obtain defect detection results; The detection result display module analyzes the defect detection result according to the chip qualification standard and outputs the analysis result.

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