A semiconductor structure and a detection method for the semiconductor structure

Abstract

This invention discloses a semiconductor structure and a detection method for the semiconductor structure. The semiconductor structure includes: a first wafer having a plurality of first-type chip units thereon, the first wafer having a first bonding surface; each first-type chip unit having a first conductive line pattern at the first bonding surface; and a second wafer having a plurality of second-type chip units thereon, the second wafer having a second bonding surface; each second-type chip unit having a second conductive line pattern at the second bonding surface; the first wafer and the second wafer can be wafer-bonded through the first bonding surface and the second bonding surface, and after bonding, the first conductive line pattern and the second conductive line pattern are electrically connected to each other and form a closed loop.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to, but not limited to, a semiconductor structure and a detection method for the semiconductor structure. Background Technology

[0002] In recent years, an increasing number of engineers in the field of microelectronics packaging have begun to research emerging 2.5D or 3D packaging technologies to meet the requirements of miniaturization, high performance, and high reliability in electronic products. In 3DIC (three-dimensional integrated circuit) chips, memory wafers (DRAM die) and logic wafers (logic die) can be connected together and packaged using wafer-level interconnection methods such as hybrid bonding and TSV (through silicon via) technology to form a three-dimensional stacked chip.

[0003] Bonding technology is the core technology for realizing three-dimensional wafer stacking, and its success directly determines the mechanical strength and electrical interconnection characteristics of the entire integrated unit. Compared with wire bonding and flip-chip bonding, wafer-level Cu / SiO2 hybrid bonding eliminates the need for metal wires or microbumps, achieving direct bonding through the interfaces between Cu / Cu and SiO2 / SiO2. The bonding interconnects between SiO2 dielectrics provide mechanical support and electrical isolation for the entire integrated unit, while the vertical electrical interconnections of the chip are achieved through inter-metal bonding. Hybrid bonding technology can accelerate the achievement of bump pitches of 10 micrometers and below, providing higher interconnect density, smaller and simpler circuits, greater bandwidth, lower capacitance, and lower power consumption (less than 0.05 picojoules per bit). Therefore, it is considered an ideal bonding solution for CMOS image sensors (CIS), high-bandwidth memory (HBM), and chiplet technology.

[0004] In 3D stacking processes, the connectivity of metal interconnects after hybrid bonding is the core criterion for evaluating bonding results. However, current processes can only detect bubbles and interconnect alignment after wafer bonding, and cannot perform non-destructive testing at the current site to determine if the interconnects are properly connected. Judgment can only be made through destructive slicing or electrical testing at the end of the production chain.

[0005] How to directly detect the connection status of metal interconnects after wafer bonding is an urgent problem to be solved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a detection method for the semiconductor structure, so as to solve the technical problem in the prior art that the connection status of metal interconnects after wafer bonding cannot be directly detected.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a first wafer having a plurality of first-type chip units thereon, the first wafer having a first bonding surface; each first-type chip unit having a first conductive line pattern at the first bonding surface; and a second wafer having a plurality of second-type chip units thereon, the second wafer having a second bonding surface; each second-type chip unit having a second conductive line pattern at the second bonding surface; the first wafer and the second wafer can be wafer-bonded through the first bonding surface and the second bonding surface, and after bonding, the first conductive line pattern and the second conductive line pattern are electrically connected to each other and form a closed loop.

[0008] Furthermore, the technologies used for wafer-level bonding between the first wafer and the second wafer include: oxide bonding technology, fused bonding technology, metal diffusion bonding technology, fusible metal bonding, or hybrid bonding, etc.

[0009] Furthermore, when the first wafer and the second wafer are bonded together, each first type of chip unit and each second type of chip unit correspond to each other one-to-one, and each first conductive line pattern and each second conductive line pattern also correspond to each other one-to-one.

[0010] Furthermore, the first type of chip unit and the second type of chip unit can be selected as logic chips, memory chips, or sensor chips, etc.

[0011] Furthermore, the first conductive circuit pattern also includes a first conductive circuit portion and a first conductive connection portion, and the second conductive circuit pattern also includes a second conductive circuit portion and a second conductive connection portion. The first conductive circuit portion and the second conductive circuit portion constitute the main coil portion of the loop-shaped closed loop, while the first conductive connection portion and the second conductive connection portion constitute the bonding connection portion of the loop-shaped closed loop.

[0012] Furthermore, the first conductive line portion and the second conductive line portion, as well as the first conductive connection portion and the second conductive connection portion, are all made of metallic materials.

[0013] Furthermore, the loop-shaped closed circuit can be a single-layer multi-coil circuit.

[0014] Furthermore, the loop-shaped closed loop can be a multi-layer single coil, which is formed by connecting one end of the innermost layer of the coil to one end of the outermost layer of the coil through multi-layer metal wiring.

[0015] Furthermore, both the first conductive line portion and the second conductive line portion are located in the inner layer of the bonding surface, and the first conductive line portion and the second conductive line portion can be fabricated in the same layer as the circuit layer in the first type of chip unit and / or the second type of chip unit; the first conductive connection portion and the second conductive connection portion adopt through-hole technology to lead the first conductive line portion and the second conductive line portion to the surface layer of the bonding surface, respectively.

[0016] Both the first conductive line portion and the second conductive line portion are located on the surface layer of the bonding surface, and the first conductive connection portion and the second conductive connection portion are also located on the surface layer of the bonding surface. At this time, the first conductive line portion and the first conductive connection portion are integrally formed, and the second conductive line portion and the second conductive connection portion are integrally formed.

[0017] Furthermore, the top view shape of the loop can be rectangular, circular, elliptical, rhomboid, polygonal, etc.

[0018] The present invention also provides a method for detecting semiconductor structures. A first wafer and a second wafer are provided, which are wafer-bonded via the first bonding surface and the second bonding surface. After bonding, the first conductive circuit pattern and the second conductive circuit pattern are electrically connected to each other to form a closed loop. Further, a detection probe is provided, which is placed above the closed loop for detecting the wafer bonding result.

[0019] Furthermore, the detection probe is an eddy current detection probe, which generates an alternating magnetic field, causing an induced current to be generated in the loop closed circuit within the alternating magnetic field; furthermore, the eddy current detection probe also provides a detection element, which determines the connection status of the metal interconnects after wafer bonding by detecting changes in the induced current.

[0020] This invention achieves non-destructive testing of wafer bonding results by employing a special coil-like metal wiring structure within the wafer and utilizing eddy current detection. The connection status of the metal interconnects is directly inspected after wafer bonding, eliminating the need for slicing at the current site or completing back-end interconnects before performing electrical testing. This avoids the continuation of subsequent semiconductor processes due to bonding anomalies, thereby reducing production costs and improving production efficiency. Compared to traditional processes where it's impossible to determine whether metal interconnect connection anomalies are caused by bonding or back-end interconnects, this invention can eliminate bonding-related metal interconnect connection anomalies, further improving wafer production efficiency. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the first wafer on the first bonding surface side in a specific embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the structure of the second wafer on the second bonding surface side in a specific embodiment of the present invention;

[0023] Figure 3A -B is a structural schematic diagram of a set of corresponding first conductive line patterns 120 and second conductive line patterns 220. Figure 3C for Figure 3A -B is a single-layer multi-coil loop closed circuit formed by bonding the first conductive line pattern 120 and the second conductive line pattern 220.

[0024] Figure 4A -D is a top view of the loop-shaped closed loop in this invention;

[0025] Figure 5A -B is a three-dimensional structural diagram of a single-layer multi-coil loop closed loop portion structure in some embodiments of the present invention;

[0026] Figure 6A -B is a structural schematic diagram of a set of corresponding first conductive line patterns 120 and second conductive line patterns 220. Figure 6C for Figure 6A -B is a multilayer single coil loop formed by bonding the first conductive line pattern 120 and the second conductive line pattern 220 in B.

[0027] Figure 7A -B is a three-dimensional structural diagram of the loop closed loop portion of the multilayer single coil in some embodiments of the present invention;

[0028] Figure 8 This is a schematic diagram of a method for detecting semiconductor structures in a specific embodiment of the present invention. Detailed Implementation

[0029] To facilitate understanding of this disclosure, exemplary embodiments thereof will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0030] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of actual embodiments, nor well-known functions and structures, may be described herein.

[0031] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0032] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0034] As described in the background section, alignment accuracy is currently assessed during hybrid bonding by checking overlay precision. After bonding, the presence of bubbles or voids at the bonding interface and the bonding strength of the wafer are checked. However, due to technical limitations, non-destructive testing of the interconnect connectivity is not possible. Currently, the only way to assess interconnect connectivity at this site is through slicing inspection, or near the end of the production chain, after back-end bonding is completed, by performing electrical testing on the wafer to determine the interconnect connectivity.

[0035] Therefore, the current process has the following disadvantages:

[0036] 1. It is impossible to determine whether the abnormal connection of the metal wires is caused by bonding or by the back wiring.

[0037] 2. Abnormal connection conditions of metal wires caused by bonding can significantly increase production costs and reduce production efficiency.

[0038] 3. For slicing inspection, the inspection is destructive and cannot be applied to every wafer.

[0039] In existing 3D stacking processes, the detection process for the connectivity of metal interconnects after hybrid bonding still needs improvement. This will be analyzed and explained in conjunction with specific embodiments.

[0040] Appendix Figure 1 This is a schematic diagram of the structure of the first wafer on the first bonding surface side in a specific embodiment of the present invention.

[0041] Please refer to the attached document. Figure 1 The semiconductor structure includes: a first wafer 100, on which a plurality of first-type chip units 110 are disposed. The first-type chip units 110 are fabricated using the first wafer as a base layer, and then using techniques such as photolithography, etching, thin film growth, diffusion, ion implantation, chemical mechanical polishing, and metallization to create the desired semiconductor devices, thus completing the fabrication of the first-type chip units 110; simultaneously, the first wafer 100 has a first bonding surface, with... Figure 1 The diagram shown is a schematic representation of the structure of the first wafer 100 on the first bonding surface side. The first wafer 100 can be mixed-bonded with other wafers through the first bonding surface; (The diagram is accompanied by...) Figure 1 An enlarged view of a single first-type chip unit 110 in the first wafer 100 is also shown. Referring to the enlarged view, each first-type chip unit 110 has a first conductive line pattern 120 at the first bonding surface. The first conductive line pattern 120 is a special marking line pattern set by the present invention, which is used to directly detect the connection status of the metal interconnects after wafer bonding.

[0042] Appendix Figure 2 This is a schematic diagram of the structure of the second wafer on the second bonding surface side in a specific embodiment of the present invention.

[0043] Please refer to the attached document. Figure 2 The semiconductor structure further includes: a second wafer 200, on which a plurality of second-type chip units 210 are disposed. The second-type chip units 210 are fabricated using the second wafer as a base layer, and then using techniques such as photolithography, etching, thin film growth, diffusion, ion implantation, chemical mechanical polishing, and metallization to create the desired semiconductor devices, thus completing the fabrication of the second-type chip units 210; simultaneously, the second wafer has a second bonding surface; (Attached) Figure 2 The diagram shown is a schematic representation of the structure of the second wafer 200 on the second bonding surface side. The second wafer 200 can be mixed-bonded with other wafers through the second bonding surface. In this invention, the second wafer 200 can be mixed-bonded with the first wafer 100 through the second bonding surface; simultaneously, attached... Figure 2 An enlarged view of a single second-type chip unit 210 in the second wafer 200 is also shown. Referring to the enlarged view, each second-type chip unit 210 has a second conductive line pattern 220 at the second bonding surface. The second conductive line pattern 220 is a special marking line pattern set by the present invention, which is used to directly detect the connection status of the metal interconnects after wafer bonding.

[0044] Furthermore, the first wafer 100 and the second wafer 200 can be bonded together via the first bonding surface and the second bonding surface. After bonding, the first conductive line pattern 120 and the second conductive line pattern 220 are electrically connected to each other and form a complete closed loop. Furthermore, the closed loop can be used to directly detect the connection status of the metal interconnects after wafer bonding.

[0045] Furthermore, the technologies used for wafer-level bonding between the first wafer 100 and the second wafer 200 mainly include: oxide bonding technology, fused bonding technology, metal diffusion bonding technology, fusible metal bonding, hybrid bonding, etc. Furthermore, in this invention, hybrid bonding is preferred.

[0046] Furthermore, during wafer bonding of the first wafer 100 and the second wafer 200, each first type of chip unit 110 and each second type of chip unit 210 corresponds one-to-one with each other, and each first conductive line pattern 120 and each second conductive line pattern 220 also corresponds one-to-one with each other. The first type of chip unit 110 and the second type of chip unit 210 can be selected as logic chips such as GPUs, CPUs, MCUs, and AI chips; or memory chips such as DRAM, SDRAM, ROM, and NAND; or sensing chips such as MEMS, fingerprint sensors, microphones, and image sensors. Please refer to the appendix. Figure 3A -C, which shows a structural schematic diagram of a set of corresponding first conductive line patterns 120 and second conductive line patterns 220, through hybrid bonding, attached Figure 3A The first conductive line pattern 120 in the middle is mirror-flipped, and is attached to the middle. Figure 3B The second conductive line patterns 220 in the diagram are electrically connected to each other and form as shown in the attached diagram. Figure 3C The diagram shows a single-layer, multi-coil, loop-shaped closed loop. Further, the first conductive line pattern 120 includes a first conductive line portion 1201 and a first conductive connection portion 1202, and the second conductive line pattern 220 includes a second conductive line portion 2201 and a second conductive connection portion 2202. The first conductive line portion 1201 and the second conductive line portion 2201 constitute the main coil portion of the loop-shaped closed loop, while the first conductive connection portion 1202 and the second conductive connection portion 2202 constitute the bonding connection portion of the loop-shaped closed loop.

[0047] Appendix Figure 3C The top view of the single-layer multi-coil loop closed loop shown can be rectangular. For further details, please refer to the appendix. Figure 4A -D, the top view of the loop-shaped closed loop can also be circular, elliptical, rhomboid, polygonal, etc., but is not limited to the above-mentioned shapes. The top view of the loop-shaped closed loop that can be used to directly detect the connection status of metal interconnects after wafer bonding is within the protection scope of this invention.

[0048] Appendix Figure 5A -B is a three-dimensional structural diagram of a single-layer multi-coil annular closed loop portion structure in some embodiments of the present invention.

[0049] In some embodiments, the first conductive line pattern 120 includes a first conductive line portion 1201, and the second conductive line pattern 220 includes a second conductive line portion 2201. Both the first conductive line portion 1201 and the second conductive line portion 2201 are made of metallic material. Further, both the first conductive line portion 1201 and the second conductive line portion 2201 are located in the inner layer of the bonding surface. Please refer to the attached drawing. Figure 5AAs shown, in some embodiments, the first conductive line portion 1201 and the second conductive line portion 2201 may be fabricated on the same layer as the circuit layer in the first type of chip unit 110 and / or the second type of chip unit 210; furthermore, the first conductive line pattern 120 also includes a first conductive connection portion 1202, and the second conductive line pattern 220 also includes a second conductive connection portion 2202. Please refer to the attached diagram. Figure 5A As shown, the first conductive connection portion 1202 and the second conductive connection portion 2202 adopt through-hole technology to lead the first conductive line portion 1201 and the second conductive line portion 2201 to the surface layer of the bonding surface, respectively. Both the first conductive connection portion 1202 and the second conductive connection portion 2202 are made of metal material.

[0050] In some embodiments, the first conductive line pattern 120 includes a first conductive line portion 1201, and the second conductive line pattern 220 includes a second conductive line portion 2201. Both the first conductive line portion 1201 and the second conductive line portion 2201 are made of metallic material. Further, both the first conductive line portion 1201 and the second conductive line portion 2201 are located on the surface layer of the bonding surface. Please refer to the attached drawing. Figure 5B As shown, in some embodiments, the first conductive line portion 1201 and the second conductive line portion 2201 are separately fabricated on the surface layer of the bonding surface; furthermore, the first conductive line pattern 120 also includes a first conductive connection portion 1202, and the second conductive line pattern 220 also includes a second conductive connection portion 2202. Please refer to the attached drawing. Figure 5B As shown, the first conductive connection portion 1202 and the second conductive connection portion 2202 are also located on the surface of the bonding surface. At this time, the first conductive line portion 1201 and the first conductive connection portion 1202 are integrally formed, and the second conductive line portion 2201 and the second conductive connection portion 2202 are integrally formed. The first conductive connection portion 1202 and the second conductive connection portion 2202 are also made of metal material, which serves as the bonding connection portion during mixed bonding.

[0051] Furthermore, when the first wafer 100 and the second wafer 200 are hybrid bonded, each first type of chip unit 110 and each second type of chip unit 210 corresponds one-to-one with each other, and each first conductive line pattern 120 and each second conductive line pattern 220 also corresponds one-to-one with each other. The first type of chip unit 110 and the second type of chip unit 210 can be selected as logic chips such as GPUs, CPUs, MCUs, and AI chips; or memory chips such as DRAM, SDRAM, ROM, and NAND; or sensing chips such as MEMS, fingerprint sensors, microphones, and image sensors. Please refer to the appendix. Figure 6A -C, which shows a structural schematic diagram of a set of corresponding first conductive line patterns 120 and second conductive line patterns 220, through hybrid bonding, attached Figure 6A The first conductive line pattern 120 in the middle is mirror-flipped, and is attached to the middle. Figure 6B The second conductive line patterns 220 in the diagram are electrically connected to each other and form as shown in the attached diagram. Figure 6C The diagram illustrates a multi-layered single-coil loop closed loop. In this loop, multiple layers of metal wiring connect one end of the innermost coil to one end of the outermost coil, forming the loop. Further, the first conductive line pattern 120 includes a first conductive line portion 1201 and a first conductive connection portion 1202, and the second conductive line pattern 220 includes a second conductive line portion 2201 and a second conductive connection portion 2202. The first conductive line portion 1201 and the second conductive line portion 2201 constitute the main coil portion of the loop closed loop. Multiple layers of metal wiring connect one end of the innermost coil of the first conductive line portion 1201 or the second conductive line portion 2201 to one end of the outermost coil. Figure 6B -C only shows an embodiment in which one end of the innermost coil of the second conductive line portion 2201 is connected to one end of the outermost coil; meanwhile, the first conductive connection portion 1202 and the second conductive connection portion 2202 constitute the bonding connection portion of the ring-shaped closed loop.

[0052] Furthermore, for multi-layer single-coil wiring methods, the following can be used: Figure 6C The diagram shows a coil structure with connected ends. Compared to a single-layer multi-coil wiring method, this structure increases the complexity of the manufacturing process. However, this wiring method amplifies the current signal, making it easier to detect electrical signals. It also amplifies the signal difference between well-connected and poorly connected circuits, making detection easier.

[0053] Appendix Figure 6C The top view of the loop closed loop of the multilayer single coil shown can be rectangular. Furthermore, the top view of the loop closed loop can also be circular, elliptical, rhomboid, polygonal, etc., but is not limited to the above shapes. The top view of the loop closed loop that can be used to directly detect the connection status of metal interconnects after wafer bonding is within the scope of protection of this invention.

[0054] Appendix Figure 7A -B is a three-dimensional structural diagram of the loop closed loop portion of the multilayer single coil in some embodiments of the present invention.

[0055] In some embodiments, the first conductive line pattern 120 includes a first conductive line portion 1201, and the second conductive line pattern 220 includes a second conductive line portion 2201. Both the first conductive line portion 1201 and the second conductive line portion 2201 are made of metallic material. Further, both the first conductive line portion 1201 and the second conductive line portion 2201 are located in the inner layer of the bonding surface. Please refer to the attached drawing. Figure 7A As shown, in some embodiments, the first conductive line portion 1201 and the second conductive line portion 2201 may be fabricated on the same layer as the circuit layer in the first type of chip unit 110 and / or the second type of chip unit 210; further, through multilayer metal wiring, one end of the innermost layer of the coil is connected to one end of the outermost coil; further, the first conductive line pattern 120 further includes a first conductive connection portion 1202, and the second conductive line pattern 220 further includes a second conductive connection portion 2202. Please refer to the attached diagram. Figure 7A As shown, the first conductive connection portion 1202 and the second conductive connection portion 2202 adopt through-hole technology to lead the first conductive line portion 1201 and the second conductive line portion 2201 to the surface layer of the bonding surface, respectively. Both the first conductive connection portion 1202 and the second conductive connection portion 2202 are made of metal material.

[0056] In some embodiments, the first conductive line pattern 120 includes a first conductive line portion 1201, and the second conductive line pattern 220 includes a second conductive line portion 2201. Both the first conductive line portion 1201 and the second conductive line portion 2201 are made of metallic material. Further, both the first conductive line portion 1201 and the second conductive line portion 2201 are located on the surface layer of the bonding surface. Please refer to the attached drawing. Figure 7B As shown, in some embodiments, the first conductive line portion 1201 and the second conductive line portion 2201 are separately fabricated on the surface layer of the bonding surface; further, one end of the innermost layer of the coil is connected to one end of the outermost coil through multilayer metal wiring; further, the first conductive line pattern 120 also includes a first conductive connection portion 1202, and the second conductive line pattern 220 also includes a second conductive connection portion 2202. Please refer to the attached diagram. Figure 7B As shown, the first conductive connection portion 1202 and the second conductive connection portion 2202 are also located on the surface of the bonding surface and are respectively connected to the first conductive line portion 1201 and the second conductive line portion 2201; the first conductive connection portion 1202 and the second conductive connection portion 2202 are both made of metal material, which serves as the bonding connection portion during hybrid bonding.

[0057] In some embodiments, the closed loop can be located in an area outside the main circuit area of ​​the chip cell, such as in the bonding monitor pad or dicing area. This allows for direct detection of the interconnect connection status after wafer bonding without affecting the main circuit area of ​​the chip cell, thereby reducing production costs and improving production efficiency.

[0058] In some embodiments, the present invention also provides a method for detecting semiconductor structures to solve the technical problem that the connection status of metal interconnects after wafer bonding cannot be directly detected in the prior art.

[0059] Appendix Figure 8 This is a schematic diagram of a method for detecting semiconductor structures in a specific embodiment of the present invention.

[0060] Furthermore, a method for detecting semiconductor structures is provided, comprising the aforementioned first wafer 100 and second wafer 200, wherein the first wafer 100 and the second wafer 200 are wafer-bonded through the first bonding surface and the second bonding surface, and after bonding, the first conductive line pattern 120 and the second conductive line pattern 220 are electrically connected to each other and form a complete closed loop. Furthermore, a detection probe is provided, which is placed above the closed loop for detecting the wafer bonding result.

[0061] Furthermore, the detection probe is an eddy current detection probe, which generates an alternating magnetic field, causing an induced current to be generated in the loop closed circuit within the alternating magnetic field; furthermore, the eddy current detection probe also provides a detection element, which determines the connection status of the metal interconnects after wafer bonding by detecting changes in the induced current.

[0062] Eddy current testing is a non-destructive testing method based on the principle of electromagnetic induction, applicable to conductive materials. When a conductor is placed in an alternating magnetic field, an induced current exists, i.e., eddy currents are generated. Due to changes in various factors of the conductor itself (such as conductivity, permeability, shape, size, defects, etc.), the eddy currents will change. The testing method that uses this phenomenon to determine the properties and state of the conductor is called eddy current testing.

[0063] This invention provides a method for detecting semiconductor structures by setting a first conductive line pattern 120 and a second conductive line pattern 220 to form a complete closed loop. The method employs the eddy current detection principle. Please refer to the appendix. Figure 8As shown, the direction of the eddy currents in the loop is opposite to the direction of the current in the coil of the alternating magnetic field applied to the loop. The alternating magnetic field generated by the eddy currents also produces alternating magnetic field lines, which induce a reaction current when passing through the excitation coil. If the eddy currents in the loop change, this reaction current also changes. Measuring this change allows us to measure the change in the eddy currents, thus obtaining information about the loop. The distribution of the eddy currents and their magnitude are determined by the shape and size of the coil, the test frequency, the conductivity, permeability, shape and size of the loop, the distance between the coil and the loop, and any defects in the loop. By detecting the eddy currents in the loop, we can obtain information about the material, defects, shape, and size of the loop. The aforementioned closed-loop ring is a special marking circuit pattern designed in this invention. It is used to directly detect the connection status of metal interconnects after wafer bonding. By detecting the eddy currents in the closed-loop ring, the connection status of the closed-loop ring can be determined. At the same time, the connection status of the metal interconnects after wafer bonding can also be determined. It is not necessary to perform wafer electrical testing after slicing or back-end wiring is completed at the current site. This allows for obtaining the connection status of the metal interconnects, thereby reducing production costs and improving production efficiency.

[0064] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0065] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0066] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure for non-destructive testing, characterized in that, The semiconductor structure includes: A first wafer having a plurality of first-type chip units thereon, the first wafer having a first bonding surface; Each of the first type of chip units has a first conductive line pattern at the first bonding surface; A second wafer having a plurality of second-type chip units thereon, the second wafer having a second bonding surface; Each second type of chip unit has a second conductive line pattern at the second bonding surface; The first wafer and the second wafer can be bonded together through the first bonding surface and the second bonding surface. After bonding, the first conductive circuit pattern and the second conductive circuit pattern are electrically connected to each other and form a closed loop. The closed loop is a coil structure. A detection probe is positioned above the closed loop.

2. The semiconductor structure according to claim 1, characterized in that, The techniques used for wafer-level bonding of the first wafer and the second wafer include: oxide bonding, fused bonding, metal diffusion bonding, fusible metal bonding, or hybrid bonding.

3. The semiconductor structure according to claim 1, characterized in that, When the first wafer and the second wafer are wafer bonded, each first type of chip unit and each second type of chip unit correspond to each other one-to-one, and each first conductive line pattern and each second conductive line pattern also correspond to each other one-to-one.

4. The semiconductor structure according to claim 1, characterized in that, The first type of chip unit and the second type of chip unit can be selected as logic chips, memory chips, or sensor chips.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The first conductive circuit pattern further includes a first conductive circuit portion and a first conductive connection portion, and the second conductive circuit pattern further includes a second conductive circuit portion and a second conductive connection portion. The first conductive circuit portion and the second conductive circuit portion constitute the main coil portion of the loop-shaped closed loop, while the first conductive connection portion and the second conductive connection portion constitute the bonding connection portion of the loop-shaped closed loop.

6. The semiconductor structure according to claim 5, characterized in that, The first conductive line portion and the second conductive line portion, as well as the first conductive connection portion and the second conductive connection portion, are all made of metallic materials.

7. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The closed loop can be a single layer with multiple coils.

8. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The loop-shaped closed loop can be a multi-layer single coil. By connecting one end of the innermost layer of the coil to one end of the outermost layer of the coil through multi-layer metal wiring, a loop-shaped closed loop of multi-layer single coil is formed.

9. The semiconductor structure according to claim 5, characterized in that, Both the first conductive line portion and the second conductive line portion are located in the inner layer of the bonding surface. The first conductive line portion and the second conductive line portion can be fabricated in the same layer as the circuit layer in the first type of chip unit and / or the second type of chip unit. The first conductive connection portion and the second conductive connection portion adopt through-hole technology to lead the first conductive line portion and the second conductive line portion to the surface layer of the bonding surface, respectively.

10. The semiconductor structure according to claim 5, characterized in that, Both the first conductive line portion and the second conductive line portion are located on the surface layer of the bonding surface, and the first conductive connection portion and the second conductive connection portion are also located on the surface layer of the bonding surface, respectively connected to the first conductive line portion and the second conductive line portion.

11. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The top view shape of the closed loop can be rectangular, circular, elliptical, rhomboid, polygonal, etc.

12. A method for detecting a semiconductor structure as claimed in any one of claims 1-11, characterized in that, The detection method includes: The aforementioned first wafer and second wafer are provided. The first wafer and the second wafer can be bonded together through the first bonding surface and the second bonding surface. After bonding, the first conductive line pattern and the second conductive line pattern are electrically connected to each other and form a closed loop. A detection probe is provided, which is placed above the annular closed loop for detecting wafer bonding results.

13. The detection method according to claim 12, characterized in that, The detection probe is an eddy current detection probe, which generates an alternating magnetic field, causing the closed loop to generate an induced current in the alternating magnetic field. The eddy current detection probe also provides a detection element to determine the connection status of the metal interconnects after wafer bonding by detecting changes in the induced current.

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