Multi-chip integrated circuit packaging method

Abstract

The present invention provides a multi-chip integrated circuit packaging method, which relates to the field of integrated circuit packaging technology. A multi-chip integrated circuit packaging method includes the following steps: silicon wafer reflow, film lamination, silicon wafer cutting processing, then converting the silicon wafer carrier, performing flux padding, and removing the flux remaining between the chip and the substrate after the chip connection through controlled collapse chip welding. Before injection molding, residual moisture on the chip and the substrate is removed, and liquid epoxy is poured between the chip and the substrate and along the periphery of the chip to seal. Finally, the FCBGA1 component is loaded into the aging board for aging testing to remove defective products. Through controlled collapse chip welding, the spherical bumps are not deformed, thereby ensuring the integrity and performance of the chip. Although the power consumption of the BGA increases, the controlled collapse chip method is used for welding, which can improve the electrothermal performance, reduce the signal transmission delay, and greatly improve the adaptability frequency and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a multi-chip integrated circuit packaging method. Background Art

[0002] The original definition of electronic packaging is to protect circuit chips from the influence of the surrounding environment (including physical and chemical influences). Therefore, in the initial microelectronic packaging, metal cans were used as the outer shell to protect fragile electronic components in a completely isolated and airtight manner from the outside world. However, with the development of integrated circuit technology, especially the continuous improvement of chip passivation layer technology, the function of packaging is also slowly changing. It is generally believed that packaging has four major functions, namely power distribution, signal distribution, heat dissipation and packaging protection. Its function is to connect the integrated circuit device to the system, including electrical connection and physical connection. At present, the IO lines of integrated circuit chips are increasing. Their power supply and signal transmission must be connected to the system through packaging. The speed of chips is getting faster and faster, and the power is getting bigger and bigger, which makes the heat dissipation problem of chips more and more serious. Due to the improvement of the quality of chip passivation layer, the commonly used packaging technology can no longer meet the packaging requirements of multi-chip integrated circuits. Summary of the Invention

[0003] In view of the shortcomings of the existing technology, the present invention provides a multi-chip integrated circuit packaging method, which solves the problem that the commonly used chip packaging technology cannot adapt to multi-chip integrated circuits.

[0004] To achieve the above objectives, the present invention is implemented through the following technical solutions: A multi-chip integrated circuit packaging method includes the following steps:

[0005] Step 1: First, the silicon wafer is dried to remove unnecessary components and prepare for film lamination. The solder joints are fused to change the mushroom shape into a spherical shape, which will produce a thermal oxide layer to prevent the solder joints from being oxidized uncontrollably during the two processes of silicon wafer cutting and cleaning.

[0006] Step 2: A layer of tape is applied to the back of the wafer, and then it is sent to the wafer cutting machine for cutting. After cutting, the dies will be neatly arranged and pasted on the tape. At the same time, the support of the frame can prevent the dies from colliding due to the wrinkles of the tape, which is convenient for the handling process.

[0007] Step 3: Use diamond cutting tools, laser beams, or other methods to separate the wafer with integrated circuit dies into individual dies for packaging. Remove the FCBGA1 substrate from the transport tray and place it in the front-end stainless steel tray. Apply enough flux to the substrate by stencil printing to wet the surface area where the chip is to be attached.

[0008] Step 4: Print solder paste on the capacitor pads of the substrate, bond the chip and capacitor to the FCBGA1 substrate, and solder them using the controlled collapse chip method. Use evaporative sputtering to deposit an adhesion metal layer, a diffusion barrier metal layer, and a conductive metal layer, respectively. Then, electroplating is performed to form bumps. After passing through a reflow oven, connect the solder balls between the chip and substrate to ensure electrical continuity between the two. Remove any remaining flux between the chip and substrate after the chip is connected. Before injection molding, remove any residual moisture from the chip and substrate.

[0009] Step 5: Pour liquid epoxy between the chip and substrate and around the chip to seal this area and provide mechanical support for the connection between the chip and substrate. The FCBGA1 components are moved from the stainless steel tray to the tray used by the back-end. The products are visually inspected for surface defects and the defect-free FCBGA1 components are stored in the semi-finished product warehouse.

[0010] Step 6: Install the FCBGA1 components into the aging board. After aging, remove the components from the aging board and conduct electrical performance tests. Defective products are removed again, and a logo is engraved on the top surface of the package module of good products.

[0011] Step 7: Place the processed FCBGA1 component in a low-temperature oven and bake it at 40-45°C for 20-30 minutes to remove moisture from the inside of the FCBGA1 component. Finally, stick the solder ball on the welding area and heat it to melt the solder ball and fix it on the circuit board.

[0012] Preferably, in step 4, the bumps and the metal pads on the substrate are interconnected by utilizing the shrinkage force generated when the photosensitive resin is cured.

[0013] Preferably, in step five, when the products arrive at the semi-finished product warehouse from the front-end, they will be some very small LOTs. SFGI will check the properties of the LOT, combine the chips that can be combined into a large LOT, and print out the TFPO form of the new LOT. On the form, there will be the new LOT number, product type and some data to record the process of this LOT in the back-end.

[0014] Preferably, in step 4, since the degree of collapse of the solder bump can be controlled, the welding unevenness caused by defects in the chip and the substrate can be compensated, so that all bumps can be reliably interconnected. Due to the self-alignment effect produced by the surface tension of the Pb / Sn solder, even if the bump deviates by half of the diameter of the solder bump (for example, when the bump diameter is 100-150 μm, the maximum deviation is 50-75 μm), the bump can be restored to the center position during solder reflow.

[0015] Preferably, in step 4, the area of the pins connected by the separation layer within the colloid cannot exceed 10%-12% of the front area of the colloid, and the number of pins connected by the separation layer cannot exceed 1 / 5 of the total number of pins.

[0016] Preferably, the delamination caused by the conductive adhesive around the chip in step 5 should not exceed 8%-10% of the front area of the adhesive.

[0017] The present invention provides a multi-chip integrated circuit packaging method. It has the following beneficial effects:

[0018] The present invention firstly processes the silicon wafer through reflow, film lamination and silicon wafer cutting, then converts the carrier of the silicon wafer, performs flux padding, and performs controlled collapse chip welding. An adhesion metal layer, a diffusion barrier metal layer and a conductive metal layer are deposited respectively by an evaporative sputtering method, and then the layers are electroplated to form bumps, which are then formed into spherical shapes after reflow. When the layers are connected to the metal welding area on the substrate and reflowed, the welding pressure during the connection of the general Au hard bumps can be greatly reduced, and the degree of collapse of the solder bumps can be controlled by the pressure applied to the chip. When the metal welding area on the substrate is coated with low-melting-point Pb / Sn solder is welded with a high-melting-point controlled collapse chip. When the bump connection is reflowed, the spherical bumps of the controlled collapse chip welding will not be deformed, thereby ensuring the integrity and performance of the chip. Then, organic fillers are poured between the chip and the substrate to improve the reliability of the controlled collapse chip welding. The chip is pasted and reflowed, and the excess flux is removed. Then, the package is pre-baked and cured. Although the power consumption of BGA increases, the controlled collapse chip method is used for welding, which can improve the electrothermal performance, and the signal transmission delay is small, and the adaptability frequency and reliability are greatly improved. DETAILED DESCRIPTION

[0019] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0020] Example 1:

[0021] An embodiment of the present invention provides a multi-chip integrated circuit packaging method, comprising the following steps:

[0022] Step 1: First, the silicon wafer is dried to remove unnecessary components and prepare for film lamination. The solder joints are fused to change the mushroom shape into a spherical shape, which will produce a thermal oxide layer to prevent the solder joints from being oxidized uncontrollably during the two processes of silicon wafer cutting and cleaning.

[0023] Step 2: A layer of tape is applied to the back of the wafer, and then it is sent to the wafer cutting machine for cutting. After cutting, the dies will be neatly arranged and pasted on the tape. At the same time, the support of the frame can prevent the dies from colliding due to the wrinkles of the tape, which is convenient for the handling process.

[0024] Step 3: Use diamond cutting tools, laser beams, or other methods to separate the wafer with integrated circuit dies into individual dies for packaging. Remove the FCBGA1 substrate from the transport tray and place it in the front-end stainless steel tray. Apply enough flux to the substrate by stencil printing to wet the surface area where the chip is to be attached.

[0025] Step 4: Print solder paste on the capacitor pads of the substrate, bond the chip and capacitor to the FCBGA1 substrate, and solder them using the controlled collapse chip method. Use evaporative sputtering to deposit an adhesion metal layer, a diffusion barrier metal layer, and a conductive metal layer, respectively. Then, electroplating is performed to form bumps. After passing through a reflow oven, connect the solder balls between the chip and substrate to ensure electrical continuity between the two. Remove any remaining flux between the chip and substrate after the chip is connected. Before injection molding, remove any residual moisture from the chip and substrate.

[0026] Provide energy to destroy the oxide layer and contaminants on the surface to be welded, causing plastic deformation of the metal in the welding area, so that the lead is in close contact with the surface to be welded, reaching the range of interatomic attraction and causing atomic diffusion between the interfaces to form a weld point.

[0027] Step 5: Pour liquid epoxy between the chip and substrate and around the chip to seal this area and provide mechanical support for the connection between the chip and substrate. The FCBGA1 components are moved from the stainless steel tray to the tray used by the back-end. The products are visually inspected for surface defects and the defect-free FCBGA1 components are stored in the semi-finished product warehouse.

[0028] Step 6: Install the FCBGA1 components into the burn-in board. After aging, remove the components from the burn-in board. The purpose of the burn-in test is to provide a means of strengthening the product before providing it to customers, so as to eliminate components with short-term failures. Then, electrical performance tests are performed to eliminate defective products again, and a logo is engraved on the top surface of the package module of good products.

[0029] Step 7: Place the processed FCBGA1 component in a low-temperature oven and bake it at 40-45°C for 20-30 minutes to remove moisture from the inside of the FCBGA1 component. Finally, stick the solder ball on the welding area and heat it to melt the solder ball and fix it on the circuit board.

[0030] Multiple MCMs can be mounted on a multi-layer PCB. If their I / Os are arranged as a solder point array (SGA), each contact is connected to the nearest pad on the PCB. This greatly shortens the length of the leads that originally led the MCM's I / Os around the package shell and then interconnected with the PCB, thereby improving electrical performance and reliability.

[0031] Through controlled collapse chip welding, an adhesion metal layer, a diffusion barrier metal layer and a conductive metal layer are deposited separately by evaporation sputtering, and then raised by electroplating to form bumps, which are then formed into spherical shapes after reflow. When connected to the metal welding area on the substrate and reflowed, the welding pressure during general Au hard bump connection can be greatly reduced, and the degree of collapse of the solder bump can be controlled by applying pressure to the chip. When the metal welding area on the substrate is coated with low-melting-point Pb / Sn solder and welded to the high-melting-point controlled collapse chip, the spherical bumps of the controlled collapse chip welding do not deform when the bump connection is reflowed, thereby ensuring the integrity and performance of the chip. Injecting organic fillers between the chip and the substrate will improve the reliability of the controlled collapse chip welding.

[0032] Example 2:

[0033] In the above embodiment, the shrinkage force generated by the curing of the photosensitive resin is utilized in step 4 to interconnect the bumps and the metal pads on the substrate. Since the degree of collapse of the solder bumps can be controlled in step 4, soldering unevenness caused by defects between the chip and the substrate can be compensated, allowing all bumps to be reliably interconnected. Due to the self-alignment effect generated by the surface tension of the Pb / Sn solder, even if the bumps deviate by half their diameter (e.g., a maximum deviation of 50 to 75 μm when the bump diameter is 100 to 150 μm), the bumps can be returned to their center position during solder reflow. The chip is then pasted and reflowed, excess flux is removed, and the package is pre-baked and packaged before the package material is cured. Although the BGA's power consumption increases, the controlled collapse chip method is used for soldering, thereby improving electrothermal performance, minimizing signal transmission delay, and significantly increasing frequency adaptability and reliability.

[0034] In step 4, the area of the pins connected by the separation layer inside the colloid should not exceed 10%-12% of the front area of the colloid. At the same time, the number of pins connected by the separation layer should not exceed 1 / 5 of the total number of pins.

[0035] In step 5, the delamination caused by the conductive adhesive around the chip should not exceed 8%-10% of the front area of the adhesive. In step 5, when the products arrive at the semi-finished product warehouse from the front end, they will be some very small lots. SFGI will check the properties of the lots, combine the chips that can be combined into a large lot, and print out the TFPO form of the new lot. On the form, there will be the new lot number, product type and some data to record the process of this lot in the back end.

[0036] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A multi-chip integrated circuit packaging method, characterized in that: The following steps are involved: Step 1: First, the silicon wafer is dried to prepare for film lamination. The solder joints are fused to change the mushroom shape into a spherical shape, which will produce a thermal oxide layer to prevent the solder joints from being oxidized uncontrollably during the two processes of silicon wafer cutting and cleaning. Step 2: A layer of tape is applied to the back of the wafer, and then it is sent to the wafer cutting machine for cutting. After cutting, the dies will be neatly arranged and pasted on the tape. At the same time, the support of the frame can prevent the dies from colliding due to the wrinkles of the tape, which is convenient for the handling process. Step 3: Use diamond cutting tools and laser beams to separate the wafer with integrated circuit dies into individual dies for packaging. Remove the FCBGA1 substrate from the transport tray and place it in the front-end stainless steel tray. Apply enough flux to the substrate through template printing to wet the surface area where the chip is attached. Step 4: Print solder paste on the capacitor pads of the substrate, bond the chip and capacitor to the FCBGA1 substrate, and solder them using the controlled collapse chip method. Use evaporative sputtering to deposit an adhesion metal layer, a diffusion barrier metal layer, and a conductive metal layer, respectively. Then, electroplating is performed to form bumps. After passing through a reflow oven, connect the solder balls between the chip and substrate to ensure electrical continuity between the two. Remove any remaining flux between the chip and substrate after the chip is connected. Before injection molding, remove any residual moisture from the chip and substrate. Step 5: Pour liquid epoxy between the chip and substrate and around the chip to seal this area and provide mechanical support for the connection between the chip and substrate. The FCBGA1 components are moved from the stainless steel tray to the tray used by the back-end. The products are visually inspected for surface defects and the defect-free FCBGA1 components are stored in the semi-finished product warehouse. Step 6: Install the FCBGA1 components into the aging board. After aging, remove the components from the aging board and conduct electrical performance tests. Defective products are removed again, and a logo is engraved on the top surface of the package module of good products. Step 7: Place the processed FCBGA1 component in a low-temperature oven and bake it at 40-45°C for 20-30 minutes to remove moisture from the inside of the FCBGA1 component. Finally, stick the solder ball on the welding area and heat it to melt the solder ball and fix it on the circuit board.

2. The multi-chip integrated circuit packaging method according to claim 1, wherein: In the fourth step, the shrinkage force generated when the photosensitive resin is cured is used to interconnect the bumps and the metal pads on the substrate.

3. The multi-chip integrated circuit packaging method according to claim 1, wherein: In step 5, when the product arrives at the semi-finished product warehouse from the front-end, it will exist in the form of a smaller batch LOT. The SFGI system will combine the chips that can be combined into a large LOT according to the LOT attributes and print out the TFPO form of the new LOT. On the TFPO form, there will be the new LOT number and product type, recording the process of this LOT in the back-end.

4. The multi-chip integrated circuit packaging method according to claim 1, wherein: In step 4, by controlling the degree of collapse of the solder bumps, the soldering unevenness caused by defects in the chip and the substrate can be compensated, so that all bumps can be reliably interconnected. Due to the self-alignment effect generated by the surface tension of the Pb / Sn solder, even if the bump deviates by half the diameter of the solder bump, when the bump diameter is 100-150 μm, the maximum deviation can be 50-75 μm, ensuring that the bump returns to the center position during solder reflow.

5. The multi-chip integrated circuit packaging method according to claim 1, wherein: In the fourth step, the area of the pins connected by the separation layer inside the colloid cannot exceed 10%-12% of the front area of the colloid, and the number of pins connected by the separation layer cannot exceed 1 / 5 of the total number of pins.

6. The multi-chip integrated circuit packaging method according to claim 1, wherein: In the step 5, the delamination caused by the conductive adhesive around the chip should not exceed 8%-10% of the front area of the adhesive.