Germanium-silicon heterojunction bipolar transistor structure and method of forming the same

Abstract

A structure of a germanium-silicon heterojunction bipolar transistor and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a base and a collector region on the base, the collector region comprising a first region and a second region on both sides of the first region; forming a main base region on the first region and an outer base region on the second region, the outer base region being on the sidewall surface and part of the top surface of the main base region; and forming an emitter region on part of the surface of the main base region, the emitter region and the outer base region being separated from each other, and the contact area of the outer base region with the main base region being increased, which is conducive to reducing the connection resistance of the outer base region, thereby improving the cutoff frequency of the device and improving the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a structure of a germanium-silicon heterojunction bipolar transistor and a forming method thereof. BACKGROUND

[0002] With the development of society and the demand of modern communication for high performance and low cost RF components under high frequency band, the traditional silicon material device cannot meet these new requirements in performance. Since the high frequency performance of germanium-silicon heterojunction bipolar transistor (HBT) is much better than that of silicon bipolar transistor, and the compatibility with silicon process makes it have the low price of silicon, the germanium-silicon technology has made great progress, and the germanium-silicon HBT technology has become one of the mainstream technologies in the RF integrated circuit market, and has a profound influence on the development of modern communication technology.

[0003] In the prior art, the development of the cut-off frequency of the device is limited due to the high connection resistance of the external base region in forming the germanium-silicon HBT device. Therefore, improving the device external base region connection process to improve the performance of the device has become a hot spot of current research. SUMMARY

[0004] The technical problem solved by the present application is to provide a structure of a germanium-silicon heterojunction bipolar transistor and a forming method thereof to improve the performance of the formed germanium-silicon heterojunction bipolar transistor structure.

[0005] To solve the above technical problem, the technical scheme of the present application provides a structure of a germanium-silicon heterojunction bipolar transistor, comprising: a substrate, the substrate comprising a base and a collector region located on the base, the collector region comprising a first region and a second region located on both sides of the first region; a main base region located on the first region; an external base region located on the side wall and part of the top surface of the main base region; an emitter region located on part of the surface of the main base region, the emitter region and the external base region being isolated from each other.

[0006] Optionally, the external base region comprises a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located on the top surface of the second region, the top surface of the first epitaxial layer is higher than the top surface of the main base region, the first epitaxial layer has opposite first and second side walls, the first side wall is in contact with the side wall surface of the main base region, and the second epitaxial layer is located on part of the top surface of the main base region and the first side wall surface.

[0007] Optionally, the external base region further comprises a third epitaxial layer, the third epitaxial layer is located on the second side wall surface and part of the top surface of the first epitaxial layer.

[0008] Optionally, a protective layer is further included between the emitter region, the outer base region and the main base region, and the protective layer exposes the top surface of the outer base region and the top surface of the emitter region.

[0009] Accordingly, the technical scheme of the present application further provides a forming method of a GeSi heterojunction bipolar transistor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a base and a collector region on the base, and the collector region comprises a first region and second regions on both sides of the first region; forming a main base region on the first region and an outer base region on the second regions, wherein the outer base region is on the sidewall surface and part of the top surface of the main base region; and forming an emitter region on part of the surface of the main base region, wherein the emitter region and the outer base region are separated from each other.

[0010] Optionally, the outer base region comprises a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is on the top surface of the second region, the top surface of the first epitaxial layer is higher than the top surface of the main base region, the first epitaxial layer has opposite first and second sidewalls, the first sidewall is in contact with the sidewall surface of the main base region, and the second epitaxial layer is on part of the top surface of the main base region and the first sidewall surface; and the forming method of the first and second epitaxial layers comprises the following steps: forming a first sacrificial layer on the first region and a second sacrificial layer on the first sacrificial layer, wherein the first and second sacrificial layers expose the top surface of the second region; forming a first epitaxial layer on the top surface of the second region, wherein the top surface of the first epitaxial layer is higher than the top surface of the first sacrificial layer, the first epitaxial layer has opposite first and second sidewalls, and the first sidewall is adjacent to the sidewalls of the first and second sacrificial layers; forming a third sacrificial layer on the surface of the substrate, the second sidewall and the top surface of the first epitaxial layer, and removing the second sacrificial layer to form a first opening in the first epitaxial layer and the third sacrificial layer, wherein the first opening exposes part of the first sidewall; and forming a second epitaxial layer on the first sidewall surface exposed by the first opening.

[0011] Optionally, the forming process of the first epitaxial layer comprises a selective epitaxial growth process, and the forming process of the second epitaxial layer comprises a selective epitaxial growth process.

[0012] Optionally, the forming method of the first and second sacrificial layers comprises the following steps: forming a first sacrificial material layer on the substrate and a second sacrificial material layer on the first sacrificial material layer; etching the first and second sacrificial material layers until the surface of the substrate is exposed, so that the first sacrificial material layer is the first sacrificial layer and the second sacrificial material layer is the second sacrificial layer.

[0013] Optionally, the material of the first and second sacrificial layers is different; the material of the first sacrificial layer comprises a dielectric material, the dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride; the material of the second sacrificial layer comprises a dielectric material, the dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0014] Optionally, the forming process of the third sacrificial layer and the first opening comprises: forming a third sacrificial material layer on the substrate surface, the first epitaxial layer, and the surface of the second sacrificial layer; forming a first patterned layer on the surface of the third sacrificial material layer, the first patterned layer exposing the surface of the third sacrificial material layer on the second sacrificial layer; etching the third sacrificial material layer with the first patterned layer as a mask to form the third sacrificial layer, the third sacrificial layer exposing the second sacrificial layer; and removing the second sacrificial layer to form the first opening.

[0015] Optionally, the material of the third sacrificial layer comprises a dielectric material, the dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0016] Optionally, the first epitaxial layer and the second epitaxial layer are initial outer base regions; the method comprises: after forming the initial outer base regions, forming the main base region; and after forming the main base region, forming the emission region.

[0017] Optionally, the forming method of the main base region and the emission region comprises: forming a first mask layer on the surface of the third sacrificial layer and the surface of the initial outer base region, the first mask layer exposing part of the first sacrificial layer; replacing the first sacrificial layer with the main base region; and forming an emission region on the main base region.

[0018] Optionally, the forming method of the emission region comprises: forming an emission material layer on the surface of the first mask layer and the surface of the main base region, the top of the emission material layer being higher than the surface of the first mask layer; and planarizing the emission material layer until the top surface of the first mask layer is exposed.

[0019] Optionally, the forming process of the emission material layer comprises a non-selective epitaxial growth process.

[0020] Optionally, the forming process of the main base region comprises a selective epitaxial growth process.

[0021] Optionally, the method of replacing the first sacrificial layer with a main base region comprises: removing the first sacrificial layer to form a second opening between the initial outer base region and the first region; and forming the main base region on the surface of the first region exposed by the second opening.

[0022] Optionally, the method of forming the first mask layer comprises: forming a first mask material layer on the surface of the third sacrificial layer and the surface of the initial outer base region; forming a second patterning layer on the surface of the first mask material layer, the second patterning layer exposing a portion of the surface of the first mask material layer on the first sacrificial layer; and etching the first mask material layer using the second patterning layer as a mask to form the first mask layer.

[0023] Optionally, the outer base region further comprises a third epitaxial layer located on the surface of the second sidewall and a portion of the top surface of the first epitaxial layer; and the method of forming the third epitaxial layer comprises: forming a second mask layer on the surface of the first mask layer and the surface of the emission region; patterning the first mask layer and the second mask layer to form a transition protection layer, the transition protection layer exposing a portion of the third sacrificial layer; removing the third sacrificial layer to expose a portion of the sidewall and the top surface of the transition outer base region; and forming the third epitaxial layer on the exposed portion of the sidewall and the top surface of the transition outer base region to form the outer base region together with the initial outer base region.

[0024] Optionally, the method further comprises: forming a protection layer between the emission region, the outer base region, and the main base region, the protection layer exposing a portion of the top surface of the outer base region and the top surface of the emission region.

[0025] Optionally, the method of forming the protection layer comprises: after forming the outer base region, patterning the transition protection layer to form the protection layer.

[0026] Optionally, the method of forming the protection layer further comprises: forming a third patterning layer on the surface of the substrate and the transition protection layer, the third patterning layer exposing a portion of the transition protection layer; etching the transition protection layer using the third patterning layer as a mask to form an intermediate protection layer, the intermediate protection layer exposing a portion of the top surface of the outer base region and being located on the sidewall and the top surface of the emission region; and etching the intermediate protection layer until the top surface of the emission region is exposed to form the protection layer.

[0027] Optionally, the forming process of the third epitaxial layer comprises a selective epitaxial growth process.

[0028] Optionally, the main base region comprises a buffer layer, a main body layer, and a cap layer located on the main body layer; the material of the buffer layer comprises silicon; the material of the main body layer comprises germanium-silicon; and the material of the cap layer comprises silicon.

[0029] Optionally, the substrate further comprises an isolation layer on the substrate, and the isolation layer is located on the collector region sidewall.

[0030] Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:

[0031] The forming method of the germanium-silicon heterojunction bipolar transistor structure provided by the technical scheme has the advantages that the outer base region is formed on the sidewall of the main base region and part of the top surface, the contact area of the outer base region with the main base region is increased, which is conducive to reducing the connection resistance of the outer base region, thereby being conducive to improving the cutoff frequency of the device and improving the performance of the device.

[0032] The germanium-silicon heterojunction bipolar transistor structure provided by the technical scheme has the advantages that the outer base region is located on the sidewall of the main base region and part of the top surface, the contact area of the outer base region with the main base region is increased, which is conducive to reducing the connection resistance of the outer base region, thereby being conducive to improving the cutoff frequency of the device and improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural schematic diagram of a germanium-silicon heterojunction bipolar transistor structure.

[0034] Figure 2 is a structural schematic diagram of another germanium-silicon heterojunction bipolar transistor structure.

[0035] Figures 3 to 17 is a structural schematic diagram of each step of the forming method of the germanium-silicon heterojunction bipolar transistor structure of the embodiment of the application. DETAILED DESCRIPTION

[0036] It should be noted that the "surface", "upper", in the specification are used to describe the relative positional relationship in space, and are not limited to whether they are in direct contact.

[0037] As described in the background, the performance of the germanium-silicon heterojunction bipolar transistor structure formed by using the prior art needs to be improved. Now, a germanium-silicon heterojunction bipolar transistor structure will be described and analyzed.

[0038] Figure 1 is a structural schematic diagram of a germanium-silicon heterojunction bipolar transistor structure.

[0039] Please refer to Figure 1The GeSi HBT structure includes: a substrate including an auxiliary collector region 101 and an isolation structure 102 on the sidewall of the auxiliary collector region 101; a main collector region 103 on the auxiliary collector region 101; a base region 104 on the main collector region 103, the base region 104 having an emitter region 105 thereon, the base region 104 having an outer base region 106 on the sidewall thereof; a dielectric layer 109 on the substrate, the main collector region 103, the base region 104, the emitter region 105 and the outer base region 106 being located in the dielectric layer 109; a first conductive plug 107 and a second conductive plug 108 in the dielectric layer 109, the first conductive plug 107 being located on the surface of the outer base region 106, and the second conductive plug 108 being located on the surface of the emitter region 105.

[0040] In the above-mentioned GeSi HBT device, the base region 104 includes a silicon buffer layer, a GeSi layer on the silicon buffer layer, and a silicon cover layer on the GeSi layer. The outer base region 106 is laterally connected with the base region 104, that is, the outer base region 106 is formed on the sidewall of the base region 104. Due to the small contact area between the outer base region 106 and the base region 104, the connection resistance of the outer base region 106 is high, which is not conducive to improving the cutoff frequency of the device.

[0041] In order to reduce the connection resistance of the outer base region, in another embodiment, a way of longitudinally connecting the outer base region and the base region is proposed. Please refer to Figure 2 .

[0042] Figure 2 is another structural schematic diagram of a GeSi HBT structure.

[0043] Please refer to Figure 2 , the GeSi HBT structure includes: a substrate including an auxiliary collector region 201 and an isolation structure 202 on the sidewall of the auxiliary collector region 201; a main collector region 203 on the auxiliary collector region 201; a base region 204 on the main collector region 203, the base region 204 including a first region I and a second region II on both sides of the first region I; an emitter region 205 on the first region I; an outer base region 206 on the second region II; a dielectric layer 209 on the substrate, the main collector region 203, the base region 204, the emitter region 205 and the outer base region 206 being located in the dielectric layer 209; a first conductive plug 207 and a second conductive plug 208 in the dielectric layer 209, the first conductive plug 207 being located on the surface of the outer base region 206, and the second conductive plug 208 being located on the surface of the emitter region 205.

[0044] In the above germanium-silicon HBT device, the outer base region 206 and the base region 204 are longitudinally connected, i.e. the outer base region 206 is located on the second region II at both ends of the base region 204. However, as the requirement for the cutoff frequency performance of the germanium-silicon HBT device is improved, the longitudinal connection mode still cannot meet the technical requirement.

[0045] To solve the above problem, the present application provides a forming method of a germanium-silicon heterojunction bipolar transistor structure, in which an outer base region is formed on the sidewall and part of the top surface of the main base region, the contact area of the outer base region with the main base region is increased, which is beneficial to reduce the connection resistance of the outer base region, thereby improving the cutoff frequency of the device and improving the performance of the device.

[0046] To make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0047] Figures 3 to 17 is a structural schematic diagram of each step of the forming method of the germanium-silicon heterojunction bipolar transistor structure of the embodiment of the present application.

[0048] Please refer to Figure 3 , a substrate is provided, which includes a substrate 300 and a collector region 301 located on the substrate 300, the collector region 301 including a first region i and a second region ii located on both sides of the first region i.

[0049] In the embodiment, the substrate further includes an isolation layer 302 located on the substrate 300, and the isolation layer 302 is located on the sidewall of the collector region 301.

[0050] In the embodiment, the material of the substrate 301 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Among them, the multi-element semiconductor material composed of III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0051] Subsequently, a main base region located on the first region i and an outer base region located on the second region ii are formed, and the outer base region is located on the sidewall surface and part of the top surface of the main base region.

[0052] In the embodiment, the outer base region includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located on the top surface of the second region ii, the top surface of the first epitaxial layer is higher than the top surface of the main base region, the first epitaxial layer has opposite first and second sidewalls, the first sidewall is in contact with the sidewall surface of the main base region, and the second epitaxial layer is located on part of the top surface of the main base region and the first sidewall surface.

[0053] In this embodiment, the method for forming the first epitaxial layer and the second epitaxial layer is described in reference [reference needed]. Figures 4 to 7 .

[0054] Please refer to Figure 4 A first sacrificial layer 303 and a second sacrificial layer 304 are formed on the first region ii, the first sacrificial layer 303 and the second sacrificial layer 304 exposing the top surface of the second region ii.

[0055] In this embodiment, the method for forming the first sacrificial layer 303 and the second sacrificial layer 304 includes: forming a first sacrificial material layer (not shown in the figure) and a second sacrificial material layer (not shown in the figure) on the substrate; etching the first sacrificial material layer and the second sacrificial material layer until the substrate surface is exposed, with the first sacrificial material layer as the first sacrificial layer 303 and the second sacrificial material layer as the second sacrificial layer 304.

[0056] The first sacrificial layer 303 and the second sacrificial layer 304 are made of different materials. Both the first sacrificial layer 303 and the second sacrificial layer 304 are used to guide the epitaxial growth of the outer base region.

[0057] The material of the first sacrificial layer 303 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the second sacrificial layer 304 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride.

[0058] In this embodiment, the material of the first sacrificial layer 303 is silicon oxide, and the material of the second sacrificial layer 304 is silicon nitride.

[0059] Please refer to Figure 5 A first epitaxial layer 305 is formed on the top surface of the second region ii. The top surface of the first epitaxial layer 305 is higher than the top surface of the first sacrificial layer 303. The first epitaxial layer 305 has opposing first sidewalls (not shown) and second sidewalls (not shown). The first sidewall is adjacent to the first sacrificial layer 303 and the second sacrificial layer 304.

[0060] In this embodiment, the formation process of the first epitaxial layer 305 includes a selective epitaxial growth process. Using a selective epitaxial growth process is beneficial for controlling the crystal growth direction of the first epitaxial layer 305.

[0061] In this embodiment, the material of the first epitaxial layer 305 is polycrystalline silicon.

[0062] Please refer to Figure 6 A third sacrificial layer 306 is formed on the substrate surface, the second sidewall and top surface of the first epitaxial layer 305, and the second sacrificial layer 304 is removed, forming a first opening 307 in the first epitaxial layer 305 and the third sacrificial layer 306, the first opening 307 exposing part of the first sidewall.

[0063] In this embodiment, the forming process of the third sacrificial layer 306 and the first opening 307 includes: forming a third sacrificial material layer (not shown in the figure) on the substrate surface, the first epitaxial layer 305 and the surface of the second sacrificial layer 304; forming a first patterning layer (not shown in the figure) on the surface of the third sacrificial material layer, the first patterning layer exposing the surface of the third sacrificial material layer on the second sacrificial layer 304; taking the first patterning layer as a mask, etching the third sacrificial material layer to form the third sacrificial layer 306, the third sacrificial layer 306 exposing the second sacrificial layer 304; removing the second sacrificial layer 304 to form the first opening 307.

[0064] In this embodiment, the material of the first patterning layer includes photoresist.

[0065] The process of removing the second sacrificial layer 304 includes one or a combination of wet etching process and dry etching process. In this embodiment, the process of removing the second sacrificial layer 304 is wet etching process.

[0066] The materials of the first sacrificial layer 303 and the second sacrificial layer 304 are different, which is beneficial to reduce the etching damage to the first sacrificial layer 303 when removing the second sacrificial layer 304.

[0067] The material of the third sacrificial layer 306 includes dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the material of the third sacrificial layer 306 and the material of the first sacrificial layer 303 are the same, both of which are silicon oxide.

[0068] Please refer to Figure 7 A second epitaxial layer 308 is formed on the first sidewall surface exposed by the first opening 307.

[0069] In this embodiment, the forming process of the second epitaxial layer 308 includes selective epitaxial growth process. Using selective epitaxial growth process is beneficial to control the crystal growth direction of the second epitaxial layer 308.

[0070] In the embodiment, the first epitaxial layer 305 and the second epitaxial layer 308 are initial outer base regions. In other embodiments, the first epitaxial layer 305 and the second epitaxial layer 308 can be outer base regions.

[0071] Subsequently, after the initial outer base regions are formed, the main base region is formed; and after the main base region is formed, the emission region is formed.

[0072] In the embodiment, the method for forming the main base region and the emission region is described in detail with reference to Figures 8 to 11 .

[0073] The method for forming the first mask layer 309 is described in detail with reference to Figure 8 .

[0074] In the embodiment, the method for forming the first mask layer 309 includes: forming a first mask material layer (not shown in the figure) on the surface of the third sacrificial layer 306 and the surface of the initial outer base region; forming a second patterning layer (not shown in the figure) on the surface of the first mask material layer, the second patterning layer exposing part of the surface of the first mask material layer on the first sacrificial layer 303; and etching the first mask material layer with the second patterning layer as a mask to form the first mask layer 309.

[0075] In the embodiment, the material of the second patterning layer includes photoresist.

[0076] The material of the first mask layer 309 includes dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In the embodiment, the material of the first mask layer 309 is silicon nitride.

[0077] Subsequently, the first sacrificial layer is replaced by the main base region. The method for replacing the first sacrificial layer by the main base region is described in detail with reference to Figures 9 to 10 .

[0078] The method for removing the first sacrificial layer 303 is described in detail with reference to Figure 9 .

[0079] In the embodiment, the process for removing the first sacrificial layer 303 is a wet etching process.

[0080] The method for forming the main base region 311 is described in detail with reference to Figure 10 .

[0081] The forming process of the main base region 311 includes a selective epitaxial growth process.

[0082] In this embodiment, the main base region 311 includes a buffer layer (not shown in the figure), a main body layer (not shown in the figure) and a cover layer (not shown in the figure) on the main body layer; the material of the buffer layer includes silicon; the material of the main body layer includes germanium-silicon; and the material of the cover layer includes silicon.

[0083] Please refer to Figure 11 The emitter region 312 is formed on part of the surface of the main base region 311, and the emitter region 312 and the outer base region are separated from each other.

[0084] In this embodiment, the forming method of the emitter region 312 includes: forming an emitter material layer (not shown in the figure) on the surface of the first mask layer 309 and the surface of the main base region 311, and the top of the emitter material layer is higher than the surface of the first mask layer 309; and planarizing the emitter material layer until the top surface of the first mask layer 309 is exposed.

[0085] In this embodiment, the forming process of the emitter material layer includes a non-selective epitaxial growth process. Due to the shape of the previous layer, the first mask layer 309 and the surface of the main base region 311 form a groove (not shown in the figure), and the emitter region is formed in the groove. The purpose of the non-selective epitaxial growth process is to make the material film of the emitter material layer grow on the surface of the main base region 211 and the first mask layer 309, which is beneficial to the filling of the material film in the groove.

[0086] In this embodiment, the outer base region further includes a third epitaxial layer, and the third epitaxial layer is located on the surface of the second side wall and part of the top surface of the first epitaxial layer 305. Specifically, the forming method of the third epitaxial layer please refer to Figures 12 to 15 .

[0087] Please refer to Figure 12 The second mask layer 313 is formed on the surface of the first mask layer 309 and the emitter region 312.

[0088] The material of the second mask layer 313 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the material of the second mask layer 313 is silicon nitride.

[0089] Please refer to Figure 13 The first mask layer 309 and the second mask layer 313 are patterned to form a transition protection layer 314, and the transition protection layer 314 exposes part of the third sacrificial layer 306.

[0090] In the embodiment, the method for patterning the first mask layer 309 and the second mask layer 313 includes: forming a fourth patterning layer (not shown in the figure) on the surface of the second mask layer 313, the fourth patterning layer not covering part of the second mask layer 313; etching the first mask layer 309 and the second mask layer 313 with the fourth patterning layer as a mask until the top surface of the third sacrificial layer 306 is exposed.

[0091] In the embodiment, the material of the fourth patterning layer includes photoresist.

[0092] The material of the third sacrificial layer 306 includes dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In the embodiment, the material of the third sacrificial layer 306 is silicon oxide.

[0093] Please refer to Figure 14 , remove the third sacrificial layer 306 to expose the transition outer base region sidewall and part of the top surface.

[0094] In the embodiment, the process for removing the third sacrificial layer 306 is a wet etching process.

[0095] Please refer to Figure 15 , form a third epitaxial layer 315 on the exposed transition outer base region sidewall and part of the top surface, and form an outer base region with the third epitaxial layer 315 and the initial outer base region.

[0096] At this point, an outer base region is formed on the sidewall and part of the top surface of the main base region 311, the contact area of the outer base region with the main base region 311 is increased, which is conducive to reducing the connection resistance of the outer base region, thereby improving the cutoff frequency of the device and improving the performance of the device.

[0097] In the embodiment, the forming process of the third epitaxial layer 315 includes a selective epitaxial growth process. The selective epitaxial growth process is conducive to controlling the crystal growth direction of the third epitaxial layer 315.

[0098] Subsequently, a protective layer is formed between the emitter region 312, the outer base region, and the main base region 311, and the protective layer exposes part of the top surface of the outer base region and the top surface of the emitter region 312.

[0099] Specifically, after the outer base region is formed, the transition protective layer 314 is patterned to form the protective layer. In the embodiment, the forming method of the protective layer please refer to Figures 16 to 17 .

[0100] Please refer to Figure 16forming a third patterning layer (not shown in the figure) on the substrate and the surface of the transition protection layer, the third patterning layer exposing part of the transition protection layer; etching the transition protection layer 314 with the third patterning layer as a mask to form an intermediate protection layer 316, the intermediate protection layer 316 exposing part of the top surface of the outer base region and being located on the sidewall and top surface of the emitter region 312.

[0101] The purpose of exposing the top surface of the outer base region is to facilitate the formation of a conductive plug on the emitter region 312 in the subsequent process to lead out the main base region 311 through the outer base region.

[0102] In the embodiment, the material of the third patterning layer includes photoresist.

[0103] Please refer to Figure 17 etching the intermediate protection layer 316 until the top surface of the emitter region 312 is exposed to form the protection layer 317.

[0104] The purpose of exposing the emitter region 312 is to facilitate the formation of a conductive plug on the emitter region 312 in the subsequent process to lead out the emitter region 312.

[0105] Correspondingly, the embodiment of the present application also provides a germanium-silicon heterojunction bipolar transistor structure formed by the above method, please continue to refer to Figure 17 , comprising: a substrate including a base 300 and a collector region 301 located on the base 300, the collector region 301 including a first region i and a second region ii located on both sides of the first region i; a main base region 311 located on the first region i; an outer base region located on the sidewall and part of the top surface of the main base region 311; an emitter region 312 located on part of the surface of the main base region 311, the emitter region 312 and the outer base region being isolated from each other.

[0106] At this point, the outer base region located on the sidewall and part of the top surface of the main base region 311 has an increased contact area with the main base region 311, which is conducive to reducing the connection resistance of the outer base region, thereby improving the cutoff frequency of the device and improving the performance of the device.

[0107] In the embodiment, the outer base region includes a first epitaxial layer 305 and a second epitaxial layer 308, the first epitaxial layer 305 being located on the top surface of the second region ii, the top surface of the first epitaxial layer 305 being higher than the top surface of the main base region 311, the first epitaxial layer 305 having opposite first and second sidewalls, the first sidewall being in contact with the sidewall surface of the main base region 311, and the second epitaxial layer 308 being located on part of the top surface of the main base region 311 and the first sidewall surface.

[0108] In this embodiment, the outer base region further comprises a third epitaxial layer 315, which is located on the second sidewall surface and the partial top surface of the first epitaxial layer 305.

[0109] In this embodiment, the germanium-silicon heterojunction bipolar transistor structure further comprises a protective layer 317 located between the emitter region 312, the outer base region and the main base region 311, which exposes the partial top surface of the outer base region and the top surface of the emitter region 312.

[0110] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the scope of protection of the present application should be defined by the scope of the claims.

Claims

1. A method for forming a germanium-silicon heterojunction bipolar transistor structure, characterized in that, include: A substrate is provided, the substrate including a base and a current collector region located on the base, the current collector region including a first region and a second region located on both sides of the first region; A primary base region is formed on a first region and an outer base region is formed on a second region. The outer base region is located on the sidewall surface and a portion of the top surface of the primary base region. The outer base region includes a first epitaxial layer and a second epitaxial layer. The first epitaxial layer is located on the top surface of the second region and the top surface of the first epitaxial layer is higher than the top surface of the primary base region. The first epitaxial layer has opposing first and second sidewalls. The first sidewall is in contact with the sidewall surface of the primary base region. The second epitaxial layer is located on a portion of the top of the primary base region and the surface of the first sidewall. The method for forming the first epitaxial layer and the second epitaxial layer includes: forming a first sacrificial layer and a second sacrificial layer on the first sacrificial layer in the first region, wherein the first sacrificial layer and the second sacrificial layer expose the top surface of the second region; forming a first epitaxial layer on the top surface of the second region, wherein the top surface of the first epitaxial layer is higher than the top surface of the first sacrificial layer, the first epitaxial layer having opposing first sidewalls and second sidewalls, and the first sidewalls being adjacent to the sidewalls of the first sacrificial layer and the second sacrificial layer; forming a third sacrificial layer on the substrate surface, the second sidewall of the first epitaxial layer and the top surface, and removing the second sacrificial layer; forming a first opening in the first epitaxial layer and the third sacrificial layer, wherein the first opening exposes a portion of the first sidewall; and forming a second epitaxial layer on the surface of the first sidewall exposed by the first opening. An emission region is formed on a portion of the surface of the primary base region, and the emission region and the outer base region are separate from each other.

2. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The formation process of the first epitaxial layer includes a selective epitaxial growth process; the formation process of the second epitaxial layer includes a selective epitaxial growth process.

3. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The method for forming the first sacrificial layer and the second sacrificial layer includes: forming a first sacrificial material layer and a second sacrificial material layer on the substrate; etching the first sacrificial material layer and the second sacrificial material layer until the surface of the substrate is exposed, with the first sacrificial material layer as the first sacrificial layer and the second sacrificial layer as the second sacrificial layer.

4. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 3, characterized in that, The first sacrificial layer and the second sacrificial layer are made of different materials; the material of the first sacrificial layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the second sacrificial layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride.

5. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The process for forming the third sacrificial layer and the first opening includes: forming a third sacrificial material layer on the substrate surface, the first epitaxial layer, and the surface of the second sacrificial layer; forming a first patterning layer on the surface of the third sacrificial material layer, wherein the first patterning layer exposes the surface of the third sacrificial material layer on the second sacrificial layer; using the first patterning layer as a mask, etching the third sacrificial material layer to form the third sacrificial layer, wherein the third sacrificial layer exposes the second sacrificial layer; and removing the second sacrificial layer to form the first opening.

6. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 5, characterized in that, The material of the third sacrificial layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

7. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The method comprises: forming the initial outer base region using the first epitaxial layer and the second epitaxial layer as the initial outer base region; and forming the main base region after forming the main base region.

8. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 7, characterized in that, The method for forming the primary base region and the emitter region includes: forming a first mask layer on the surface of the third sacrificial layer and the surface of the initial outer base region, wherein the first mask layer exposes a portion of the first sacrificial layer; replacing the first sacrificial layer with the primary base region; and forming the emitter region on the primary base region.

9. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The method for forming the emission region includes: forming an emission material layer on the surface of the first mask layer and the surface of the main base region, wherein the top of the emission material layer is higher than the surface of the first mask layer; and planarizing the emission material layer until the top surface of the first mask layer is exposed.

10. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 9, characterized in that, The formation process of the emission material layer includes a non-selective epitaxial growth process.

11. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The formation process of the main base region includes a selective epitaxial growth process.

12. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The method of replacing the first sacrificial layer with a primary base region includes: removing the first sacrificial layer, forming a second opening between the initial outer base region and the first region; and forming the primary base region on the surface of the first region exposed by the second opening.

13. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The method for forming the first mask layer includes: forming a first mask material layer on the surface of the third sacrificial layer and the surface of the initial outer base region; forming a second patterned layer on the surface of the first mask material layer, wherein the second patterned layer exposes a portion of the surface of the first mask material layer on the first sacrificial layer; and etching the first mask material layer using the second patterned layer as a mask to form the first mask layer.

14. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 8, characterized in that, The outer base region further includes a third epitaxial layer, which is located on the surface of the second sidewall and a portion of the top surface of the first epitaxial layer; the method of forming the third epitaxial layer includes: forming a second mask layer on the surface of the first mask layer and the emitter region; patterning the first mask layer and the second mask layer to form a transition protection layer, the transition protection layer exposing a portion of the third sacrificial layer; removing the third sacrificial layer to expose the sidewall and a portion of the top surface of the initial outer base region; forming the third epitaxial layer on the exposed sidewall and a portion of the top surface of the initial outer base region, thereby forming the outer base region with the third epitaxial layer and the initial outer base region.

15. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 14, characterized in that, Also includes: A protective layer is formed between the emitter region, the outer base region, and the main base region, the protective layer exposing a portion of the top surface of the outer base region and the top surface of the emitter region.

16. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 15, characterized in that, The method for forming the protective layer includes: after forming the outer base region, graphically forming the transition protective layer to form the protective layer.

17. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 16, characterized in that, The method for forming the protective layer further includes: forming a third patterned layer on the surface of the substrate and the transition protective layer, wherein the third patterned layer exposes a portion of the transition protective layer; using the third patterned layer as a mask, etching the transition protective layer to form an intermediate protective layer, wherein the intermediate protective layer exposes a portion of the top surface of the outer base region and is located on the sidewall and top surface of the emitter region; etching the intermediate protective layer until the top surface of the emitter region is exposed to form the protective layer.

18. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 14, characterized in that, The formation process of the third epitaxial layer includes a selective epitaxial growth process.

19. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The main base region includes a buffer layer, a main body layer, and a cover layer located on the main body layer; the material of the buffer layer includes silicon; the material of the main body layer includes germanium silicon; and the material of the cover layer includes silicon.

20. The method for forming a germanium-silicon heterojunction bipolar transistor structure as described in claim 1, characterized in that, The substrate further includes an isolation layer located on the substrate, the isolation layer being located on the sidewall of the current collector region.

21. A germanium-silicon heterojunction bipolar transistor structure, characterized in that, Formed using the forming method as described in any one of claims 1 to 20, comprising: A substrate, the substrate including a base and a current collector region located on the base, the current collector region including a first region and a second region located on both sides of the first region; The primary base region located in the first region; The outer base region is located on the sidewall and part of the top surface of the main base region; The emitter region is located on a portion of the surface of the main base region, and the emitter region and the outer base region are isolated from each other.

22. The germanium-silicon heterojunction bipolar transistor structure as described in claim 21, characterized in that, The outer base region includes a first epitaxial layer and a second epitaxial layer. The first epitaxial layer is located on the top surface of the second region and the top surface of the first epitaxial layer is higher than the top surface of the main base region. The first epitaxial layer has opposing first and second sidewalls. The first sidewall is in contact with the sidewall surface of the main base region. The second epitaxial layer is located on a portion of the top of the main base region and the surface of the first sidewall.

23. The germanium-silicon heterojunction bipolar transistor structure as described in claim 22, characterized in that, The outer base region also includes a third epitaxial layer, which is located on the second sidewall surface and the top surface of a portion of the first epitaxial layer.

24. The germanium-silicon heterojunction bipolar transistor structure as described in claim 21, characterized in that, Also includes: A protective layer is located between the emitter region, the outer base region, and the main base region, the protective layer exposing a portion of the top surface of the outer base region and the top surface of the emitter region.

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