A trench type double gate power device and a manufacturing method thereof

Abstract

The application discloses a kind of trench type double-layer gate power devices, including N+ substrate, N-epitaxial layer, P well and dielectric layer;N-epitaxial layer is provided with source region trench and terminal area trench between dielectric layer;Source region trench outside is trench field oxide layer, inside has N type shield gate, isolation oxide layer, gate oxide layer and control gate, N+ source region is between P well and dielectric layer, source region contact hole is between source region trench and is connected with source region front metal layer by dielectric layer;Terminal area trench outside is terminal area trench field oxide layer, terminal area trench polysilicon is set in terminal area trench, is wrapped by terminal area trench field oxide layer and dielectric layer, before terminal area trench cutoff ring, there is avalanche resistance enhancement structure by the last terminal area trench ring of terminal area terminal area trench and its accessory structure composition.The application can increase forward on-current density, reduce on-resistance and increase avalanche resistance EAS in the case of ensuring that chip area and chip cost are not increased, and improve product performance.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a trench-type double-gate power device and its manufacturing method. Background Technology

[0002] In power devices, trench-type double-gate power MOSFETs (Metal-O-Metal Field-Effect Transistors) possess characteristics such as high breakdown voltage, low on-resistance, fast switching speed, and high conversion efficiency. Typically, the bottom polysilicon electrode in the trench serves as the shielding electrode, shorted to the source, while the top polysilicon electrode acts as the gate. The primary research focus for trench-type double-gate power MOSFETs is continuously reducing power consumption (including conduction and switching losses) and improving the robustness of the device's dynamic performance.

[0003] The existing method for increasing avalanche withstand capability in trench-type double-gate power MOSFETs is to create regions in the source region that only have P-well regions and no N+ source regions (i.e., dummy structures) to provide a path for avalanche hole current, thereby reducing the magnitude and density of cell avalanche hole current. However, the existing method for increasing avalanche withstand capability in trench-type double-gate power MOSFETs has the following problems: 1) The existing technology's avalanche withstand capability enhancement structure in the source region only has P-well regions and no N+ source regions, i.e., dummy structures. Since the avalanche withstand capability enhancement structure in the source region does not have N+ source regions and cannot generate forward current, the existence of these structures will increase the chip area and increase the chip cost. 2) In practical applications, the source of an existing trench-type double-gate power MOS is likely to be connected to the positive terminal (the difference between the gate voltage and the source voltage is greater than the threshold voltage). This reduces the drain-source voltage difference VDS, which in turn reduces the internal electric field of the reverse-biased PWELL-N junction. This weakens the avalanche withstand capability enhancement structure's ability to extract avalanche hole current, resulting in a slower extraction rate. Therefore, the avalanche withstand capability enhancement structure's effect on improving avalanche withstand capability is not fully realized. 3) In practical applications, the source of an existing trench-type double-gate power MOS is likely to be connected to the positive terminal, causing the difference between the gate voltage and the source voltage to exceed the threshold voltage. 4) When an existing trench-type double-gate power MOS device is turned off, the extraction time of the avalanche hole current caused by the non-clamped inductive switch is relatively long, resulting in a large amount of heat generated by the avalanche hole current during device turn-off, leading to a significant temperature rise.

[0004] It should be noted that the information disclosed in the background section above is only for understanding the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problem of how to reduce on-resistance, increase avalanche resistance (EAS), and improve product performance without increasing chip area and chip cost. The invention proposes a trench-type double-gate power device and its manufacturing method.

[0006] The technical problem of this invention is solved by the following technical solution:

[0007] This invention discloses a trench-type double-gate power device, which comprises, from bottom to top, an N+ substrate, an N- epitaxial layer, a P-well, and a dielectric layer. Multiple adjacent source trenches and multiple adjacent termination trenches are respectively disposed between the N-epitaxy layer and the dielectric layer. The outer side of each source trench is a trench field oxide layer, and the inner side, from bottom to top, comprises an N-type shielding gate, an isolation oxide layer, a gate oxide layer, and a control gate. An N+ source region is disposed between the P-well and the dielectric layer, and source contact holes are disposed between the source trenches and connected to the front metal layer of the source region through the dielectric layer. The outer side of each termination trench is a termination trench field oxide layer, and polysilicon in the termination trench is disposed inside the termination trench and encapsulated by the termination trench field oxide layer and the dielectric layer. An avalanche tolerance enhancement structure, consisting of the last termination trench ring and its associated structures, is disposed before the termination trench stop ring.

[0008] In some embodiments, the avalanche resistance enhancement structure includes the dielectric layer, the avalanche resistance enhancement structure metal layer, the avalanche resistance enhancement structure body region, the avalanche resistance enhancement structure body region contact hole and the avalanche resistance enhancement structure polysilicon contact hole, the avalanche resistance enhancement structure trench field oxide layer and the avalanche resistance enhancement structure polysilicon.

[0009] Furthermore, the width of the contact hole in the avalanche tolerance enhancement structure region is greater than the width of the contact hole in the source region.

[0010] Furthermore, the polycrystalline silicon of the avalanche tolerance enhancement structure has zero potential with the front metal layer of the avalanche tolerance enhancement structure.

[0011] In some embodiments, the front metal layer of the avalanche tolerance enhancement structure is separated from the front metal layer of the source region, and its potential is set to zero volts.

[0012] In some embodiments, the regions in the source region P-well that all contain N+ source regions are not regions in the source region P-well that do not contain N+ source regions.

[0013] In some embodiments, the back side of the N+ substrate is provided with a back metal.

[0014] The present invention also discloses a method for manufacturing the above-mentioned trench-type double-gate power device, comprising the following steps:

[0015] S1. An N- epitaxial layer is formed on an N+ substrate;

[0016] S2. Perform trench photolithography and etching on the N-epitaxial layer to simultaneously form source region trenches, terminal region trenches and avalanche resistance enhancement structure trenches.

[0017] S3. A trench field oxide layer and a terminal avalanche tolerance enhancement structure trench field oxide layer are simultaneously grown on the sidewall of the trench.

[0018] S4. Deposit polysilicon and perform polysilicon phosphorus diffusion, photolithography and etching to simultaneously form source region N-type shielding gate, terminal region trench polysilicon and avalanche resistance-enhanced polysilicon structure.

[0019] S5. Deposit a high-density oxide film using chemical vapor deposition, and then etch the oxide film back to the specified depth to retain sufficient isolation oxide film thickness to form an isolation oxide layer. At this time, there is no oxide layer above the isolation oxide layer.

[0020] S6. A gate oxide layer is formed above the isolation oxide layer in the source region trench using a thermal oxidation method;

[0021] S7. Deposit N-type polysilicon and perform chemical mechanical polishing until it is flush with the chip surface. Remove the polysilicon and oxide layer on the chip surface to form the control gate.

[0022] S8. Boron implantation and diffusion are performed to form a P-well, followed by N+ photolithography, arsenic implantation and diffusion to form an N+ source region;

[0023] S9, forming a dielectric layer;

[0024] S10. Contact holes are formed by photolithography and etching, and P-type high doping implantation is performed on the contact holes to simultaneously form source region contact holes, avalanche tolerance enhancement structure region contact holes, and avalanche tolerance enhancement structure polysilicon.

[0025] S11, front metal sputtering, photolithography and etching, simultaneously forming the source region front metal layer, the terminal region front metal layer and the avalanche resistance enhancement structure front metal layer;

[0026] S12, passivation layer deposition, photolithography and etching, forming passivation layer lead windows;

[0027] S13, metal evaporates, forming the back metal.

[0028] In some embodiments, in step S5, the terminal trench polysilicon and the avalanche tolerance enhancement structure polysilicon are both integral.

[0029] In some embodiments, in step S9, the structure of the dielectric layer is a bilayer structure consisting of a phosphorus-free silicon glass layer and a phosphorus-doped silicon glass layer.

[0030] The beneficial effects of this invention compared to the prior art include:

[0031] The trench-type double-gate power device of this invention is equivalent to moving the avalanche withstand capability enhancement structure in the source region of a traditional structure to the terminal. Since the overall length of the terminal is not increased, this invention saves the chip area occupied by the avalanche withstand capability enhancement structure in a traditional structure. That is, with the same chip area, this invention can increase the forward conduction current density, reduce the on-resistance, and improve product performance. Under the same chip area conditions, this invention increases the conduction current density because there is no N+ source region in the source region, thereby reducing the on-resistance and increasing the avalanche withstand capability (EAS), thus improving product performance. Attached Figure Description

[0032] Figure 1 This is a top view of an existing trench-type double-gate power device;

[0033] Figure 2 This is a schematic diagram of the cross-sectional structure of a prior art trench-type double-gate power device along the A1A2 direction;

[0034] Figure 3 This is a top view of the trench-type double-gate power device in an embodiment of the present invention;

[0035] Figure 4 This is a schematic cross-sectional view of the trench-type double-layer gate power device along the A1A2 direction in an embodiment of the present invention;

[0036] Figure 5 This is a schematic cross-sectional view of the trench-type double-layer gate power device along the B1B2 direction in an embodiment of the present invention.

[0037] Figure 6 This is a schematic diagram of the avalanche hole current flow direction of the trench-type double-layer gate power device in an embodiment of the present invention;

[0038] Figure 7 This is a flowchart illustrating the manufacturing process of the trench-type double-gate power device of the present invention. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0040] See Figure 1In the prior art, the trench-type double-gate power device includes the following parts: front metal 13A at the device edge, gate metal 13B, and front metal layer 13C at the source region. The trench structure is an array of trench structures extending along the Y-axis and arranged along the X-axis, which is not shown in the figure.

[0041] See Figure 2 This is a cross-sectional view of a prior art trench-type double-gate power device along the A1A2 direction. The dashed box represents the avalanche tolerance enhancement structure. The prior art trench-type double-gate power device also includes the following components: N+ substrate 1, N- epitaxial layer 2, source trench field oxide layer 3, source isolation oxide layer 4 between the source N-type shielding gate 6 and the source control gate 11, source gate oxide layer 5, source N-type shielding gate 6, source P-well 7, source N+ source region 8, source dielectric layer 9, back metal 10, source control gate 11, source trench 12, front metal at the device edge 13A, front metal layer 13C, trench polysilicon in the termination region 14, and source contact hole 15, with source metal inside the contact hole. The left side of the dashed line represents the source region, and the right side of the dashed line represents the termination region.

[0042] The characteristic of existing trench-type double-gate power devices is that they have regions in the source region that only contain source region P-well 7 regions and no N+ source region 8, i.e., dummy structures, to provide a path for avalanche hole current, thereby reducing the magnitude and density of cellular avalanche hole current. The two source region trenches 12 in the dashed box in the figure are avalanche tolerance enhancement structures.

[0043] The existing methods for increasing avalanche tolerance in trench-type double-gate power MOSFETs have the following problems: 1) Existing technologies only have a P-well region in the source region of the avalanche tolerance enhancement structure, without an N+ source region, i.e., a dummy structure. Since the avalanche tolerance enhancement structure in the source region cannot generate forward current without an N+ source region, the presence of these structures increases chip area and chip cost. 2) In practical applications, the source of an existing trench-type double-gate power MOSFET is likely to be connected to the positive terminal (the difference between the gate voltage and the source voltage is greater than the threshold voltage). This reduces the drain-source voltage difference VDS, which in turn reduces the internal electric field of the reverse-biased PN junction PWELL-N-junction. This weakens the avalanche hole current extraction effect of the avalanche tolerance enhancement structure, reducing the extraction rate of avalanche hole current. Therefore, the avalanche tolerance enhancement structure's effect on improving avalanche tolerance is not fully realized. 3) Since the source of a trench-type double-gate power MOS is likely to be connected to the positive terminal in practical application circuits (the difference between the gate voltage and the source voltage is greater than the threshold voltage), the trench-type double-gate power device structure in this embodiment of the invention increases the drain-source voltage difference VDS by setting the potential of the front metal of the avalanche withstand capability enhancement structure to zero volts, thus further increasing the avalanche withstand capability EAS compared to existing structures. 4) Because the avalanche hole current extraction time caused by the non-clamped inductive switch is relatively long when the existing trench-type double-gate power MOS device is turned off, the heat generated by the avalanche hole current when the device is turned off is large, which will cause a large temperature rise.

[0044] See Figure 3 The trench-type double-gate power device of this embodiment includes the following components: a front-side metal layer 13A at the device edge, a gate metal layer 13B, a front-side metal layer 13C at the source region, and a front-side metal layer 13D for avalanche tolerance enhancement structures. The front-side metal layer 13D for avalanche tolerance enhancement structures is separated from the front-side metal layer 13C at the source region and is not connected as a whole. The trench structure is an array of trench structures extending along the Y-axis and arranged along the X-axis, which is not shown in the figure.

[0045] See Figure 4 The trench-type double-gate power device of the embodiment further includes the following parts: N+ substrate 1, N- epitaxial layer 2, source trench field oxide layer 3, source isolation oxide layer 4 between source N-type shielding gate 6 and source control gate 11, source gate oxide layer 5, source N-type shielding gate 6, source P-well 7, source N+ source region 8, source dielectric layer 9, back metal 10, source control gate 11, source trench 12, termination trench 12A, device edge front metal 13A, source front metal layer 13C, termination trench polysilicon 14, source contact hole 15, and source contact hole 15 contains source metal. The area to the left of the dashed line represents the source region, and the area to the right of the dashed line represents the termination region.

[0046] The difference between the shielded gate power MOSFET in this embodiment of the invention and the cross-sectional structure diagram of the shielded gate power MOSFET in the prior art along the A1A2 direction is that the shielded gate power MOSFET in this embodiment of the invention does not have an avalanche tolerance enhancement structure in the source region, that is, there is no region without N+ source region in the P-well of the source region.

[0047] See Figure 5 The cross-sectional structure of the trench-type double-gate power device in this embodiment along the B1B2 direction further includes the following parts: an avalanche tolerance enhancement structure front metal layer 13D, a terminal region trench polysilicon 14, a source region contact hole 15, and the source region contact hole 15 contains source metal. The dashed box in the figure represents the avalanche tolerance enhancement structure of the trench-type double-gate power device in this embodiment, which consists of the last trench ring at the end and its associated structures, located before the trench stop ring. The avalanche tolerance enhancement structure includes the following parts: an avalanche tolerance enhancement structure trench field oxide layer 3A, an avalanche tolerance enhancement structure dielectric layer 9A, an avalanche tolerance enhancement structure trench 12B, an avalanche tolerance enhancement structure front metal layer 13D, an avalanche tolerance enhancement structure polysilicon 14A, an avalanche tolerance enhancement structure body region 7A, an avalanche tolerance enhancement structure body region contact hole 15A, and an avalanche tolerance enhancement structure polysilicon contact hole 15B. The avalanche resistance enhancement structure is characterized by the following: the width of the contact hole 15A in the avalanche resistance enhancement structure body region is greater than the width of the contact hole 15 in the source region. The left side of the dashed line represents the source region, and the right side of the dashed line represents the terminal region. The terminal region trench field oxide layer 3A is disposed outside the terminal region trench 12A, and the avalanche resistance enhancement structure polysilicon 14A is disposed inside the terminal region trench 12A, and is enclosed by the terminal region trench field oxide layer 3A and the avalanche resistance enhancement structure dielectric layer 9A. Both the avalanche resistance enhancement structure body region contact hole 15A and the avalanche resistance enhancement structure polysilicon contact hole 15B are connected to the avalanche resistance enhancement structure front metal layer 13D through the avalanche resistance enhancement structure dielectric layer 9A, wherein the avalanche resistance enhancement structure polysilicon 14A is connected to the avalanche resistance enhancement structure front metal layer 13D.

[0048] The hole current flow direction of the trench-type double-gate power device in the embodiment is as follows: Figure 6 As shown, A is the total avalanche hole current of the device, A1 is the avalanche hole current flowing into the source region, and A2 is the avalanche hole current flowing into the terminal avalanche tolerance enhancement structure.

[0049] The principle and beneficial effects of the trench-type double-layer gate power device avalanche tolerance enhancement structure according to embodiments of the present invention are as follows:

[0050] When an avalanche occurs after the device is turned off, the avalanche hole current A2 flowing into the P-well of the terminal avalanche tolerance enhancement structure enters the structure. Because the contact hole width in the body region of the avalanche tolerance enhancement structure is larger than the contact hole width in the source region, and because there is no obstruction from the N+ source region, the avalanche hole current easily passes through the metal in the contact hole and enters the front metal of the avalanche tolerance enhancement structure. This increases the total avalanche hole current entering the terminal avalanche tolerance enhancement structure and weakens the avalanche hole current entering the source region. Therefore, the avalanche tolerance enhancement structure of this embodiment increases the avalanche tolerance EAS compared to existing avalanche tolerance enhancement structures.

[0051] Meanwhile, in the avalanche tolerance enhancement structure of this invention, the polysilicon has a zero potential. In contrast, in the prior art avalanche tolerance enhancement structure, the N-type shielding gate of the source region is connected to the front metal layer of the source region, which may have a positive potential. The attraction of electrons in the polysilicon of the avalanche tolerance enhancement structure of this invention to the avalanche hole current is stronger than that of electrons in the N-type shielding gate of the source region, allowing more avalanche hole current to be discharged through the avalanche tolerance enhancement structure of this invention. Therefore, the avalanche tolerance enhancement structure of this invention further increases the avalanche tolerance (EAS) compared to the avalanche tolerance enhancement structure of the prior art.

[0052] Since the source of a trench-type double-gate power device is likely to be connected to the positive terminal in practical application circuits, meaning the difference between the gate voltage and the source voltage is greater than the threshold voltage, the trench-type double-gate power device structure in this embodiment of the invention increases the drain-source voltage difference VDS by setting the potential of the front metal layer of the avalanche withstand capability enhancement structure to zero volts. This avoids the problems in existing avalanche withstand capability enhancement structures, such as a decrease in the internal electric field of the reverse-biased PN junction PWELL-N-junction, a weaker extraction effect of the avalanche hole current, a slower extraction speed, and insufficient improvement in avalanche withstand capability caused by the reduction of the drain-source voltage difference VDS. Therefore, this avalanche withstand capability enhancement structure further increases the avalanche withstand capability EAS compared to existing structures. Because the extraction time of the avalanche hole current caused by the non-clamped inductive switch is short when the trench-type double-gate power MOS device in this embodiment of the invention is short, the heat generated by the avalanche hole current when the device is turned off is smaller, reducing the temperature rise.

[0053] Under the same chip area conditions, the trench-type double-gate power device of the present invention increases the current density of the conduction current, reduces the conduction resistance, and improves the performance of the product because there is no region without N+ source region in the P-well of the source region.

[0054] The avalanche tolerance enhancement structure in this embodiment of the invention serves the same purpose as the traditional avalanche tolerance enhancement structure: reducing the current density of avalanche hole current flowing through the effective cell structure. Essentially, it moves the avalanche tolerance enhancement structure from the source region to the terminal in the traditional structure. Since the overall length of the terminal is not increased, the trench-type double-gate power device in this embodiment of the invention saves the chip area occupied by the traditional avalanche tolerance enhancement structure. That is, with the same chip area, it increases the forward conduction current density, reduces the on-resistance, and improves product performance.

[0055] Furthermore, the flowchart of the manufacturing method of the trench-type double-gate power device in the embodiments of the present invention is as follows: Figure 7 As shown, the specific steps are as follows:

[0056] S1. An N- epitaxial layer 2 is formed on an N+ substrate 1;

[0057] S2. Perform trench photolithography and etching on the N-epitaxial layer 2 to simultaneously form source region trench 12, terminal region trench 12A and avalanche tolerance enhancement structure trench 12B.

[0058] S3. A trench field oxide layer 3 and a terminal avalanche tolerance enhancement structure trench field oxide layer 3A are simultaneously grown on the sidewall of the trench.

[0059] S4. Polycrystalline silicon is deposited and polycrystalline phosphorus diffusion, photolithography and etching are performed to simultaneously form the source region N-type shielding gate 6, the terminal region trench polycrystalline silicon 14 and the avalanche tolerance enhancement structure polycrystalline silicon 14A; the terminal region trench polycrystalline silicon 14 and the avalanche tolerance enhancement structure polycrystalline silicon 14A are both integral units.

[0060] S5. A high-density oxide film is deposited using chemical vapor deposition, and then the oxide film is etched back to a specified depth to retain sufficient isolation oxide film thickness to form isolation oxide layer 4; where the isolation oxide film is also called intermediate oxide film, and there is no oxide layer above the isolation oxide layer at this time;

[0061] S6. A gate oxide layer 5 is formed above the isolation oxide layer 4 in the source region trench 12 by thermal oxidation.

[0062] S7. Deposit N-type polysilicon and perform chemical mechanical polishing until it is flush with the chip surface. Remove the polysilicon and oxide layer on the chip surface to form the control gate 11.

[0063] S8. Boron implantation and diffusion are performed to form the source region P-well 7, followed by N+ photolithography, arsenic implantation and diffusion to form the N+ source region 8.

[0064] S9, forming a dielectric layer (source region dielectric layer 9, avalanche tolerance enhanced structure dielectric layer 9A); the material is a USG (undoped silicon glass) layer and a PSG (doped silicon glass) layer;

[0065] S10. Contact holes are formed by photolithography and etching, and P-type high doping implantation is performed on the contact holes to simultaneously form source region contact holes 15, avalanche resistance enhanced structure region contact holes 15A and avalanche resistance enhanced structure polysilicon contact holes 15B.

[0066] S11. Front metal sputtering, photolithography and etching are performed to simultaneously form the source region front metal layer 13C, the terminal region front metal layer 13A and the avalanche tolerance enhancement structure front metal layer 13D.

[0067] S12, passivation layer deposition, photolithography and etching, forming passivation layer lead windows;

[0068] S13, metal evaporates, forming back metal 10.

[0069] The above description provides a further detailed explanation of the present invention in conjunction with specific / preferred embodiments, and it should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various substitutions or modifications can be made to these described embodiments without departing from the concept of the present invention, and all such substitutions or modifications should be considered within the scope of protection of the present invention. In the description of this specification, the reference to terms such as "an embodiment," "some embodiments," "preferred embodiment," "example," "specific example," or "some examples," etc., indicates that the specific features, structures, materials, or characteristics described in connection with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the scope of protection of the patent application.

Claims

1. A trench-type double-gate power device, characterized in that: The trench-type double-layer gate power device comprises, from bottom to top, an N+ substrate (1), an N- epitaxial layer (2), a source region P-well (7), and a dielectric layer; the dielectric layer is composed of a source region dielectric layer (9) and an avalanche tolerance enhancement structure dielectric layer (9A), and multiple adjacent source region trenches (12) and multiple adjacent terminal region trenches (12A) are respectively disposed between the N- epitaxial layer (2) and the dielectric layer; the outer side of the source region trench (12) is a trench field oxide layer (3), and the inner side is composed of an N-type shielding gate (6), an isolation oxide layer (4), a gate oxide layer (5), and a control gate (11) from bottom to top; the N+ source region (8) is disposed between the source region P-well (7) and the source region dielectric layer (9A). Between 9), source region contact holes (15) are disposed between the source region trenches (12) and penetrate the source region dielectric layer (9). The source region front metal layer (13C) is connected to the N+ source region (8) and the source region P-well (7) through the source region contact holes (15). The outer side of the terminal region trench (12A) is the terminal region trench field oxide layer (3A). The terminal region trench polysilicon (14) is disposed inside the terminal region trench (12A) and is wrapped by the terminal region trench field oxide layer (3A) and the avalanche tolerance enhancement structure dielectric layer (9A). An avalanche tolerance enhancement structure composed of the last terminal region trench ring and its associated structure is disposed before the terminal region trench stop ring. The avalanche resistance enhancement structure includes an avalanche resistance enhancement structure dielectric layer (9A), an avalanche resistance enhancement structure front metal layer (13D), an avalanche resistance enhancement structure body region (7A), an avalanche resistance enhancement structure body region contact hole (15A), an avalanche resistance enhancement structure polycrystalline silicon contact hole (15B), an avalanche resistance enhancement structure trench field oxide layer (3A), and an avalanche resistance enhancement structure polycrystalline silicon (14A). The width of the contact hole (15A) in the avalanche tolerance enhancement structure region is greater than the width of the contact hole (15) in the source region; The avalanche tolerance enhancement structure polycrystalline silicon (14A) has zero potential with the front metal layer (13D) of the avalanche tolerance enhancement structure; The avalanche tolerance enhancement structure has a front metal layer (13D) that is separated from the source region front metal layer (13C) and its potential is set to zero volts. In each of the source regions P-wells (7), there is a region of N+ source region (8).

2. The trench-type double-gate power device as described in claim 1, characterized in that: The N+ substrate (1) has a back metal (10) on its back side.

3. A method for manufacturing a trench-type double-gate power device as described in any one of claims 1-2, characterized in that, Includes the following steps: S1. An N- epitaxial layer (2) is formed on an N+ substrate (1); S2. Trench photolithography and etching are performed on the N-epitaxial layer (2) to simultaneously form source region trench (12), terminal region trench (12A) and avalanche tolerance enhancement structure trench (12B); S3. A trench field oxide layer (3) and a terminal avalanche tolerance enhancement structure trench field oxide layer (3A) are simultaneously grown on the sidewall of the trench. S4. Polysilicon is deposited and polysilicon is diffused, photolithography and etching are performed to simultaneously form the source region N-type shielding gate (6), the terminal region trench polysilicon (14) and the avalanche resistance-enhanced structure polysilicon (14A). S5. A high-density oxide film is deposited by chemical vapor deposition, and then the oxide film is etched back to the specified depth to retain sufficient isolation oxide film thickness to form an isolation oxide layer (4). At this time, there is no oxide layer above the isolation oxide layer. S6. A gate oxide layer (5) is formed above the isolation oxide layer (4) in the source trench (12) by thermal oxidation. S7. Deposit N-type polysilicon and perform chemical mechanical polishing until it is flush with the chip surface. Remove the polysilicon and oxide layer on the chip surface to form a control gate (11). S8. Boron implantation and diffusion are performed to form a source region P-well (7), followed by N+ photolithography, arsenic implantation and diffusion to form an N+ source region (8); S9, forming a dielectric layer; S10. Contact holes are formed by photolithography and etching, and P-type high doping implantation is performed on the contact holes to simultaneously form source region contact holes (15), avalanche resistance enhanced structure region contact holes (15A) and avalanche resistance enhanced structure polysilicon contact holes (15B). S11, front-side metal sputtering, photolithography and etching, simultaneously forming the source region front-side metal layer (13C), the terminal region front-side metal layer (13A) and the avalanche tolerance enhancement structure front-side metal layer (13D); S12, passivation layer deposition, photolithography and etching, forming passivation layer lead windows; S13, the metal evaporates, forming the back metal (10).

4. The method for manufacturing a trench-type double-gate power device as described in claim 3, characterized in that, In step S5, the terminal trench polysilicon (14) and the avalanche tolerance enhanced structure polysilicon (14A) are both integral units.

5. The method for manufacturing a trench-type double-gate power device as described in claim 3, characterized in that, In step S9, the structure of the dielectric layer is a double-layer structure consisting of a phosphorus-free silicon glass layer and a phosphorus-doped silicon glass layer.

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