Frequency doubling device and multiple frequency multiplication apparatus

Abstract

The application relates to a frequency doubling device and a multiple frequency doubling apparatus. The frequency doubling device comprises a substrate, a first high-voltage switch module, a second high-voltage switch module and a MOM capacitor. The application replaces the operational amplifier in the traditional frequency doubling circuit with the first high-voltage switch module, the second high-voltage switch module and the MOM capacitor, can generate a frequency doubling signal based on a reference pulse signal and an input voltage, and is suitable for a high-voltage environment. Meanwhile, due to the large chip area of the LDMOS tube, there is sufficient space above the first high-voltage switch module and the second high-voltage switch module to configure a suitable MOM capacitor.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a frequency doubling device and a frequency multiplication device. Background Technology

[0002] Currently, traditional frequency multiplier circuits typically consist of operational amplifiers, mainly because the operating frequency of the operational amplifiers is high enough to generate multi-frequency signals based on a reference signal. However, the current problem is that existing frequency multiplier circuits can generally only be applied to low-voltage signals. The operational amplifiers and other components in existing frequency multiplier circuits cannot withstand excessively high voltages, and the cost is relatively high. Summary of the Invention

[0003] The purpose of this application is to provide a frequency doubling device and a frequency multiplication device, which aims to solve the problem that traditional frequency multiplication circuits cannot be applied to high-voltage circuits.

[0004] A first aspect of this application provides a frequency doubling device, comprising: a substrate having a signal input terminal and a high-voltage power supply terminal, the signal input terminal being used to provide a periodically varying reference pulse signal, and the high-voltage power supply terminal being used to provide an input voltage; a first high-voltage switching module disposed on the upper surface of the substrate, the first high-voltage switching module being connected to the signal input terminal and the high-voltage power supply terminal respectively, the first high-voltage switching module including a plurality of LDMOS transistors, the first high-voltage switching module being configured to generate and output a first pulse signal based on the reference pulse signal provided by the signal input terminal by controlling the switching of the LDMOS transistors between the high-voltage power supply terminal and ground; and a MOM capacitor disposed above the first high-voltage switching module, the MOM capacitor including a first interdigitated capacitor layer, the input terminal of the first interdigitated capacitor layer being connected to the signal input terminal, the first interdigitated capacitor layer being configured to receive the input terminal of the first interdigitated capacitor layer. The signal is delayed and then output from the output terminal of the first interdigital capacitor layer; a second high-voltage switching module is disposed on the upper surface of the substrate, and the second high-voltage switching module is connected to the output terminal of the first interdigital capacitor layer and the high-voltage power supply terminal respectively. The second high-voltage switching module also includes a plurality of LDMOS transistors. The second high-voltage switching module is configured to generate and output a second pulse signal based on the delayed reference pulse signal output from the first interdigital capacitor layer by controlling the switching of the LDMOS transistors between the high-voltage power supply terminal and the ground terminal; the duty cycle of the first pulse signal and the second pulse signal are both 1 / 2 of the duty cycle of the reference pulse signal, and the frequencies of the first pulse signal and the second pulse signal are the same as the frequency of the reference pulse signal. The delay time of the first interdigital capacitor layer is 1 / 2 of the period of the reference pulse signal. The first pulse signal and the second pulse signal are used to synthesize a frequency multiplication signal.

[0005] In one embodiment, the first high-voltage switching module includes a first LDMOS transistor and a second LDMOS transistor, and the MOM capacitor further includes a second interdigital capacitor layer; the first conducting terminal of the first LDMOS transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the first LDMOS transistor is connected to the first conducting terminal of the second LDMOS transistor, the second conducting terminal of the second LDMOS transistor is the output terminal of the first high-voltage switching module, the control terminal of the first LDMOS transistor is connected to the signal input terminal, the input terminal of the second interdigital capacitor layer is connected to the control terminal of the first LDMOS transistor, the output terminal of the second interdigital capacitor layer is connected to the control terminal of the second LDMOS transistor, the second interdigital capacitor layer is configured to delay the signal received at the input terminal of the second interdigital capacitor layer and then output it from the output terminal of the second interdigital capacitor layer, the duty cycle of the reference pulse signal is Y, and the delay duration of the second interdigital capacitor layer is Y / 2 of the period of the reference pulse signal.

[0006] In one embodiment, the second high-voltage switching module includes a third LDMOS transistor and a fourth LDMOS transistor, and the MOM capacitor further includes a third interdigital capacitor layer; the first conducting terminal of the third LDMOS transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the third LDMOS transistor is connected to the first conducting terminal of the fourth LDMOS transistor, the second conducting terminal of the fourth LDMOS transistor is the output terminal of the second high-voltage switching module, the control terminal of the third LDMOS transistor is connected to the output terminal of the first interdigital capacitor layer, the input terminal of the third interdigital capacitor layer is connected to the control terminal of the third LDMOS transistor, the output terminal of the third interdigital capacitor layer is connected to the control terminal of the fourth LDMOS transistor, and the third interdigital capacitor layer is configured to delay the signal received at the input terminal of the third interdigital capacitor layer and then output it from the output terminal of the third interdigital capacitor layer, the delay duration of the third interdigital capacitor layer is equal to the delay duration of the second interdigital capacitor layer.

[0007] In one embodiment, the first LDMOS transistor, the second LDMOS transistor, the third LDMOS transistor, and the fourth LDMOS transistor are all N-type LDMOS transistors.

[0008] In one embodiment, a pull-down resistor is further included, wherein the first end of the pull-down resistor is connected to the output terminal of the first high-voltage switch module and the output terminal of the second high-voltage switch module, and the second end of the pull-down resistor is connected to ground.

[0009] In one embodiment, the second interdigital capacitor layer, the first interdigital capacitor layer, and the third interdigital capacitor layer are stacked sequentially from top to bottom.

[0010] In one embodiment, the first interdigitated capacitor layer includes multiple stacked sub-capacitor layers, and adjacent sub-capacitor layers are connected by metal vias.

[0011] A second aspect of this application provides a frequency multiplication device, including a plurality of frequency doubling devices as described above connected in series, wherein the frequency multiplication signal output by the preceding frequency multiplication device is used as the reference pulse signal of the following frequency multiplication device.

[0012] In one embodiment, the multi-frequency doubling device includes two frequency doubling devices connected in series.

[0013] In one embodiment, the multi-frequency doubling device includes three frequency doubling devices connected in series.

[0014] The advantages of this application embodiment compared to the prior art are as follows: by replacing the operational amplifier in the traditional frequency multiplier circuit with a first high-voltage switching module, a second high-voltage switching module, and a MOM capacitor, a frequency multiplication signal can be generated based on the reference pulse signal and the input voltage, making it adaptable to high-voltage environments. Simultaneously, due to the large chip area of ​​the LDMOS transistor, there is sufficient space above the first and second high-voltage switching modules to configure a suitable MOM capacitor. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a frequency doubling device provided in an embodiment of this application;

[0016] Figure 2 An equivalent circuit diagram of a frequency doubling device provided in an embodiment of this application;

[0017] Figure 3 This is another schematic diagram of the structure of a frequency doubling device provided in an embodiment of this application;

[0018] Figure 4 This is a schematic diagram of the principle of a MOM capacitor provided in one embodiment of this application;

[0019] Figure 5 A signal waveform diagram of a frequency doubling device provided in an embodiment of this application;

[0020] Figure 6 This is a schematic diagram of the structure of an LDMOS transistor provided in an embodiment of this application;

[0021] Figure 7 This is a schematic diagram of the structure of a MOM capacitor provided in an embodiment of this application;

[0022] Figure 8 This is a schematic diagram of a multi-frequency doubling device provided in an embodiment of this application;

[0023] Figure 9 Another schematic diagram of the multi-frequency doubling device provided in an embodiment of this application;

[0024] Figure 10 This is a schematic diagram of a multi-frequency doubling device provided in another embodiment of this application.

[0025] The above figures illustrate the following: 10, frequency doubling device; 100, substrate; 200, first high-voltage switching module; 210, first LDMOS transistor; 220, second LDMOS transistor; 300, MOM capacitor; 310, first interdigitated capacitor layer; 311, sub-capacitor layer; 312, metal via; 320, second interdigitated capacitor layer; 330, third interdigitated capacitor layer; 400, second high-voltage switching module; 410, third LDMOS transistor; 420, fourth LDMOS transistor; 510, N-type injection region; 520, P-type injection region; 530, polysilicon; 540, wire. Detailed Implementation

[0026] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0027] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0028] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0030] Figure 1A schematic diagram of a frequency doubling device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0031] like Figure 1 As shown, a frequency doubling device 10 includes: a substrate 100, a first high-voltage switching module 200, an MOM (Metal-Oxide-Metal) capacitor 300, and a second high-voltage switching module 400.

[0032] The substrate 100 is provided with a signal input terminal and a high-voltage power supply terminal. The signal input terminal is used to provide a periodically varying reference pulse signal VIN, and the high-voltage power supply terminal is used to provide an input voltage VDD. Specifically, the signal input terminal and the high-voltage power supply terminal can be connected to an external circuit to obtain the reference pulse signal VIN and the input voltage VDD from the external circuit, and provide the reference pulse signal VIN and the input voltage VDD to the first high-voltage switching module 200, the MOM capacitor 300, and the second high-voltage switching module 400. The reference pulse signal VIN varies periodically, and the input voltage VDD can reach 5V to 700V, specifically 600V.

[0033] The first high-voltage switch module 200 is disposed on the upper surface of the substrate 100. The first high-voltage switch module 200 is connected to the signal input terminal and the high-voltage power supply terminal respectively. The first high-voltage switch module 200 includes a plurality of LDMOS (laterally-diffused metal-oxide semiconductor) transistors. The first high-voltage switch module 200 is configured to generate and output a first pulse signal V1 based on the reference pulse signal VIN provided by the signal input terminal by controlling the switching of the LDMOS transistors between the high-voltage power supply terminal and the ground terminal.

[0034] MOM capacitor 300 is disposed above the first high voltage switch module 200. MOM capacitor 300 includes a first interdigitated capacitor layer 310. The input terminal of the first interdigitated capacitor layer 310 is connected to the signal input terminal. The first interdigitated capacitor layer 310 is configured to delay the signal received at the input terminal of the first interdigitated capacitor layer 310 and then output it from the output terminal of the first interdigitated capacitor layer 310.

[0035] The second high-voltage switching module 400 is disposed on the upper surface of the substrate 100. The second high-voltage switching module 400 is connected to the output terminal of the first interdigital capacitor layer 310 and the high-voltage power supply terminal, respectively. The second high-voltage switching module 400 also includes several LDMOS transistors. The second high-voltage switching module 400 is configured to generate and output a second pulse signal V2 based on the delayed reference pulse signal VIN output from the first interdigital capacitor layer 310 by controlling the switching of the LDMOS transistors between the high-voltage power supply terminal and the ground terminal. The duty cycles of both the first pulse signal V1 and the second pulse signal V2 are half the duty cycle of the reference pulse signal VIN, and the frequencies of both the first pulse signal V1 and the second pulse signal V2 are the same as the frequency of the reference pulse signal VIN. The delay duration of the first interdigital capacitor layer 310 is half the period of the reference pulse signal VIN. The first pulse signal V1 and the second pulse signal V2 are used to synthesize a frequency-multiplied signal VOUT. Let the period of the reference pulse signal VIN be T, and the delay duration of the first interdigital capacitor layer 310 be T1, then T1 = T / 2.

[0036] The delay caused by the MOM capacitor 300 creates a phase difference between the reference pulse signal VIN received by the first high-voltage switch module 200 and the second high-voltage switch module 400, which in turn creates a phase difference between the first pulse signal V1 and the second pulse signal V2. This allows the synthesis of a corresponding frequency-doubled signal VOUT, whose frequency is twice that of the reference pulse signal VIN.

[0037] It should be noted that the frequency doubling device 10 in this embodiment is a semiconductor device. Both the first high-voltage switching module 200 and the second high-voltage switching module 400 are composed of LDMOS transistors. Since the chip area of ​​LDMOS transistors is relatively large, there is sufficient space above the first high-voltage switching module 200 and the second high-voltage switching module 400 to configure a suitable MOM capacitor 300.

[0038] This embodiment replaces the operational amplifier in a traditional frequency multiplier circuit with a first high-voltage switching module 200, a second high-voltage switching module 400, and a MOM capacitor 300. It can generate a frequency multiplier signal VOUT based on the reference pulse signal VIN and the input voltage VDD. Due to the use of LDMOS transistors, it can adapt to high-voltage environments. Furthermore, since both the first high-voltage switching module 200 and the second high-voltage switching module 400 only need to output one pulse within one cycle of the reference pulse signal VIN, the switching frequency of the LDMOS transistors in both modules is low. This avoids the problem of being unable to directly and continuously output high-frequency signals due to the low switching speed of the first high-voltage switching module 200 and the second high-voltage switching module 400.

[0039] The equivalent circuit diagram of the frequency doubling device 10 is as follows: Figure 2As shown, in this embodiment, the first high-voltage switching module 200 includes a first LDMOS transistor 210 and a second LDMOS transistor 220. Another structural schematic diagram of the frequency doubling device 10 is shown below. Figure 3 As shown in the schematic diagram of MOM capacitor 300 Figure 4 As shown, the MOM capacitor 300 also includes a second interdigitated capacitor layer 320. The first conducting terminal of the first LDMOS transistor 210 is connected to the high-voltage power supply terminal, and the second conducting terminal of the first LDMOS transistor 210 is connected to the first conducting terminal of the second LDMOS transistor 220. The second conducting terminal of the second LDMOS transistor 220 is the output terminal of the first high-voltage switching module 200. The control terminal of the first LDMOS transistor 210 is connected to the signal input terminal. The input terminal of the second interdigitated capacitor layer 320 is connected to the control terminal of the first LDMOS transistor 210, and the output terminal of the second interdigitated capacitor layer 320 is connected to the control terminal of the second LDMOS transistor 220. The second interdigitated capacitor layer 320 is configured to delay the signal received at the input terminal of the second interdigitated capacitor layer 320 and then output it from the output terminal of the second interdigitated capacitor layer 320. When the duty cycle of the reference pulse signal VIN is Y, the delay duration of the second interdigitated capacitor layer 320 is Y / 2 of the period of the reference pulse signal VIN. Let the delay time of the second interdigital capacitor layer 320 be T2, then T2 = YT / 2. In one example, Y is 0.5, then T2 = T / 4.

[0040] Specifically, the frequency doubling device 10 also includes a pull-down resistor R1, the first end of which is connected to the output terminal of the first high-voltage switching module 200, and the second end of which is connected to ground.

[0041] In this embodiment, the waveforms of the reference pulse signal VIN, the first pulse signal V1, the second pulse signal V2, and the frequency multiplication signal VOUT are as follows: Figure 5 As shown.

[0042] It should be noted that the input voltage VDD provided by the high-voltage power supply can only increase the output voltage of the first high-voltage switching module 200 when both the first LDMOS transistor 210 and the second LDMOS transistor 220 are turned on simultaneously. When either the first LDMOS transistor 210 or the second LDMOS transistor 220 is turned off, the pull-down resistor R1 reduces the output voltage of the first high-voltage switching module 200, thereby generating a corresponding first pulse signal V1 based on the reference pulse signal VIN. The pulse width of the first pulse signal V1 corresponds to the delay duration of the second interdigital capacitor layer 320. If the delay duration of the second interdigital capacitor layer 320 is zero, then the duty cycle and pulse width of the first pulse signal V1 are equal to those of the reference pulse signal VIN. When the delay duration of the second interdigital capacitor layer 320 increases from zero, the duty cycle and pulse width of the first pulse signal V1 decrease accordingly until the delay duration of the second interdigital capacitor layer 320 reaches Y / 2 of the period of the reference pulse signal VIN. At this time, the duty cycle and pulse width of the first pulse signal V1 are also 1 / 2 of the reference pulse signal VIN, corresponding to the frequency multiplication signal VOUT of the target.

[0043] In this embodiment, the second high-voltage switching module 400 includes a third LDMOS transistor 410 and a fourth LDMOS transistor 420, and the MOM capacitor 300 also includes a third interdigital capacitor layer 330. The first conducting terminal of the third LDMOS transistor 410 is connected to the high-voltage power supply terminal, the second conducting terminal of the third LDMOS transistor 410 is connected to the first conducting terminal of the fourth LDMOS transistor 420, the second conducting terminal of the fourth LDMOS transistor 420 is the output terminal of the second high-voltage switching module 400, the control terminal of the third LDMOS transistor 410 is connected to the output terminal of the first interdigital capacitor layer 310, the input terminal of the third interdigital capacitor layer 330 is connected to the control terminal of the third LDMOS transistor 410, and the output terminal of the third interdigital capacitor layer 330 is connected to the control terminal of the fourth LDMOS transistor 420. The third interdigital capacitor layer 330 is configured to delay the signal received at the input terminal of the third interdigital capacitor layer 330 and then output it from the output terminal of the third interdigital capacitor layer 330. The delay time of the third interdigital capacitor layer 330 is equal to the delay time of the second interdigital capacitor layer 320.

[0044] The output terminal of the second high-voltage switch module 400 is also connected to the first terminal of the pull-down resistor R1. That is, the first terminal of the pull-down resistor R1 is connected to the output terminals of both the first high-voltage switch module 200 and the second high-voltage switch module 400, to synthesize the corresponding frequency-multiplied signal VOUT based on the first pulse signal V1 and the second pulse signal V2. The circuit structure of the second high-voltage switch module 400 is basically the same as that of the first high-voltage switch module 200. The difference is that the signal received by the second high-voltage switch module 400 is a reference pulse signal VIN delayed by the first interdigital capacitor layer 310. This results in a phase difference between the second pulse signal V2 and the first pulse signal V1 output by the second high-voltage switch module 400, which corresponds precisely to the phase difference between adjacent pulses of the target frequency-multiplied signal VOUT.

[0045] Traditional frequency multiplier circuits using operational amplifiers require multiple cycles of the reference pulse signal VIN before outputting the target multiplied signal VOUT. This embodiment, however, can output the corresponding multiplied signal VOUT immediately upon receiving the reference pulse signal VIN. Traditional frequency multiplier circuits require modifications to their overall architecture when parameters such as the period of the reference pulse signal VIN change. This embodiment, however, only needs to change the parameters of each capacitor layer to adapt to these changes.

[0046] In this embodiment, the first LDMOS transistor 210, the second LDMOS transistor 220, the third LDMOS transistor 410, and the fourth LDMOS transistor 420 are all N-type LDMOS transistors. The drain of the N-type LDMOS transistor corresponds to the first on-terminal, the source corresponds to the second on-terminal, and the gate corresponds to the control terminal. Figure 6 As shown, in one example, the N-type LDMOS transistor includes an N-type implantation region 510 as the drain, a P-type implantation region 520 as the source, and polysilicon 530 as the gate. Both the N-type implantation region 510 and the P-type implantation region 520 can be obtained by implanting corresponding ions. The N-type implantation regions 510 of the first LDMOS transistor 210 and the third LDMOS transistor 410 are directly connected, and the P-type implantation regions 520 of the second LDMOS transistor 220 and the fourth LDMOS transistor 420 are directly connected. The P-type implantation region 520 of the first LDMOS transistor 210 is connected to the N-type implantation region 510 of the second LDMOS transistor 220 via a wire 540, and the P-type implantation region 520 of the third LDMOS transistor 410 is connected to the N-type implantation region 510 of the fourth LDMOS transistor 420 via another wire 540. The LDMOS has a large package area, providing sufficient space to configure the MOM capacitor 300. In another embodiment, the N-type LDMOS transistor includes a high-k metal gate (HKMG) as the gate.

[0047] like Figure 7 As shown, in this embodiment, the second interdigital capacitor layer 320, the first interdigital capacitor layer 310, and the third interdigital capacitor layer 330 are stacked sequentially from top to bottom.

[0048] In this embodiment, the capacitance value corresponding to the first interdigital capacitor layer 310 is greater than the capacitance values ​​corresponding to the second interdigital capacitor layer 320 and the third interdigital capacitor layer 330. That is, the delay duration corresponding to the first interdigital capacitor layer 310 is greater than the delay duration corresponding to the second interdigital capacitor layer 320 and the third interdigital capacitor layer 330.

[0049] In this embodiment, the first interdigital capacitor layer 310 includes multiple stacked sub-capacitor layers 311, and adjacent sub-capacitor layers 311 are connected by metal vias 312. The number and size of the sub-capacitor layers 311 correspond to the specific capacitance value of the first interdigital capacitor layer 310 and can be configured according to actual needs. In one example, there are two sub-capacitor layers 311.

[0050] Figure 8 A schematic diagram of a multi-frequency doubling device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0051] A frequency multiplication device includes a plurality of frequency doublers 10 connected in series as described in any of the above embodiments. Between two adjacent frequency doublers 10, the frequency multiplication signal VOUT output by the preceding frequency doubler 10 is used as the reference pulse signal VIN of the following frequency doubler 10. The specific parameters of the MOM capacitor 300 of the following frequency doubler 10 correspond to the frequency multiplication signal VOUT output by the preceding frequency doubler 10.

[0052] In this embodiment, as Figure 9 As shown, the multi-frequency harmonic device includes two second-frequency harmonic devices 10 connected in series, and the multi-frequency harmonic device is a fourth-frequency harmonic device.

[0053] In another embodiment, such as Figure 10 As shown, the multi-frequency harmonic device includes three second-frequency harmonic devices 10 connected in series, and the multi-frequency harmonic device is an eighth-frequency harmonic device.

[0054] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0055] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0056] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A frequency-doubler device, characterized in that, include: The substrate is provided with a signal input terminal and a high-voltage power supply terminal. The signal input terminal is used to provide a periodically varying reference pulse signal, and the high-voltage power supply terminal is used to provide an input voltage. A first high-voltage switching module is disposed on the upper surface of the substrate. The first high-voltage switching module is connected to the signal input terminal and the high-voltage power supply terminal respectively. The first high-voltage switching module includes a plurality of LDMOS transistors. The first high-voltage switching module is configured to generate and output a first pulse signal based on the reference pulse signal provided by the signal input terminal by controlling the switching of the LDMOS transistors between the high-voltage power supply terminal and the ground terminal. A MOM capacitor is disposed above the first high-voltage switch module. The MOM capacitor includes a first interdigitated capacitor layer. The input terminal of the first interdigitated capacitor layer is connected to the signal input terminal. The first interdigitated capacitor layer is configured to delay the signal received at the input terminal of the first interdigitated capacitor layer and then output it from the output terminal of the first interdigitated capacitor layer. A second high-voltage switching module is disposed on the upper surface of the substrate. The second high-voltage switching module is connected to the output terminal of the first interdigital capacitor layer and the high-voltage power supply terminal respectively. The second high-voltage switching module also includes a plurality of LDMOS transistors. The second high-voltage switching module is configured to generate and output a second pulse signal based on the delayed reference pulse signal output by the first interdigital capacitor layer by controlling the switching of the LDMOS transistor between the high-voltage power supply terminal and the ground terminal. The duty cycles of the first pulse signal and the second pulse signal are both half the duty cycle of the reference pulse signal, and the frequencies of the first pulse signal and the second pulse signal are the same as the frequency of the reference pulse signal. The delay duration of the first interdigitated capacitor layer is half the period of the reference pulse signal. The first pulse signal and the second pulse signal are used to synthesize a frequency multiplication signal.

2. The frequency doubling device as described in claim 1, characterized in that, The first high-voltage switching module includes a first LDMOS transistor and a second LDMOS transistor, and the MOM capacitor further includes a second interdigitated capacitor layer; The first conducting terminal of the first LDMOS transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the first LDMOS transistor is connected to the first conducting terminal of the second LDMOS transistor, the second conducting terminal of the second LDMOS transistor is the output terminal of the first high-voltage switching module, the control terminal of the first LDMOS transistor is connected to the signal input terminal, the input terminal of the second interdigitated capacitor layer is connected to the control terminal of the first LDMOS transistor, the output terminal of the second interdigitated capacitor layer is connected to the control terminal of the second LDMOS transistor, the second interdigitated capacitor layer is configured to delay the signal received at the input terminal of the second interdigitated capacitor layer and then output it from the output terminal of the second interdigitated capacitor layer, the duty cycle of the reference pulse signal is Y, and the delay duration of the second interdigitated capacitor layer is Y / 2 of the period of the reference pulse signal.

3. The frequency doubling device as described in claim 2, characterized in that, The second high-voltage switching module includes a third LDMOS transistor and a fourth LDMOS transistor, and the MOM capacitor also includes a third interdigitated capacitor layer; The first conducting terminal of the third LDMOS transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the third LDMOS transistor is connected to the first conducting terminal of the fourth LDMOS transistor, the second conducting terminal of the fourth LDMOS transistor is the output terminal of the second high-voltage switching module, the control terminal of the third LDMOS transistor is connected to the output terminal of the first interdigital capacitor layer, the input terminal of the third interdigital capacitor layer is connected to the control terminal of the third LDMOS transistor, the output terminal of the third interdigital capacitor layer is connected to the control terminal of the fourth LDMOS transistor, and the third interdigital capacitor layer is configured to delay the signal received at the input terminal of the third interdigital capacitor layer and then output it from the output terminal of the third interdigital capacitor layer. The delay duration of the third interdigital capacitor layer is equal to the delay duration of the second interdigital capacitor layer.

4. The frequency doubling device as described in claim 3, characterized in that, The first LDMOS transistor, the second LDMOS transistor, the third LDMOS transistor, and the fourth LDMOS transistor are all N-type LDMOS transistors.

5. The frequency doubling device as described in claim 3, characterized in that, It also includes a pull-down resistor, the first end of which is connected to the output terminal of the first high-voltage switch module and the output terminal of the second high-voltage switch module, and the second end of which is connected to ground.

6. The frequency doubling device as described in claim 3, characterized in that, The second interdigitated capacitor layer, the first interdigitated capacitor layer, and the third interdigitated capacitor layer are stacked sequentially from top to bottom.

7. The frequency doubling device as described in claim 6, characterized in that, The first interdigitated capacitor layer includes multiple stacked sub-capacitor layers, and adjacent sub-capacitor layers are connected by metal vias.

8. A frequency multiplication device, characterized in that, It includes multiple frequency-doubled devices as described in claims 1-7 connected in series, wherein the frequency-doubled signal output by the preceding frequency-doubled device is used as the reference pulse signal of the following frequency-doubled device.

9. The multi-frequency doubling device as described in claim 8, characterized in that, The frequency multiplier device includes two frequency doublers connected in series.

10. The frequency multiplication device as described in claim 8, characterized in that, The frequency multiplier device includes three frequency doublers connected in series.

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