Clock switching circuit, chip and terminal

Abstract

This invention relates to the field of clock circuits, and discloses a clock switching circuit, chip, and terminal. The invention includes a frequency divider module, a first selection module, a second selection module, a logic selection module, and a third selection module. The frequency divider module can divide the clock signal to be divided, and in conjunction with the first and second selection modules, can select the corresponding divided signal output according to different clock signals. Simultaneously, in conjunction with the logic selection module and the third selection module, when the divided signals output by the first and second selection modules switch back and forth, the logic selection module enables the third selection module to use the clock signal output by the first selection module as a reference. It ensures that the third selection module only switches its output signal when the frequency of the clock signal output by the second selection module is lower than that of the clock signal output by the first selection module. This ensures that the working clock signal remains stable at all times, avoids glitches, and improves reliability.

Description

Technical Field

[0001] This invention relates to the field of clock circuits, and in particular to a clock switching circuit, chip, and terminal. Background Technology

[0002] Clock circuits are standard circuit modules in the field of digital circuits. In specific applications, clock circuits need to output different clock frequencies at different times. However, glitches can easily occur during the switching process, causing digital circuits to malfunction and affecting system operation. In severe cases, it can even cause the entire system to crash. Therefore, it is necessary to avoid glitches when switching frequencies. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a clock switching circuit that can avoid the occurrence of glitches.

[0004] The present invention also proposes a chip having the above-mentioned clock switching circuit.

[0005] The present invention also proposes a terminal having the above-mentioned clock switching circuit.

[0006] On one hand, a clock switching circuit according to an embodiment of the present invention includes a frequency division module, a first selection module, a second selection module, a logic selection module, and a third selection module. The frequency division module has a first enable terminal, a first clock receiving terminal, and n frequency division output terminals. The first enable terminal is used to receive a first clock enable signal, and the first clock receiving terminal is used to receive a clock signal to be divided. The first selection module has a first clock switching enable terminal, a first clock signal output terminal, and n-1 first frequency division input terminals. The first clock switching enable terminal is used to receive a first clock switching signal, and the n-1 first frequency division input terminals are sequentially electrically connected to the first to the (n-1)th frequency division output terminals of the frequency division module. The second selection module has a second clock switching enable terminal, a second clock signal output terminal, and n-1 second frequency division input terminals. The second clock switching enable terminal is used to receive a second clock switching signal, and the n-1 second frequency division input terminals are sequentially electrically connected to the second to the nth frequency division output terminals of the frequency division module. The logic selection module has a fourth clock switching enable terminal, a second enable terminal, a second clock signal receiving terminal, a third clock signal receiving terminal, and a selection output terminal. The fourth clock switching enable terminal is used to receive a third clock switching signal, the second enable terminal is used to receive a second clock enable signal, the second clock signal receiving terminal is electrically connected to the first clock signal output terminal, and the third clock signal receiving terminal is electrically connected to the second clock signal output terminal. The third selection module has a third clock switching enable terminal, a third clock signal output terminal, a third frequency divider input terminal, and a fourth frequency divider input terminal. The third clock switching enable terminal is electrically connected to the selection output terminal, the third frequency divider input terminal is electrically connected to the first clock signal output terminal, and the fourth frequency divider input terminal is electrically connected to the second clock signal output terminal. The third selection module, based on the signal from the selection output terminal, causes the third clock signal output terminal to output a working clock signal. The working clock signal is the same as the clock signal received by the third frequency divider input terminal or the clock signal received by the fourth frequency divider input terminal.

[0007] According to some embodiments of the present invention, the frequency divider module includes n first NOT gates and n falling-edge D flip-flops connected in sequence; wherein, the output terminal of the previous falling-edge D flip-flop is electrically connected to the clock input terminal of the next falling-edge D flip-flop, the output terminal of each falling-edge D flip-flop is electrically connected to the corresponding first frequency divider input terminal or the corresponding second frequency divider input terminal, the output terminal of each falling-edge D flip-flop is electrically connected to the input terminal of the corresponding first NOT gate, the output terminal of the first NOT gate is electrically connected to the input terminal of the corresponding falling-edge D flip-flop, the clock enable terminal of each falling-edge D flip-flop serves as the first enable terminal, and the clock input terminal of the first falling-edge D flip-flop serves as the first clock receiver terminal.

[0008] According to some embodiments of the present invention, the logic selection module includes a rising-edge D flip-flop, a second NOT gate, a first AND gate, a second AND gate, a first AND gate, a second AND gate, a third AND gate, a NOR gate, an OR gate, and a third NOT gate; a rising-edge D flip-flop, wherein the clock input terminal of the rising-edge D flip-flop serves as the second clock signal receiving terminal, the clock enable terminal of the rising-edge D flip-flop serves as the second enable terminal, and the output terminal of the rising-edge D flip-flop serves as the selection output terminal; the input terminal of the second NOT gate serves as the third clock signal receiving terminal; the first input terminal of the first AND gate is electrically connected to the output terminal of the rising-edge D flip-flop, and the second input terminal of the first AND gate is electrically connected to the input terminal of the second NOT gate; the first input terminal of the second AND gate is electrically connected to the output terminal of the rising-edge D flip-flop. The output of the two NOT gates is electrically connected; the first input of the third AND gate is electrically connected to the output of the first AND gate, and the second input of the third AND gate serves as the fourth clock switching enable terminal; the first input of the NOR gate is electrically connected to the second input of the third AND gate, and the second input of the NOR gate is electrically connected to the output of the second AND gate; the first input of the OR gate is electrically connected to the output of the third AND gate, and the second input of the OR gate is electrically connected to the output of the NOR gate, and the output of the OR gate is electrically connected to the input of the rising-edge D flip-flop; the input of the third NOT gate is electrically connected to the output of the rising-edge D flip-flop, and the output of the third NOT gate is electrically connected to the second input of the second AND gate.

[0009] According to some embodiments of the present invention, a frequency modulation module is further included, the frequency modulation module having a power input terminal, a second clock receiving terminal, a third clock receiving terminal, a reference voltage terminal, and a fourth clock signal output terminal; wherein, the power input terminal is used to be electrically connected to a power supply, the second clock receiving terminal is used to receive a first clock signal, the third clock receiving terminal is used to receive a second clock signal, the clock signal output terminal is electrically connected to the first clock receiving terminal, the reference voltage terminal is used to be electrically connected to a reference voltage, the first clock signal and the second clock signal are inverted clock signals, and the frequency modulation module can adjust the frequency of the first clock signal so that the fourth clock signal output terminal outputs a third clock signal of a different frequency.

[0010] According to some embodiments of the present invention, the frequency modulation module includes a comparator, a waveform shaping unit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor; a first terminal of the first switch is connected to the power input terminal, and the control terminal of the first switch serves as the second clock receiving terminal; a first terminal of the first capacitor is electrically connected to the second terminal of the first switch; a first terminal of the second switch is electrically connected to the second terminal of the first capacitor, and the control terminal of the second switch is electrically connected to the control terminal of the first switch; a first input terminal of the comparator is electrically connected to the second terminal of the second switch, and the second input terminal of the comparator serves as the reference voltage terminal; the input terminal of the waveform shaping unit is electrically connected to the output terminal of the comparator. The waveform shaping unit is electrically connected to the output terminal of the third switch, which serves as the output terminal of the fourth clock signal. The first terminal of the third switch is electrically connected to the second terminal of the first switch, and the control terminal of the third switch serves as the third clock receiver. The second terminal of the third switch is grounded. The first terminal of the fourth switch is electrically connected to the second terminal of the first capacitor, and the control terminal of the fourth switch is electrically connected to the control terminal of the third switch. The second terminal of the fourth switch is grounded. The first terminal of the fifth switch is electrically connected to the second terminal of the second switch, and the control terminal of the fifth switch is electrically connected to the output terminal of the comparator. The second terminal of the fifth switch is grounded. The first terminal of the second capacitor is electrically connected to the second terminal of the second switch, and the second terminal of the second capacitor is grounded.

[0011] According to some embodiments of the present invention, the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.

[0012] According to some embodiments of the present invention, the waveform shaping unit includes an edge trigger.

[0013] According to some embodiments of the present invention, the first capacitor and the second capacitor are variable capacitors.

[0014] On the other hand, the chip according to an embodiment of the present invention includes a clock switching circuit according to the above embodiment of the present invention.

[0015] On the other hand, the terminal according to an embodiment of the present invention includes a clock switching circuit according to the above embodiment of the present invention.

[0016] The embodiments of the present invention have at least the following beneficial effects: the frequency division module can divide the clock signal to be divided, and in conjunction with the first selection module and the second selection module, it can select the corresponding frequency division signal output according to different clock signals. At the same time, in conjunction with the logic selection module and the third selection module, when the frequency division signal output by the first selection module switches back and forth, and when the frequency division signal output by the second selection module switches back and forth, the logic selection module can make the third selection module use the clock signal output by the first selection module as a reference, and ensure that the frequency of the clock signal output by the second selection module is lower than that of the clock signal output by the first selection module before the third selection module switches the output signal. This ensures that the clock signal output by the third selection module remains stable at all times, avoids glitches, and ensures that the subsequent digital circuits can work normally, effectively improving reliability.

[0017] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. Attached Figure Description

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a schematic diagram of the clock switching circuit according to an embodiment of the present invention;

[0020] Figure 2 for Figure 1 The circuit structure diagram of the frequency divider module of the clock switching circuit is shown.

[0021] Figure 3 for Figure 1 The circuit structure diagram of the logic selection module of the clock switching circuit is shown.

[0022] Figure 4 for Figure 1 The waveform diagram of the clock switching circuit is shown below;

[0023] Figure 5 This is a waveform diagram of the clock switching circuit when no logic selection module is used.

[0024] Figure 6 This is a schematic diagram of the clock switching circuit according to another embodiment of the present invention;

[0025] Figure 7 for Figure 6 The circuit structure diagram of the frequency modulation module of the clock switching circuit is shown.

[0026] Figure 8 for Figure 6 The waveform diagram of the frequency modulation module is shown below;

[0027] Figure 9 This is a schematic diagram of the circuit structure of the frequency modulation module of the clock switching circuit according to another embodiment of the present invention;

[0028] Figure 10 for Figure 9 The circuit structure diagram of the voltage regulator module of the clock switching circuit is shown.

[0029] Figure 11 This is a schematic diagram of the circuit structure of the frequency modulation module of the clock switching circuit according to another embodiment of the present invention;

[0030] Figure 12 for Figure 11 The circuit structure diagram of the voltage regulator module of the clock switching circuit is shown.

[0031] Figure 13 This is a schematic diagram of the frequency modulation module of the clock switching circuit according to another embodiment of the present invention.

[0032] Reference numerals in the attached diagram: frequency division module 100, first selection module 200, second selection module 300, logic selection module 400, third selection module 500, frequency modulation module 600. Detailed Implementation

[0033] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0034] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. Furthermore, the descriptions of "upper," "lower," "left," "right," "top," and "bottom" used in this invention are only relative to the relative positional relationships of the various components of the invention in the accompanying drawings.

[0035] Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention. The term "and / or" as used herein includes any combination of one or more of the associated listed items.

[0036] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from one another. For example, without departing from the scope of this disclosure, a first element may also be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0037] On the one hand, refer to Figure 1According to an embodiment of the present invention, a clock switching circuit includes a frequency division module 100, a first selection module 200, a second selection module 300, a logic selection module 400, and a third selection module 500. The frequency division module 100 has a first enable terminal, a first clock receiving terminal, and n frequency division output terminals. The first enable terminal is used to receive a first clock enable signal, and the first clock receiving terminal is used to receive a clock signal to be divided. The first selection module 200 has a first clock switching enable terminal, a first clock signal output terminal, and n-1 first frequency division input terminals. The clock switching enable terminal is used to receive the first clock switching signal. The n-1 first frequency divider input terminals are sequentially electrically connected to the first to the (n-1)th frequency divider output terminals of the frequency divider module 100. The second selection module 300 has a second clock switching enable terminal, a second clock signal output terminal, and n-1 second frequency divider input terminals. The second clock switching enable terminal is used to receive the second clock switching signal. The n-1 second frequency divider input terminals are sequentially electrically connected to the second to the nth frequency divider output terminals of the frequency divider module 100. Corresponding electrical connections; the logic selection module 400 has a fourth clock switching enable terminal, a second enable terminal, a second clock signal receiving terminal, a third clock signal receiving terminal, and a selection output terminal. The fourth clock switching enable terminal is used to receive a third clock switching signal, the second enable terminal is used to receive a second clock enable signal, the second clock signal receiving terminal is electrically connected to the first clock signal output terminal, and the third clock signal receiving terminal is electrically connected to the second clock signal output terminal. The third selection module 500 has a third clock switching enable terminal, a third clock signal output terminal, a third frequency divider input terminal, and a fourth frequency divider input terminal. The third clock switching enable terminal is electrically connected to the selection output terminal, the third frequency divider input terminal is electrically connected to the first clock signal output terminal, and the fourth frequency divider input terminal is electrically connected to the second clock signal output terminal. The third selection module 500, according to the signal from the selection output terminal, causes the third clock signal output terminal to output a working clock signal. The working clock signal is the same as the clock signal received by the third frequency divider input terminal or the clock signal received by the fourth frequency divider input terminal.

[0038] Working principle: The frequency divider module 100 can divide the clock signal to be divided and output the divided frequency signal OSC1 (2-divided), OSC2 (4-divided), OSC3 (8-divided), ... and 2-divided signals to the first selection module 200 respectively. n-1 The frequency division signal OSCn-1, and the frequency division module 100 also outputs a 4-division signal OSC2, an 8-division signal OSC3, ... and a 2-division signal OSCn-1 to the second selection module 300. nThe frequency division signal is OSCn; it should be noted that the clock signal CLK1 output by the first clock signal output terminal of the first selection module 200 is the frequency division signal received by one of the n-1 first frequency division input terminals, and the clock signal CLK2 output by the second clock signal output terminal of the second selection module 300 is the frequency division signal received by one of the n-1 second frequency division input terminals; that is, the first selection module 200 will output the corresponding frequency division signal to the logic selection module 400 and the third selection module 500 according to the change of the first clock switching signal; the second selection module 300 will also output the corresponding frequency division signal according to the second clock switching signal. The signal change outputs a corresponding frequency division signal to the logic selection module 400 and the third selection module 500. The third selection module 500 determines whether to output the clock signal CLK1 of the first selection module 200 or the clock signal CLK2 of the second selection module 300 based on the selection signal output from the logic selection module 400. That is, the working clock signal of the third selection module 500 is either clock signal CLK1 or clock signal CLK2. When the logic selection module 400 receives the third clock switching signal and determines that a switch is needed, the logic selection module 400 will first determine the clock signal output from the first selection module 200. The logic selection module 400 determines the frequency of clock signal CLK1 and clock signal CLK2 output by the second selection module 300. If it synchronously determines that the frequency of clock signal CLK2 output by the second selection module 300 is lower than the frequency of clock signal CLK1 output by the first selection module 200, it outputs a corresponding selection signal, causing the third selection module 500 to switch to output clock signal CLK2 from the second selection module 300. Otherwise, even if the logic selection module 400 confirms the need to switch based on feedback from the third clock switching signal, it will only switch if it determines that the frequency of clock signal CLK2 output by the second selection module 300 is higher than the frequency of clock signal CLK1 from the first selection module 200. When module 200 outputs clock signal CLK1, logic selection module 400 will not output a corresponding selection signal to switch the third selection module 500. That is, under normal circumstances, the third selection module 500 will output the clock signal CLK1 output by the first selection module 200. Only when logic selection module 400 receives the third switching clock signal that needs to be switched, and determines that the frequency of the clock signal CLK2 output by the second selection module 300 is lower than the frequency of the clock signal CLK1 output by the first selection module 200, will it control the third selection module 500 to switch to outputting the clock signal CLK2 output by the second selection module 300. Therefore, the circuit module in this embodiment of the invention can ensure that the output clock signal remains stable at all times during the switching process of the third selection module 500, avoiding glitches, thereby ensuring that subsequent digital circuits can work normally and effectively improving the reliability of the clock signal.

[0039] Reference Figure 2In some embodiments of the present invention, the frequency divider module 100 includes n first NOT gates and n falling-edge D flip-flops connected in sequence; wherein, the output terminal of the previous falling-edge D flip-flop is electrically connected to the clock input terminal of the next falling-edge D flip-flop, the output terminal of each falling-edge D flip-flop is electrically connected to the corresponding first frequency divider input terminal or the corresponding second frequency divider input terminal, the output terminal of each falling-edge D flip-flop is electrically connected to the input terminal of the corresponding first NOT gate, the output terminal of the first NOT gate is electrically connected to the input terminal of the corresponding falling-edge D flip-flop, the clock enable terminal of each falling-edge D flip-flop serves as the first enable terminal, and the clock input terminal of the first falling-edge D flip-flop serves as the first clock receiving terminal. By using the cascaded structure of multiple first NOT gates and falling-edge D flip-flops, the sequentially connected falling-edge D flip-flops can output frequency divider signals OSC1 (divided by 2), OSC2 (divided by 4), OSC3 (divided by 8), ..., OSCn (divided by n). In this embodiment, the number of falling-edge D flip-flops and first NOT gates is not specifically limited. The corresponding number can be set according to actual needs, that is, n is an integer and n≥1. Depending on the specific needs, n can be any integer such as 2, 3, 4, or 5.

[0040] Reference Figure 3In some embodiments of the present invention, the logic selection module 400 includes a rising-edge D flip-flop, a second NOT gate, a first AND gate, a second AND gate, a first AND gate, a second AND gate, a third AND gate, a NOR gate, an OR gate, and a third NOT gate; the rising-edge D flip-flop has its clock input terminal serving as the second clock signal receiver, its clock enable terminal serving as the second enable terminal, and its output terminal serving as the selection output terminal; the input terminal of the second NOT gate serves as the third clock signal receiver; the first input terminal of the first AND gate is electrically connected to the output terminal of the rising-edge D flip-flop, and the second input terminal of the first AND gate is electrically connected to the input terminal of the second NOT gate; the first input terminal of the second AND gate is electrically connected to the output terminal of the rising-edge D flip-flop. The output of the second NOT gate is electrically connected; the first input of the third AND gate is electrically connected to the output of the first AND gate, and the second input of the third AND gate serves as the fourth clock switching enable terminal; the first input of the NOR gate is electrically connected to the second input of the third AND gate, and the second input of the NOR gate is electrically connected to the output of the second AND gate; the first input of the OR gate is electrically connected to the output of the third AND gate, and the second input of the OR gate is electrically connected to the output of the NOR gate, and the output of the OR gate is electrically connected to the input of the rising-edge D flip-flop; the input of the third NOT gate is electrically connected to the output of the rising-edge D flip-flop, and the output of the third NOT gate is electrically connected to the second input of the second AND gate. In this embodiment, the rising-edge D flip-flop, the second NOT gate, the first AND gate, the second AND gate, the first AND gate, the second AND gate, the third AND gate, the NOR gate, the OR gate, and the third NOT gate are all conventional structures. In this embodiment, by connecting them in the above order, the logic selection module 400 can simultaneously judge based on the third clock switching signal, the clock signal CLK1 output by the first clock signal output terminal, and the clock signal CLK2 output by the second clock signal output terminal, and output the corresponding selection signal to control whether the working clock signal of the third selection module 500 is switched. Thus, under the premise of ensuring that the third selection module 500 stably outputs the clock signal CLK1 output by the first selection module 200, when switching is required, the working clock signal is switched only when the frequency of the clock signal CLK2 output by the second selection module 300 is lower than that of the clock signal CLK2 output by the first selection module 200. This can avoid glitches in the working clock signal output by the third selection module 500 and effectively improve reliability.

[0041] Specifically, you can refer to Figure 4In this embodiment of the invention, after employing the logic selection module 400, the working clock signal of the third selection module 500 is switched from the output clock signal CLK1 to the clock signal CLK2, and then back to the clock signal CLK1. It can be seen that during the switching process of the first selection module 200, glitches in the working clock signal can be avoided, and the synchronization reference... Figure 5 The waveform diagram shows a traditional clock switching circuit, without the logic selection module 400. It can be seen that when switching is controlled by the selection signal, the working clock signal exhibits glitches at the corresponding switching moments. This can easily cause subsequent circuit modules to malfunction. Therefore, in conjunction with... Figure 4 As can be seen, the clock switching circuit of this invention can effectively solve the glitches that occur during the switching process and ensure that the working clock signal can be output stably.

[0042] In some embodiments of the present invention, the first selection module 200, the second selection module 300, and the third selection module 500 all employ selectors.

[0043] Reference Figure 6 In some embodiments of the present invention, a frequency modulation module 600 is further included. The frequency modulation module 600 has a power input terminal, a second clock receiving terminal, a third clock receiving terminal, a reference voltage terminal, and a fourth clock signal output terminal. The power input terminal is electrically connected to a power supply. The second clock receiving terminal receives a first clock signal. The third clock receiving terminal receives a second clock signal. The clock signal output terminal is electrically connected to the first clock receiving terminal. The reference voltage terminal is electrically connected to a reference voltage. The first clock signal and the second clock signal are inverted clock signals. The frequency modulation module 600 can adjust the frequency of the first clock signal so that the fourth clock signal output terminal outputs a third clock signal of a different frequency. Using the frequency modulation module 600, the initial frequency of the clock signal to be divided can be controlled according to requirements, and then it enters the frequency division module 100 for division by two, four, or two frequencies. n Frequency division can effectively improve the adaptability range, thereby enabling adjustment of the required output frequency.

[0044] Reference Figure 7In some embodiments of the present invention, the frequency modulation module 600 includes a comparator, a waveform shaping unit, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a first capacitor C1, and a second capacitor C2; the first terminal of the first switch S1 is connected to the power input terminal and connected to the power supply VDD, and the control terminal of the first switch S1 serves as the second clock receiving terminal; the first terminal of the first capacitor C1 is electrically connected to the second terminal of the first switch S1; the first terminal of the second switch S2 is electrically connected to the second terminal of the first capacitor C1, and the control terminal of the second switch S2 is electrically connected to the control terminal of the first switch S1; the first input terminal of the comparator is electrically connected to the second terminal of the second switch S2, and the second input terminal of the comparator serves as the reference voltage terminal; the input terminal of the waveform shaping unit is connected to the comparator... The output terminal of the comparator is electrically connected, and the output terminal of the waveform shaping unit serves as the fourth clock signal output terminal; the first terminal of the third switch S3 is electrically connected to the second terminal of the first switch S1, the control terminal of the third switch S3 serves as the third clock receiving terminal, and the second terminal of the third switch S3 is grounded; the first terminal of the fourth switch S4 is electrically connected to the second terminal of the first capacitor C1, the control terminal of the fourth switch S4 is electrically connected to the control terminal of the third switch S3, and the second terminal of the fourth switch S4 is grounded; the first terminal of the fifth switch S5 is electrically connected to the second terminal of the second switch S2, the control terminal of the fifth switch S5 is electrically connected to the output terminal of the comparator, and the second terminal of the fifth switch S5 is grounded; the first terminal of the second capacitor C2 is electrically connected to the second terminal of the second switch S2, and the second terminal of the second capacitor C2 is grounded.

[0045] Reference Figure 7 In this embodiment, the first switch S1 and the second switch S2 are controlled by a first clock signal, and the third switch S3 and the fourth switch S4 are controlled by a second clock signal. The first clock signal and the second clock signal are an inverted pair of clock signals, and the first clock signal is the clock signal whose frequency needs to be adjusted. Because the first clock signal and the second clock signal are an inverted pair of clock signals, when the first switch S1 and the second switch S2 are closed, the third switch S3 and the fourth switch S4 are open, and when the first switch S1 and the second switch S2 are open, the third switch S3 and the fourth switch S4 are closed. When the first switch S1 and the second switch S2 are closed, and the third switch S3 and the fourth switch S4 are open, the power supply VDD charges the first capacitor C1 and the second capacitor C2. When the first switch S1 and the second switch S2 are open, and the third switch S3 and the fourth switch S4 are closed, the first capacitor C1 discharges. The first clock signal can be directly provided by a crystal oscillator or an oscillator, and the second clock signal can be obtained by using a NOT gate.

[0046] Reference Figure 7 In some embodiments of the present invention, the capacitance value of the first capacitor C1 is less than the capacitance value of the second capacitor C2. Therefore, the charging time of the second capacitor C2 is longer than the charging time of the first capacitor C1; when the first capacitor C1 is fully charged, the second capacitor C2 is not yet fully charged. The state of the fifth switch S5 can be controlled by the output signal of the comparator. In one embodiment, when the output signal of the comparator flips, the switching state of the fifth switch S5 is changed. When the charging voltage V of the second capacitor C2... CAP Greater than the reference voltage V REF When the comparator flips, it closes the fifth switch S5, causing the second capacitor C2 to discharge. It should be noted that when the fifth switch S5 is closed, the second capacitor C2 should be fully discharged to ensure a fixed period for the output clock. For example, the closing time of the fifth switch S5 can be controlled to allow the second capacitor C2 sufficient discharge time to ensure it is fully discharged. This can be achieved by setting the capacitance values ​​of the first capacitor C1 and the second capacitor C2, and the reference voltage V. REF The voltage value is used to adjust the period of the comparator's output signal. In this embodiment, the reference voltage V... REF Less than the power supply VDD.

[0047] Reference Figure 7 In some embodiments of the present invention, the waveform shaping unit includes an edge-triggered flip-flop. The waveform shaping unit is used to adjust the duty cycle of the comparator's output signal. In some embodiments of the present invention, the waveform shaping unit includes a rising-edge flip-flop, which, for example, can be toggled on the rising edge of the comparator's output to adjust the duty cycle of the output clock signal.

[0048] Reference Figure 7 In some embodiments of the present invention, the first capacitor C1 and the second capacitor C2 are variable capacitors. That is, the first capacitor C1 and the second capacitor C2 can be adjusted according to actual needs, thereby enabling the frequency modulation module 600 to output clock signals of different frequencies.

[0049] The clock signal to be divided controls the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4. The first capacitor C1 charges the second capacitor C2, and a comparator compares the voltage across the second capacitor C2, outputting the final divided clock waveform. In application, the first and second switches S1 and S2 are simultaneously open / closed, as are the third and fourth switches S3 and S4. Furthermore, the first and second switches S1 and S2, and the third and fourth switches S3 and S4, are alternately open / closed to alternately charge and discharge the first capacitor C1 during different clock cycles. The capacitance of the second capacitor C2 should be greater than that of the first capacitor C1, preventing the second capacitor C2 from being fully charged in one go, thus achieving the purpose of frequency division. The fifth switch S5 provides a discharge path for the second capacitor C2. Finally, a waveform shaping unit converts the comparator output into a clock waveform with a 50% duty cycle. It should be understood that this application is not limited to implementing a clock waveform with a 50% duty cycle; for example, it can also be a clock waveform with a 25% duty cycle, and the present invention does not limit this.

[0050] In one embodiment, the capacitance of the first capacitor C1 is 1 / 3 of the capacitance of the second capacitor C2, V REF Let's take 5 / 6VDD as an example for explanation. Figure 8 The waveforms during circuit operation are shown. Because the first capacitor C1 is smaller than the second capacitor C2, the first capacitor C1 completes a full charge and discharge within one clock cycle, while the second capacitor C2 cannot be fully charged in one cycle. Instead, it is charged in a "stepped" manner over multiple cycles through the first capacitor C1. Finally, relying on VDD (which is smaller than VDD)... REF The comparator is toggled, and then a waveform shaping unit outputs a frequency-divided clock signal with a 50% duty cycle. In this embodiment, the relationship at the second capacitor C2 is as shown in the following formula:

[0051]

[0052] Where τ is the charging time constant of the second capacitor C2, T is the period of the first clock signal, and t is the time required for the second capacitor C2 to charge. From this formula, we have the relationship that t is less than T, and the final clock signal output period is 4 times the period of the first clock signal. This means that a 4-fold clock signal can be obtained from the first clock signal, and then this 4-fold clock signal is output as the clock signal to be divided to the frequency divider module 100.

[0053] When the values ​​of the first capacitor C1 and the second capacitor C2 are taken, and V REFWhile the values ​​may differ, the underlying principle remains the same, enabling integer frequency modulation at different multiples. The frequency modulation module 600 described in this article, employing analog devices, allows its modulation coefficients to be adjusted beyond the limitations of digital circuits, enabling modulation with arbitrary coefficients. Compared to traditional integer frequency modulation circuits based on digital devices, the modulation coefficient adjustment is more flexible, and decimal point frequency modulation can also be achieved, thus obtaining clock signals of different frequencies to be divided.

[0054] Reference Figure 9 and Figure 10 In some embodiments of the present invention, the frequency modulation module 600 further includes a voltage regulator unit. The input terminal of the voltage regulator unit is connected to the power input terminal, and the output terminal of the voltage regulator unit is connected to the first terminal of the first switch S1. The voltage regulator unit includes PMOS transistors MP1, MP2, MP3, NMOS transistors MN1, MN2, and MN3. The source of PMOS transistor MP1 is connected to the power supply VCC, and the gate of PMOS transistor MP1 is connected to the power input terminal, i.e., connected to the power supply VDD. The source of PMOS transistor MP2 is connected to the drain of PMOS transistor MP1, and the gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP1. The drain of PMOS transistor MP2 serves as the output terminal of the waveform shaping unit. The gate of PMOS transistor MP3... The drain of PMOS transistor MP2 is connected to the drain of PMOS transistor MP3, the drain of PMOS transistor MP3 is connected to ground VSS, and the source of PMOS transistor MP3 is connected to the gate of PMOS transistor MP1; the source of NMOS transistor MN1 is connected to ground VSS, and the gate of NMOS transistor MN1 is connected to the gate of PMOS transistor MP1; the source of NMOS transistor MN2 is connected to the drain of NMOS transistor MN1, the gate of NMOS transistor MN2 is connected to the gate of PMOS transistor MP1, and the drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP2; the source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN1, the gate of NMOS transistor MN3 is connected to the drain of PMOS transistor MP2, and the drain of NMOS transistor MN3 is connected to the source of PMOS transistor MP1.

[0055] The voltage signal output from the voltage regulator unit after the power supply VDD has only two modes: high level and low level, effectively filtering out glitches from the input power supply VDD. In a specific embodiment, when VDD = 0, MP1 and MP2 are turned on, MN1 and MN2 are turned off, and the output Vout1 is high. Then MP3 is turned off and MN3 is turned on, and the voltage at node X is VCC - vthn (vthn is the threshold voltage of the NMOS transistor). When the power supply VDD rises from 0V, because the initial voltage at node X is high, MN2 must be turned on when the power supply VDD is greater than VCC / 2 before Vout1 starts to decrease, i.e., the rising threshold vrise is greater than VCC / 2. On the other hand, when VDD = VCC, MP1 and MP2 are turned off, MN1 and MN2 are turned on, and the output Vout1 is low. Then MP3 is turned on and MN3 is turned off, and the voltage at node Y is VSS + vthp (vthp is the threshold voltage of the PMOS transistor). When VDD drops from VCC, due to the low initial voltage at node Y, MP2 can only conduct when VDD is less than VCC / 2, and Vout1 only starts to rise then. In other words, the falling threshold vfall is less than VCC / 2. In short, the rising threshold is greater than the falling threshold, achieving a hysteresis function. Glitches in the input signal voltage VDD during power-on and power-off processes can be effectively filtered out. Combined with the voltage regulator unit, this ensures the output voltage of the voltage regulator unit remains stable, avoiding glitches during power-on and power-off processes, thus ensuring a stable charging process for the first capacitor C1, and consequently ensuring a stable output of the clock signal to be divided.

[0056] In conjunction with the logic selection module 400 and the third selection module 500, the working clock signal can be kept stable during the switching process of the third selection module 500.

[0057] Reference Figure 11 and Figure 12In some embodiments of the present invention, the frequency modulation module 600 further includes a power switching unit. The output terminal Vout2 of the power switching unit is connected to the input terminal of the voltage regulation unit. The power switching unit includes resistors R1 and R2, an NMOS transistor MN4, a PMOS transistor MP4, and a PMOS transistor MP5. The power supply VDD is connected to the gate of the NMOS transistor MN4, and the drain of the NMOS transistor MN4 is grounded. A backup power supply with the same voltage as the power supply VDD is connected to the drain of the PMOS transistor MP4. The gate of the PMOS transistor MP4 is connected to the first end of resistor R1, and the second end of resistor R1 is grounded. The source of the PMOS transistor MP4 is connected to the first end of resistor R2 and the source of the PMOS transistor MP5, respectively. The power supply VDD is also connected to the drain of the PMOS transistor MP5. The source of the PMOS transistor MP5 serves as the output terminal Vout2 of the power switching unit. The gate of the PMOS transistor MP5 is also connected to the second end of resistor R2 and the source of the NMOS transistor MN4. It should be noted that when the power supply VDD is supplying power normally, NMOS transistor MN4 is turned on, which pulls down the gate of PMOS transistor MP5, causing MP5 to also turn on. At this time, the voltage between the gate and source of PMOS transistor MP4 is the on-state voltage drop of MP5, so MP4 is turned off. Therefore, the backup power supply and the output terminal Vout2 of the power switching unit are disconnected, and the power switching unit outputs power from VDD. However, when the power supply VDD is disconnected, NMOS transistor MN4 is turned off, and the gate of PMOS transistor MP4 is pulled down by resistor R1, so MP4 turns on, and then the gate of PMOS transistor MP5 also turns on. Due to the pull-up effect of resistor R2, PMOS transistor MP5 is cut off, so the output of the power switching unit, Vout2, is output from the backup power supply. Therefore, the circuit structure of the power switching unit ensures that the entire clock switching circuit operates normally. In conjunction with the voltage regulator unit, the frequency modulation module 600 can also operate stably during the switching process between the backup power supply and the power supply VDD, thereby ensuring that the clock signal to be divided can be output stably. In conjunction with the logic selection module 400 and the third selection module 500, the final output clock signal of the clock switching circuit remains stable, ensuring that subsequent circuit modules can operate normally, effectively improving stability and reliability.

[0058] In addition, refer to Figure 13 In some embodiments of the present invention, the frequency modulation module 600 may also include only a power switching unit. Unlike the above embodiments, the output terminal of the power switching unit is connected to the first terminal of the first switch S1, while the circuit structure of the power switching unit is consistent with that of the above embodiments, and the function is also the same.

[0059] On the other hand, the chip according to an embodiment of the present invention includes a clock switching circuit according to the above embodiment of the present invention.

[0060] On the other hand, the terminal according to an embodiment of the present invention includes a clock switching circuit according to the above embodiment of the present invention.

[0061] On the other hand, the chip according to an embodiment of the present invention includes a clock switching circuit according to the above embodiment of the present invention.

[0062] Other configurations and operations of the chip according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0063] The clock switching circuit of the above embodiments of the present invention is used in the chip to ensure that the chip maintains normal operation, avoids chip failure caused by glitches, and effectively improves reliability.

[0064] On the other hand, the terminal according to an embodiment of the present invention includes a clock switching circuit according to the above embodiment of the present invention.

[0065] Other configurations and operations of the terminal according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0066] The clock switching circuit of the above embodiments of the present invention is used in the terminal to ensure that the terminal maintains normal operation, avoids chip failure caused by glitches, and effectively improves reliability.

[0067] According to embodiments of the present invention, by such a configuration, at least the following effects can be achieved. The embodiments of the present invention have at least the following beneficial effects: the frequency divider module 100 can divide the clock signal to be divided, and in conjunction with the first selection module 200 and the second selection module 300, can select the corresponding frequency divider signal output according to different clock signals. Simultaneously, in conjunction with the logic selection module 400 and the third selection module 500, when the frequency divider signal output by the first selection module 200 switches back and forth, and when the frequency divider signal output by the second selection module 300 switches back and forth, the logic selection module 400 enables the third selection module 500 to use the clock signal output by the first selection module 200 as a reference, and ensures that the frequency of the clock signal output by the second selection module 300 is lower than that of the clock signal output by the first selection module 200 before the third selection module 500 switches its output signal. This ensures that the clock signal output by the third selection module 500 remains stable at all times, avoiding glitches, and thus ensuring that subsequent digital circuits can operate normally, effectively improving reliability.

[0068] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this disclosure, as long as they achieve the same technical effects, should be included within the scope of protection of this disclosure and fall under the protection scope of the present invention. Within the protection scope of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A clock switching circuit, characterized in that, include: The frequency divider module (100) has a first enable terminal, a first clock receiving terminal and n frequency divider output terminals. The first enable terminal is used to receive a first clock enable signal, and the first clock receiving terminal is used to receive a clock signal to be divided. The first selection module (200) has a first clock switching enable terminal, a first clock signal output terminal and n-1 first frequency division input terminals. The first clock switching enable terminal is used to receive a first clock switching signal. The n-1 first frequency division input terminals are electrically connected to the first frequency division output terminal to the n-1th frequency division output terminal of the frequency division module (100) in sequence. The second selection module (300) has a second clock switching enable terminal, a second clock signal output terminal and n-1 second frequency division input terminals. The second clock switching enable terminal is used to receive the second clock switching signal. The n-1 second frequency division input terminals are electrically connected to the second to the nth frequency division output terminals of the frequency division module (100) in sequence. The logic selection module (400) has a fourth clock switching enable terminal, a second enable terminal, a second clock signal receiving terminal, a third clock signal receiving terminal, and a selection output terminal. The fourth clock switching enable terminal is used to receive a third clock switching signal, the second enable terminal is used to receive a second clock enable signal, the second clock signal receiving terminal is electrically connected to the first clock signal output terminal, and the third clock signal receiving terminal is electrically connected to the second clock signal output terminal. The third selection module (500) has a third clock switching enable terminal, a third clock signal output terminal, a third frequency divider input terminal, and a fourth frequency divider input terminal. The third clock switching enable terminal is electrically connected to the selection output terminal, the third frequency divider input terminal is electrically connected to the first clock signal output terminal, and the fourth frequency divider input terminal is electrically connected to the second clock signal output terminal. The third selection module (500) outputs a working clock signal from the third clock signal output terminal according to the signal from the selection output terminal. The working clock signal is the same as the clock signal received by the third frequency divider input terminal or the clock signal received by the fourth frequency divider input terminal.

2. The clock switching circuit according to claim 1, characterized in that, The frequency divider module (100) includes n first NOT gates and n falling-edge D flip-flops that are electrically connected in sequence; In this configuration, the output of the previous falling-edge D flip-flop is electrically connected to the clock input of the next falling-edge D flip-flop; the output of each falling-edge D flip-flop is electrically connected to the corresponding first frequency divider input or the corresponding second frequency divider input; the output of each falling-edge D flip-flop is electrically connected to the corresponding input of the first NOT gate; the output of the first NOT gate is electrically connected to the corresponding input of the falling-edge D flip-flop; the clock enable terminal of each falling-edge D flip-flop serves as the first enable terminal; and the clock input of the first falling-edge D flip-flop serves as the first clock receiver terminal.

3. The clock switching circuit according to claim 1, characterized in that, The logic selection module (400) includes: A rising-edge D flip-flop, wherein the clock input terminal of the rising-edge D flip-flop serves as the second clock signal receiving terminal, the clock enable terminal of the rising-edge D flip-flop serves as the second enable terminal, and the output terminal of the rising-edge D flip-flop serves as the selection output terminal. The second NOT gate, the input of the second NOT gate serves as the receiving end of the third clock signal; The first AND gate has its first input terminal electrically connected to the output terminal of the rising-edge D flip-flop, and its second input terminal electrically connected to the input terminal of the second NOT gate. The second AND gate, wherein the first input terminal of the second AND gate is electrically connected to the output terminal of the second NOT gate; The third AND gate, wherein the first input terminal of the third AND gate is electrically connected to the output terminal of the first AND gate, and the second input terminal of the third AND gate serves as the fourth clock switching enable terminal; The NOR gate has its first input terminal electrically connected to the second input terminal of the third AND gate, and its second input terminal electrically connected to the output terminal of the second AND gate. The OR gate is electrically connected to the output of the third AND gate, the second input of the OR gate is electrically connected to the output of the NOR gate, and the output of the OR gate is electrically connected to the input of the rising edge D flip-flop. The third NOT gate has its input terminal electrically connected to the output terminal of the rising-edge D flip-flop, and its output terminal electrically connected to the second input terminal of the second AND gate.

4. The clock switching circuit according to claim 1, characterized in that, It also includes a frequency modulation module (600), which has a power input terminal, a second clock receiving terminal, a third clock receiving terminal, a reference voltage terminal and a fourth clock signal output terminal; The power input terminal is electrically connected to a power source, the second clock receiving terminal is used to receive a first clock signal, the third clock receiving terminal is used to receive a second clock signal, the clock signal output terminal is electrically connected to the first clock receiving terminal, the reference voltage terminal is electrically connected to a reference voltage, the first clock signal and the second clock signal are inverted clock signals, and the frequency modulation module (600) can adjust the frequency of the first clock signal so that the fourth clock signal output terminal outputs a third clock signal of a different frequency.

5. The clock switching circuit according to claim 4, characterized in that, The frequency modulation module (600) includes: A first switch, the first end of which is connected to the power input terminal, and the control terminal of the first switch serving as the second clock receiver; A first capacitor, wherein a first terminal of the first capacitor is electrically connected to a second terminal of the first switch; The second switch has its first terminal electrically connected to the second terminal of the first capacitor, and its control terminal electrically connected to the control terminal of the first switch. A comparator, wherein the first input terminal of the comparator is electrically connected to the second terminal of the second switch, and the second input terminal of the comparator serves as the reference voltage terminal; A waveform shaping unit, wherein the input terminal of the waveform shaping unit is electrically connected to the output terminal of the comparator, and the output terminal of the waveform shaping unit serves as the output terminal of the fourth clock signal; The third switch has its first terminal electrically connected to the second terminal of the first switch, its control terminal serving as the third clock receiver, and its second terminal grounded. The fourth switch has its first terminal electrically connected to the second terminal of the first capacitor, its control terminal electrically connected to the control terminal of the third switch, and its second terminal grounded. The fifth switch has its first terminal electrically connected to the second terminal of the second switch, its control terminal electrically connected to the output terminal of the comparator, and its second terminal grounded. The second capacitor has its first terminal electrically connected to the second terminal of the second switch, and its second terminal grounded.

6. The clock switching circuit according to claim 5, characterized in that, The capacitance value of the first capacitor is less than the capacitance value of the second capacitor.

7. The clock switching circuit according to claim 5, characterized in that, The waveform shaping unit includes an edge trigger.

8. The clock switching circuit according to claim 5, characterized in that, The first capacitor and the second capacitor are variable capacitors.

9. A chip, characterized in that: Includes the clock switching circuit as described in any one of claims 1 to 8.

10. A terminal, characterized in that: Includes the clock switching circuit as described in any one of claims 1 to 8.

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