A high-precision MASH-type high-order noise shaping analog-to-digital converter

Abstract

The present invention provides a high-precision MASH type high-order noise shaping analog-to-digital converter, which uses DWA to implement first-order shaping of DAC capacitor mismatch in the first stage, performs second-order shaping on non-ideal effects in the second stage, processes the digital code of the second stage through digital noise elimination technology, and then combines it with the digital code of the first stage to obtain an overall output. The present invention achieves a fourth-order quantization noise shaping effect in two stages and completes mismatch error shaping; at the same time, the present invention reuses an operational amplifier to meet the requirements of two-stage residual amplification, and various non-ideal effects of the second stage can be shaped in the second order, with high shaping efficiency and precision. Since the second-stage circuit of the present invention is relatively insensitive to various non-ideal effects, the difficulty of circuit design can be reduced. The present invention can have a higher value of unit capacitance under the same area overhead, reducing capacitance mismatch. In addition, the present invention can work in four different modes and is suitable for applications with different precision requirements.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a high-precision MASH type high-order noise shaping analog-to-digital converter. Background Art

[0002] Analog-to-digital converters (ADCs), bridging the analog and digital worlds, play a crucial role. Their performance ultimately limits overall system performance. As integrated circuit feature sizes continue to shrink, successive approximation register (SAR) ADCs (SAR ADCs) are finding widespread use in medium-rate, medium-to-high-precision applications due to their simple structure, low power consumption, compact size, and ease of integration. To meet the demands for high-precision and low-power ADCs in applications such as precision instrumentation, medical equipment, and industrial imaging, the design of high-precision SAR ADCs is crucial. However, traditional SAR ADCs struggle to achieve high accuracy. Therefore, combining noise shaping techniques from delta-sigma ADCs with SAR ADCs overcomes SAR limitations in high-resolution applications. Non-sigma SAR ADCs (NS SAR ADCs) allow the use of lower-resolution DACs, relaxing comparator noise requirements and achieving both high resolution and high energy efficiency. Compared to traditional delta-sigma ADCs, NS SAR ADCs utilize a single DAC array for quantization and feedback, resulting in lower power consumption.

[0003] For charge redistribution SAR ADCs, the primary factor affecting linearity is capacitor matching. With today's nanometer-scale CMOS processes, matching becomes even more critical. To address the mismatch in the DAC capacitor array, Mismatch Error Shaping (MES) is used to reduce the requirements for the capacitor array. Traditional MES requires top-plate sampling, but the variable parasitic capacitance introduced by top-plate sampling degrades linearity. Similarly, shaping these errors along with quantization noise is a design challenge. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-precision MASH type high-order noise shaping analog-to-digital converter. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] The present invention provides a high-precision MASH type high-order noise shaping analog-to-digital converter, which has a differential symmetrical structure. The upper and lower symmetrical circuits of the differential symmetrical structure both include: a sampling switch, a first-stage split capacitor array, a second-stage capacitor array, and a DWA logic unit.

[0006] Among them, the upper plate of the first-stage split capacitor array and the upper plate of the second-stage capacitor array are connected together to access a sampling switch, and the other end of the sampling switch is connected to the first input signal VCM; the lower plate of the first-stage split capacitor array and the lower plate of the second-stage capacitor array are both connected to the signal selection input end;

[0007] The upper plates of the two symmetrical first-stage split capacitor arrays are connected via an NS module. The upper plate of each second-stage capacitor array is connected to an input of a comparator. The output of the comparator is connected to a SAR logic unit. The SAR logic unit is connected to each DWA logic unit.

[0008] The first-stage split capacitor array and the second-stage capacitor array are used to change the input signals connected to themselves under the control of the DWA logic unit or the SAR logic unit, so that the voltage signals of the upper and lower plates change and are fed back to the comparator, and the process of adjusting the input signal of the first-stage split capacitor array by the SAR logic unit and the DWA logic unit is re-executed according to the comparison result of the comparator. After the voltage of the lower plate remains unchanged, the amplified upper plate voltage is amplified and stored through the NS module, and is fed back to the first-stage split capacitor array and the second-stage capacitor array after the next sampling cycle is completed.

[0009] Optionally, the signal selection input terminal is used to input one of the second input signals controlled by the SAR logic or DWA logic unit or the third input signal VIN controlled by the sampling clock; the second input signal includes: the first input signal VCM, the first reference voltage signal VREFN and the second reference voltage signal VREFP.

[0010] Optionally, the first-stage split capacitor array and the second-stage capacitor array are used to change the input signal connected to themselves under the control of the DWA logic unit or the SAR logic unit, so that the voltage signals of the upper and lower plates change and are fed back to the comparator, and the SAR logic unit and the DWA logic unit are re-executed according to the comparison result of the comparator to adjust the input signal of the first-stage split capacitor array. After the lower plate voltage remains unchanged, the amplified upper plate voltage is amplified and stored by the NS module, and fed back to the first-stage split capacitor array and the second-stage capacitor array after the next sampling cycle is completed. The process includes:

[0011] The first-stage split capacitor array and the second-stage capacitor array are configured to execute a process in which the lower plate samples the third input signal VIN controlled by the sampling clock and the upper plate samples the first input signal VCM when the rising edge of the sampling clock arrives, and the sampling is terminated when the falling edge arrives, thereby obtaining two sampling signals;

[0012] The comparator is used to compare the two sampling signals and output the comparison result to the SAR logic unit;

[0013] The SAR logic unit is used to generate a logic signal based on the comparison result, control the lower plates of the first-stage split capacitor array and the second-stage capacitor array to connect to one of the second input signals, so as to change the voltage of the upper plates of the first-stage split capacitor array and the second-stage capacitor array, and perform the sampling, comparison, and control process until three comparisons are completed to obtain three digital codes and input them into the DWA logic unit;

[0014] The DWA logic unit is configured to convert the three digital codes into a control code for controlling the first-stage split capacitor array, and control the input signal of the first-stage split capacitor array according to the control code to change the voltage of the upper and lower plates of the first-stage split capacitor array;

[0015] The NS module is used to amplify and store the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and feed it back to the upper plate of the first-stage split capacitor array and the second-stage capacitor array after sampling in the next cycle.

[0016] Optionally, each first-level split capacitor array includes 7 unit capacitors with the same capacitance value, and the 7 capacitors are connected in parallel; each second-level capacitor array includes 5 capacitors, namely redundant capacitors, three binary capacitors and one weight capacitor, and the 5 capacitors are connected in parallel; the first-level split capacitor array and the upper plate connected to the second-level capacitor array are connected to an input end of the comparator and the input end of the NS module, and the output end of the NS module is connected to the first-level split capacitor array and the upper plate connected to the second-level capacitor array.

[0017] Optionally, the NS module includes an operational amplifier, 20 switches and 4 delay units, two switches in parallel are connected between each input terminal of the operational amplifier and the upper plate, and each output terminal of the operational amplifier is connected to two parallel paths; each path is divided into an upper path and a lower path, the upper path is composed of two series switches with a capacitor in series in the middle, and the lower path is composed of two series switches with a capacitor and a delay unit in series in the middle, and the output of each path is connected to the corresponding upper plate.

[0018] Optionally, the NS module is used to amplify and store the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and feed back the voltage signal to the upper plate of the first-stage split capacitor array and the second-stage capacitor array after the next cycle sampling, including:

[0019] The NS module is used to amplify the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and store the amplified voltage signal by the capacitors of the upper path and the lower path, and after sampling in the next cycle, feed back the voltage signals stored in the upper path and the lower path capacitors of the first path to the upper plate of the first-stage split capacitor array and the second-stage capacitor array; and, after three comparisons, feed back the voltage signals stored in the upper path and the lower path capacitors of the second path to the upper plate of the first-stage split capacitor array and the second-stage capacitor array.

[0020] The present invention provides a high-precision MASH type high-order noise shaping analog-to-digital converter, which uses DWA to implement first-order shaping of DAC capacitor mismatch in the first stage, performs second-order shaping on non-ideal effects in the second stage, processes the digital code of the second stage through digital noise elimination technology, and then combines it with the digital code of the first stage to obtain an overall output. The present invention achieves a fourth-order quantization noise shaping effect in two stages and completes mismatch error shaping; at the same time, the present invention reuses an operational amplifier to meet the requirements of two-stage residual amplification, and various non-ideal effects of the second stage can be shaped in the second order, with high shaping efficiency and precision. Since the second-stage circuit of the present invention is relatively insensitive to various non-ideal effects, the difficulty of circuit design can be reduced. The present invention can have a higher value of unit capacitance under the same area overhead. In addition, the present invention can work in four different modes and is suitable for applications with different precision requirements.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a high-precision MASH high-order noise shaping analog-to-digital converter provided by the present invention;

[0023] Figure 2 The overall timing diagram of a high-precision MASH type high-order noise shaping analog-to-digital converter provided by the present invention;

[0024] Figure 3a A schematic diagram of the ping-pong process of two-order integration is given using the first order as an example;

[0025] Figure 3b The overall signal flow diagram of a high-precision MASH type high-order noise shaping analog-to-digital converter provided by the present invention;

[0026] Figure 4 The signal flow diagram provided by the present invention takes the first level as an example;

[0027] Figure 5A comparison diagram of the MASH2-2 and MASH0-4 structures without capacitor mismatch;

[0028] Figure 6 A comparison diagram of the MASH2-2 and MASH0-4 structures with capacitor mismatch. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0030] like Figure 1 As shown, the present invention provides a high-precision MASH type high-order noise shaping analog-to-digital converter, which has a differential symmetrical structure. The upper and lower symmetrical circuits of the differential symmetrical structure both include: a sampling switch, a first-stage split capacitor array, a second-stage capacitor array, and a DWA logic unit.

[0031] Among them, the upper plate of the first-stage split capacitor array and the upper plate of the second-stage capacitor array are connected together to access a sampling switch, and the other end of the sampling switch is connected to the first input signal VCM; the lower plate of the first-stage split capacitor array and the lower plate of the second-stage capacitor array are both connected to the signal selection input end;

[0032] The upper plates of the two symmetrical first-stage split capacitor arrays are connected via an NS module. The upper plate of each second-stage capacitor array is connected to an input of a comparator. The output of the comparator is connected to a SAR logic unit. The SAR logic unit is connected to each DWA logic unit.

[0033] The first-stage split capacitor array and the second-stage capacitor array are used to change the input signals connected to themselves under the control of the DWA logic unit or the SAR logic unit, so that the voltage signals of the upper and lower plates change and are fed back to the comparator, and the process of adjusting the input signal of the first-stage split capacitor array by the SAR logic unit and the DWA logic unit is re-executed according to the comparison result of the comparator. After the voltage of the lower plate remains unchanged, it is amplified through the NS module, and the amplified upper plate voltage is stored and fed back to the first-stage split capacitor array and the second-stage capacitor array after the next sampling cycle is completed.

[0034] The present invention adopts VCM-based timing, and the lower plate sampling method greatly improves the influence of the variable parasitic capacitance of the upper plate on the linearity of the system. The overall structure is a 6-bit SAR ADC. The working process is to divide the SAR into two serial stages. The first stage realizes the quantization of the upper 3 bits. After the upper 3 bits are quantized, the data weighted average DWA method is adopted to use the digital logic circuit to re-switch the level of the lower plate to achieve the first-order shaping of the mismatch error of the upper 3 split capacitors. The advantage of the DWA method is that only one index is updated in each clock cycle; after completing the amplification of the first-stage residual signal, the second-stage quantization is carried out. The second stage is 4 bits, and the highest bit is redundant. After completing the quantization of the two stages, the digital codes of the two stages are output uniformly.

[0035] Among them, each first-level split capacitor array includes 7 unit capacitors with the same capacitance value, and the 7 capacitors are connected in parallel; each second-level capacitor array includes 5 capacitors, namely redundant capacitors, three binary capacitors and one weight capacitor, and the 5 capacitors are connected in parallel; the first-level split capacitor array and the upper plate connected to the second-level capacitor array are connected to an input end of the comparator and the input end of the NS module, and the output end of the NS module is connected to the first-level split capacitor array and the upper plate connected to the second-level capacitor array.

[0036] The NS module includes an operational amplifier, 20 switches, and four delay units. Two switches are connected in parallel between each input terminal of the operational amplifier and the upper plate, and each output terminal of the operational amplifier is connected to two parallel paths. Each path is divided into an upper path and a lower path. The upper path consists of two series switches connected in series with a capacitor in between, and the lower path consists of two series switches connected in series with a capacitor and a delay unit in between. The output of each path is connected to the corresponding upper plate. The signal selection input terminal is used to input one of the second input signals controlled by the SAR logic or DWA logic unit or a third input signal VIN controlled by the sampling clock. The second input signal includes: a first input signal VCM, a first reference voltage signal VREFN, and a second reference voltage signal VREFP.

[0037] refer to Figure 1 The upper path of the first path consists of S9, C3, and S7 in series, while the lower path consists of S10, a delay unit N1, C4, and S8 in series. Because the upper path lacks the delay function of the delay unit, the upper plate voltage of the previous cycle is fed back in each cycle, while the lower path feeds back the upper plate voltage of the cycle before that. The internal principles of the NS module will be described in detail later.

[0038] In the present invention, the first-stage split capacitor array and the connected second-stage capacitor array are collectively referred to as a DAC capacitor array.

[0039] refer to Figure 1, the present invention samples the external input signal, when Φ SH When the signal is high, sampling is performed. SH Sampling ends when the signal changes from high level 1 to low level 0. During sampling, the DAC top plate samples the VCM signal, while the bottom plate samples the input signal. Because the sampling clock of the bottom plate ends slightly later than the sampling clock of the top plate, the input signal information before the bottom plate sampling switch is turned off is stored in the top plate for subsequent quantization.

[0040] Figure 1 As shown in , the first-level split capacitor array includes seven capacitors, namely CS1p, CS2p to CS7p. The second-level capacitor array consists of 4 binary capacitors and one weighted capacitor. The ratio of these 12 capacitors is 8:8:8:8:8:8:8:8:4:2:1:1, C Rp C4p, C5p, and C6p are redundant capacitors that ensure the circuit has a certain degree of fault tolerance. When comparator offset, DAC settling error, operational amplifier gain error, and other issues affect the second-stage input signal, the redundant bits ensure that the input signal of the second-stage capacitor array does not exceed the quantization range, and at the same time ensure that the residual signal of the second-stage capacitor array does not exceed the input range after feedback. C4p, C5p, and C6p are binary capacitors of the second-stage capacitor array, and C dump It is a weighted capacitor and does not undergo conversion, that is, the level of its lower plate is directly fixed and does not change. The upper plate of the DAC capacitor array is directly connected to the input of the comparator. The 7-time asynchronous clock controls the comparator to output a 7-bit digital code. Each digital code obtained simultaneously controls the SAR logic to trigger the switching level of the lower plate of the DAC capacitor array. After each switch, the voltage of the upper plate will approach the VCM level at the time of sampling in a binary manner. At the same time, the upper plate is also connected to the input of the amplifier in the NS module through a switch. The two-stage amplification process of the amplifier in the NS module corresponds to two switches to control it respectively. The load of the amplifier is connected to the integrating capacitor, and the integrating capacitor stores the amplified residual voltage.

[0041] As an optional embodiment of the present invention, the first-stage split capacitor array and the second-stage capacitor array are used to change the input signal connected to themselves under the control of the DWA logic unit or the SAR logic unit, so that the voltage signals of the upper and lower plates change and are fed back to the comparator, and the process of re-executing the SAR logic unit and the DWA logic unit to adjust the input signal of the first-stage split capacitor array according to the comparison result of the comparator. After the lower plate voltage remains unchanged, the amplified upper plate voltage is amplified by the NS module, and the amplified upper plate voltage is stored and fed back to the first-stage split capacitor array and the second-stage capacitor array after the next sampling cycle is completed. The process includes:

[0042] The first-stage split capacitor array and the second-stage capacitor array are configured to execute a process in which the lower plate samples the third input signal VIN controlled by the sampling clock and the upper plate samples the first input signal VCM when the rising edge of the sampling clock arrives, and the sampling is terminated when the falling edge arrives, thereby obtaining two sampling signals;

[0043] The comparator is used to compare the two sampling signals and output the comparison result to the SAR logic unit;

[0044] The SAR logic unit is used to generate a logic signal based on the comparison result, control the lower plates of the first-stage split capacitor array and the second-stage capacitor array to connect to one of the second input signals, so as to change the voltage of the upper plates of the first-stage split capacitor array and the second-stage capacitor array, and perform the sampling, comparison, and control process until three comparisons are completed to obtain three digital codes and input them into the DWA logic unit;

[0045] The DWA logic unit is configured to convert the three digital codes into a control code for controlling the first-stage split capacitor array, and control the input signal of the first-stage split capacitor array according to the control code to change the voltage of the upper and lower plates of the first-stage split capacitor array;

[0046] The NS module is used to amplify and store the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and feed it back to the upper plate of the first-stage split capacitor array and the second-stage capacitor array after sampling in the next cycle.

[0047] It is worth noting that when the voltages of the upper and lower plates remain unchanged, the voltage of the upper plate is the residual voltage.

[0048] Among them, the NS module is used to amplify the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and store the amplified voltage signal by the capacitors of the upper path and the lower path, and after the next cycle sampling, feed back the voltage signals stored in the upper path and the lower path capacitors of the first path to the upper plate of the first-stage split capacitor array and the second-stage capacitor array; and, after three comparisons, feed back the voltage signals stored in the upper path and the lower path capacitors of the second path to the upper plate of the first-stage split capacitor array and the second-stage capacitor array.

[0049] The operation of the overall circuit includes seven stages, namely, first-stage noise shaping, first-stage quantization, DWA, first-stage residual amplification, second-stage noise shaping, second-stage quantization, and second-stage residual amplification.

[0050] like Figure 2 The Φ shown in the timing diagram NS1Timing, complete the first level of noise shaping, the residual voltage on C1 after N-1 cycle amplification and the residual voltage on C2 after N-2 cycle amplification are fed back to the upper plate of the DAC capacitor, and the integral capacitor and DAC capacitor share the charge to achieve the effect of second-order shaping; then quantize to obtain the digital code of the upper three bits, and these three digital codes are input into the DWA logic at the same time to convert the three-digit code into a 7-bit thermometer code. At the same time, each time the rotation is made, the high level is assigned to different unit capacitors in turn, and the nonlinear error caused by the mismatch of the split capacitors in the upper three bits is randomized, thereby suppressing harmonic distortion and improving the linearity of the system. The lower plates of the seven split capacitors in the upper three bits are reset to obtain the upper plate voltage after the DWA first-order shaping, and the linearity is improved. Then the residual of the upper three bits is amplified. When Φ NS2 When the clock reaches a high level, the second stage of noise shaping is performed. The principle and process are the same as the first stage, and the lower 4 bits of the output code are obtained. After that, the second stage of amplification is performed. Non-ideal factors such as errors in the second stage can be shaped by the first stage NTF.

[0051] Combine Figure 1 as well as Figure 3a , the present invention describes the internal principles of the NS module in detail. Figure 3a The following is a schematic diagram of the ping-pong process of two-order integration, taking the first order as an example. Figure 3a The capacitors C1a and C1b correspond to Figure 1 The C3 capacitor group in the figure, capacitors C2a, C2b and C2c correspond to Figure 1 The C4 capacitor group in the Figure 3a Middle switch SN1 corresponds Figure 1 S9, switch SN2 corresponds to Figure 1 Middle S10; Figure 3a The switch group S1a and switch group S1b correspond to Figure 1 Middle S7 switch group; Figure 3a The switches S2a, S2b and S2c correspond to Figure 1 Middle S8 switch group. Figure 3aThe S1a switch group corresponds to switches S1aA and S1aB; the S1b switch group corresponds to switches S1bA and S1bB; the S2a switch group corresponds to switches S2aA, S2aB, and S2aC; the S2b switch group corresponds to switches S2bA, S2bB, and S2bC; and the S2c switch group corresponds to switches S2cA, S2cB, and S2cC. For the two-stage amplification process, the present invention reuses the same gain-adjustable operational amplifier. Based on the relationship between the integration capacitors of the two stages and the DAC capacitance, appropriate gain is required for lossless integration. Therefore, the two stages have different amplification factors, and the amplifier gain is adjustable, achieved by adjusting the op amp load resistor. The load resistors during the amplification period are all integrating capacitors. The first-order integrating capacitors include two groups, C1a and C1b. In the Nth cycle, capacitor C1a participates in amplification, capacitor C1b stores the amplification result of the N-1th cycle and participates in integration. In the N+1th cycle, capacitor C1a participates in integration, and capacitor C1b participates in amplification. The second-order integrating capacitors include three groups, C2a, C2b, and C2c. In the Nth cycle, capacitor C2c amplifies, capacitor C2b storing the residual signal of the N-1th cycle remains unchanged, and capacitor C2a storing the residual signal of the N-2th cycle participates in integration. In the N+1th cycle, capacitor C2c remains unchanged, capacitor C2b participates in integration, and capacitor C2a participates in amplification. In the N+2th cycle, capacitor C2a remains unchanged, capacitor C2c participates in integration, and capacitor C2b participates in amplification. And so on, the three cycles are alternated.

[0052] The signal flow diagram of the overall circuit is given below, as Figure 3b As shown in the figure, after the first-stage split capacitor array is quantized, the conversion residual is obtained on the DAC upper plate, which includes errors from the DAC capacitor nonlinearity and mismatch. At this time, the linearity of the system is poor. In order to reduce the impact of capacitor mismatch, a 2-2MASH architecture NS SAR ADC is adopted. At the same time, the first-stage split capacitor array uses DWA technology to perform first-order mismatch error shaping, and the second-stage non-ideal factors achieve second-order shaping. According to the Mason formula, it can be obtained:

[0053]

[0054] In the above formula, V in represents the input signal, Q1 represents the first-stage quantization noise, ε1 represents other non-ideal factors of the first stage, H1 represents the first-stage transfer function, D1 represents the three-bit output code of the first stage, Q2 represents the second-stage quantization noise, ε2 represents other non-ideal factors of the second stage, H2 represents the second-stage transfer function, D2 represents the four-bit output code of the second stage, and NTF1 represents the noise transfer function of the first stage.

[0055] The output code D of the SAR logic unit can be obtained as follows

[0056] D(z)=Vin(z)+ε1+Q2·NTF1·NTF2+NTF1·ε2

[0057] From the above output codes it can be seen that the non-ideal effects of the second stage are shaped by the second order.

[0058] Figure 4 The specific signal flow diagram of the first level is given as an example, and the specific implementation of NTF is given, where A CS Represents the attenuation coefficient of the signal, G is the gain of the amplifier, in order to ensure that the residual signal can achieve lossless integration, satisfy A CS G = 1. The output code expression, STF and NTF can be obtained according to the flow chart.

[0059] Dout(z)=(1-3A CS )·Vin(z)+[1-G·A CS (2z -1 -z -2 )]·Q(z)

[0060] STF=1-3A CS

[0061] NTF=1-G·A CS (2z -1 -z -2 )

[0062] In the present invention, the noise shaping scheme of MASH 2-2 is adopted, and the linearity degradation caused by variable parasitic capacitance is reduced by the lower plate sampling method. The traditional quantization noise is shaped to achieve 4th order. The same gain-adjustable operational amplifier is reused in two stages to achieve lossless integration. The first stage's upper three-bit split capacitor mismatch error is shaped to achieve first order by the DWA method. The second stage's DAC capacitor array mismatch and other non-ideal factors are shaped to achieve second order by NTF1. That is, the non-ideal effects of the second stage can be shaped by the first stage. Therefore, when the gain-adjustable operational amplifier is applied to the second stage, the design requirements are relaxed and there is more design space. The overall circuit is 6 bits plus one redundant bit, and the hardware overhead is low. At the same time, some timing switches are introduced, and the control circuit can operate in four modes: Nyquist mode, MASH2-0, MASH0-2 and MASH2-2, achieving adjustable precision and broadening the application scenarios.

[0063] The present invention provides a high-precision MASH-type high-order noise-shaping analog-to-digital converter. In the sampling phase, the upper plate of a DAC capacitor array samples a VCM signal, while the lower plate samples an input signal. After sampling, the input signal information is stored in the upper plate. A first-stage noise shaping is then performed, followed by quantization of the upper three bits. During this process, an asynchronous clock controls the operation of a comparator, thereby switching the lower plate of the capacitor array. The resulting three-digit digital code D1 is reset by controlling a DWA operation to reset the lower plate of the first-stage split capacitor array. The first-stage residual amplification is then performed. A second-stage noise shaping and lower four-bit quantization are then performed. After the second-stage quantization is completed, a four-bit output code D2 is obtained. A second-stage residual signal amplification is performed, and digital noise cancellation technology is then used to address the problem of noise leakage in the first stage. Finally, the two-stage output codes D1 and D2 are combined and output simultaneously.

[0064] refer to Figure 5 , Figure 5 In the case of not introducing a capacitor mismatch error of 1‰, the MASH2-2 structure achieves an SNR of 114.912dB and an ENOB of 18.796bit, while the MASH0-4 structure achieves an SNR of 113.518dB and an ENOB of 18.564bit. Figure 6 , Figure 6 When a capacitor mismatch error of 1‰ is introduced, the MASH2-2 structure achieves an SNR of 110.372dB and an ENOB of 18.042bit, while the MASH0-4 structure achieves an SNR of 89.246dB and an ENOB of 14.533bit. This shows that the high-precision MASH-type high-order noise shaping analog-to-digital converter provided by the present invention, combined with the mismatch error shaping method, can achieve higher linearity and accuracy when compared with the MASH0-4 structure that can achieve the same quantization noise shaping accuracy, both when no capacitor mismatch error is introduced and when a capacitor mismatch error is introduced.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0066] Although the present application is described herein with reference to various embodiments, those skilled in the art will be able to understand and implement other variations of the disclosed embodiments in practicing the claimed application by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0067] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-precision MASH type high-order noise shaping analog-to-digital converter, characterized in that: The high-precision MASH type high-order noise shaping analog-to-digital converter has a differential symmetrical structure, and the upper and lower symmetrical circuits of the differential symmetrical structure both include: a sampling switch, a first-stage split capacitor array, a second-stage capacitor array, and a DWA logic unit. The upper plate of the first-stage split capacitor array and the upper plate of the second-stage capacitor array are connected together and connected to a sampling switch, and the other end of the sampling switch is connected to the first input signal (VCM); the lower plate of the first-stage split capacitor array and the lower plate of the second-stage capacitor array are both connected to the signal selection input end; The upper plates of the two symmetrical first-stage split capacitor arrays are connected via an NS module. The upper plate of each second-stage capacitor array is connected to an input of a comparator. The output of the comparator is connected to a SAR logic unit. The SAR logic unit is connected to each DWA logic unit. The first-stage split capacitor array and the second-stage capacitor array are configured to change their input signals under the control of the DWA logic unit or the SAR logic unit, so that the voltage signals of the upper and lower plates change and are fed back to the comparator. Based on the comparison result of the comparator, the SAR logic unit and the DWA logic unit jointly adjust the input signal of the first-stage split capacitor array. After the lower plate voltage remains unchanged, the amplified upper plate voltage is amplified and stored by the NS module, and fed back to the first-stage split capacitor array and the second-stage capacitor array after the next sampling cycle is completed. The signal selection input terminal is used to input one of the second input signals controlled by the SAR logic or the DWA logic unit or the third input signal (VIN) controlled by the sampling clock; the second input signal includes: a first input signal (VCM), a first reference voltage signal (VREFN) and a second reference voltage signal (VREFP); Each first-level split capacitor array includes 7 unit capacitors with the same capacitance value, and the 7 capacitors are connected in parallel; each second-level capacitor array includes 5 capacitors, namely redundant capacitors, three binary capacitors and one weight capacitor, and the 5 capacitors are connected in parallel; the first-level split capacitor array and the upper plate connected to the second-level capacitor array are connected to an input end of the comparator and the input end of the NS module, and the output end of the NS module is connected to the first-level split capacitor array and the upper plate connected to the second-level capacitor array.

2. The high-precision MASH type high-order noise shaping analog-to-digital converter according to claim 1, characterized in that: The first-stage split capacitor array and the second-stage capacitor array are used to change their own input signals under the control of the DWA logic unit or the SAR logic unit, so that the voltage signals of the upper and lower plates change and are fed back to the comparator, and the SAR logic unit and the DWA logic unit are re-executed according to the comparison result of the comparator to adjust the input signal of the first-stage split capacitor array. After the lower plate voltage remains unchanged, the amplified upper plate voltage is amplified and stored through the NS module, and is fed back to the first-stage split capacitor array and the second-stage capacitor array after the next sampling cycle is completed. The process includes: The first-stage split capacitor array and the second-stage capacitor array are configured to execute a process in which the lower plate samples the third input signal (VIN) controlled by the sampling clock and the upper plate samples the first input signal (VCM) when the rising edge of the sampling clock arrives, and the sampling is terminated when the falling edge arrives, thereby obtaining two sampling signals; The comparator is used to compare the two sampling signals and output the comparison result to the SAR logic unit; The SAR logic unit is used to generate a logic signal based on the comparison result, control the lower plates of the first-stage split capacitor array and the second-stage capacitor array to connect to one of the second input signals, so as to change the voltage of the upper plates of the first-stage split capacitor array and the second-stage capacitor array, and perform the sampling, comparison, and control process until three comparisons are completed to obtain three digital codes and input them into the DWA logic unit; The DWA logic unit is configured to convert the three digital codes into a control code for controlling the first-stage split capacitor array, and control the input signal of the first-stage split capacitor array according to the control code to change the voltage of the upper and lower plates of the first-stage split capacitor array; The NS module is used to amplify and store the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and feed it back to the upper plate of the first-stage split capacitor array and the second-stage capacitor array after sampling in the next cycle.

3. The high-precision MASH type high-order noise shaping analog-to-digital converter according to claim 2, characterized in that: The NS module includes an operational amplifier, 20 switches and 4 delay units. Two switches are connected in parallel between each input terminal of the operational amplifier and the upper plate, and each output terminal of the operational amplifier is connected to two parallel paths; each path is divided into an upper path and a lower path. The upper path is composed of two series switches with a capacitor connected in series in the middle, and the lower path is composed of two series switches with a capacitor and a delay unit connected in series in the middle. The output of each path is connected to the corresponding upper plate.

4. The high-precision MASH type high-order noise shaping analog-to-digital converter according to claim 3, characterized in that: The NS module is used to amplify and store the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and feed back the voltage signal to the upper plate of the first-stage split capacitor array and the second-stage capacitor array after the next cycle sampling, including: The NS module is used to amplify the upper plate voltage signal by its own timing control when the voltage of the upper and lower plates of the first-stage split capacitor array does not change, and store the amplified voltage signal by the capacitors of the upper path and the lower path, and after sampling in the next cycle, feed back the voltage signals stored in the upper path and the lower path capacitors of the first path to the upper plate of the first-stage split capacitor array and the second-stage capacitor array; and, after three comparisons, feed back the voltage signals stored in the upper path and the lower path capacitors of the second path to the upper plate of the first-stage split capacitor array and the second-stage capacitor array.

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