Removing artifacts from an image

Abstract

An inspection tool includes: an imaging system configured to image a portion of a semiconductor substrate; an image analysis system configured to: obtain an image of a structure on the semiconductor substrate from the imaging system; encode the image of the structure into a latent space to form a first code; subtract an artifact vector representing artifacts in the image from the code to form a second code; and decode the second code to obtain a decoded image.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to European Patent Application No. 20167449.6, filed on 1 April 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to methods for processing images of semiconductor substrates, and in particular to methods for manufacturing devices using photolithography apparatus. Background Technology

[0004] A photolithography apparatus is a machine that applies a desired pattern onto a substrate, typically onto a target portion of the substrate. Photolithography apparatuses can be used, for example, in the fabrication of integrated circuits (ICs). In this case, a patterning apparatus, or what may be called a mask or photomask, can be used to generate a circuit pattern that will be formed on a separate layer of the IC. This pattern can then be transferred to a target portion (e.g., a portion of a die, a die, or several dies) on a substrate (e.g., a silicon wafer). The transfer of the pattern is typically achieved via imaging on a layer of a radiation-sensitive material (resist) disposed on the substrate. Generally, a single substrate will contain a network of continuously patterned adjacent target portions.

[0005] Most semiconductor devices require the formation of multiple patterned layers and their transfer onto a substrate. For proper device operation, there are typically limitations on the tolerable errors in edge positioning, quantified as edge placement error, or EPE. EPE can arise from errors known as overlay in the relative positioning of successive layers or from errors in the size of the feature (specifically, the critical dimension or CD). As lithography techniques continue to strive to reduce the size of features that can be formed (shrink), the limitations on EPE become even more stringent.

[0006] Overlap can be caused by a variety of factors in the photolithography process, such as errors in substrate positioning during exposure and aberrations in the projected image. Overlap can also occur in process steps such as etching used to transfer patterns onto the substrate. Some of these process steps introduce stress within the substrate, leading to localized or overall deformation. Forming three-dimensional structures on the substrate, such as those required for recently developed memory types and MEMS, can also result in significant substrate deformation. CD variations can also originate from a variety of causes, including dose or focus errors. Summary of the Invention

[0007] The purpose of this disclosure is to achieve more accurate measurement, for example, in the manufacturing process of photolithography equipment.

[0008] According to an embodiment, a method for removing artifacts from an image of a semiconductor substrate is provided, the method comprising:

[0009] Obtain images of structures on semiconductor substrates;

[0010] The image of the structure is encoded into the latent space, thus forming the first code;

[0011] The second code is formed by subtracting the artifact vector representing artifacts in the image from the original code; and

[0012] The second encoding is decoded to obtain the decoded image.

[0013] According to an embodiment, an inspection tool is provided, comprising: an imaging system configured to image a portion of a semiconductor substrate; and an image analysis system configured to:

[0014] Obtain an image of the structure on the semiconductor substrate from the imaging system;

[0015] The image of the structure is encoded into the latent space, thus forming the first code;

[0016] Subtract the artifact vector representing the artifacts in the image from the encoding to form the second encoding; and

[0017] The second encoding is decoded to obtain the decoded image.

[0018] A method for manufacturing a semiconductor substrate, the method comprising the following steps:

[0019] To manufacture at least a portion of a semiconductor substrate;

[0020] Obtain images of structures on semiconductor substrates;

[0021] The image of the structure is encoded into the latent space, thus forming the first code;

[0022] The second code is formed by subtracting the artifact vector representing the artifacts in the image from the code;

[0023] Decode the second encoding to obtain the decoded image;

[0024] Analyze and decode the image to obtain image metrics; and

[0025] Compare the metric to the target metric and take remedial measures when the metric does not meet the target metric. Attached Figure Description

[0026] Embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0027] Figure 1It describes a production facility where photolithography equipment, along with other equipment, forms semiconductor devices;

[0028] Figure 2A and Figure 2B Images depicting semiconductor substrates exhibiting varying levels of artifacts;

[0029] Figure 3A and Figure 3B An image of a semiconductor substrate is depicted, and how artifacts present therein can lead to measurement errors is shown.

[0030] Figure 4A and Figure 4B A graph is shown illustrating how increasing the number of frames used in SEM imaging affects the measured CD.

[0031] Figure 5 A method for removing artifacts according to an embodiment is described;

[0032] Figure 6 This is a flowchart depicting a method for removing artifacts according to an embodiment;

[0033] Figure 7 It describes the use of determining the purpose of Figure 6 The flowchart of the artifact vector method shown is presented.

[0034] Figure 8 It describes the use of determining the purpose of Figure 7 The flowchart illustrates the method for artifact intensity determination.

[0035] Figure 9 It is a graph illustrating the latent space and plotting the artifact vectors on it; and

[0036] Figure 10A and Figure 10B Images of semiconductor substrates with artifacts present and those with artifacts removed using the methods of this disclosure are depicted respectively. Detailed Implementation

[0037] Electronic devices consist of circuits typically formed on a piece of silicon called a substrate, which can be referred to as a semiconductor substrate. Of course, any other suitable material can be used for the substrate. Many circuits can be formed together on the same piece of silicon and are called integrated circuits or ICs. The size of these circuits has been significantly reduced, allowing more circuitry to be mounted on the substrate. For example, the IC chip in a smartphone can be represented by a scaled-down image. Figure 1 It is small, but can contain more than 2 billion transistors, each less than 1 / 1000 the size of a human hair.

[0038] Manufacturing these extremely small ICs is a complex, time-consuming, and expensive process, typically involving hundreds of individual steps. Even an error in a single step can result in a defective IC that renders it useless. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs manufactured in the process; that is, to improve the overall yield of the process.

[0039] A key component of improving yield is monitoring the chip manufacturing process to ensure it is producing a sufficient number of functional integrated circuits. One way to monitor this process is to inspect the chip's circuit structure at various stages of its formation. This can be done using scanning electron microscopy (SEM), optical inspection systems, and the like. Such systems can be used to image these structures, essentially taking "photographs" of the wafer structure, and SEMs are capable of imaging even the smallest components within these structures. This image can be used to determine if the structure is correctly formed in the correct location. If a defect is found, the process can be adjusted, making it less likely for the defect to recur.

[0040] To control errors in photolithography processes, such as errors in the relative positions of features in different layers (called overlap) and feature dimensions (called CD variation), it is necessary to measure these errors before corrections can be applied, such as by using scanning electron microscopy (SEM), optical inspection systems, etc. When using SEM or other inspection systems, an image of the substrate is typically obtained, and the dimensions of features on the substrate are measured from the image. This allows, for example, the determination of CD variation or EPE. However, images obtained by imaging techniques often contain artifacts that can negatively impact the measurement of features therein. For example, substrate charging can occur when using SEM. This charging can be very noticeable in the image of the substrate and can cause blurring of features thereon. As a result, feature measurements may not be perfectly accurate, and charging can introduce errors into the measurement. This type of error is less desirable given the small tolerances in feature measurements on such substrates. Other artifacts that may be present in the substrate image and thus contribute to errors in feature measurement on the substrate include noise and SEM-induced resist shrinkage. Novel methods for removing artifacts or other unwanted image elements are disclosed below, enabling more accurate measurement of features on the substrate.

[0041] Some methods disclosed herein process images of semiconductor substrates that may contain artifacts by encoding the image into a latent space, removing artifacts from the latent space, and decoding the encoding to reconstruct the artifact-removed image. This advantageously produces an image from which artifacts have been removed, which can then be further analyzed to determine measurements of image features. Measurements of the image from which artifacts have been removed will be more accurate. This improved accuracy can ensure appropriate actions are taken in the manufacturing process, potentially maximizing process yield. Compared to the dimension of the input space, i.e., the original image, the latent space has a lower dimension, making artifact removal easier. Furthermore, the inherent descriptive structure of the latent space makes it easier to identify artifact-specific fingerprints in the latent space compared to identifying such artifacts in the input space.

[0042] Before describing the embodiments in detail, it is helpful to present example environments in which the techniques disclosed herein can be implemented.

[0043] Figure 1 The illustration depicts a typical layout of a semiconductor manufacturing facility. A photolithography apparatus 100 applies a desired pattern onto a substrate. Photolithography apparatuses are used, for example, in the manufacture of integrated circuits (ICs). In this case, a patterning apparatus MA, or what is referred to as a mask or photomask, includes a circuit pattern of features (often referred to as "product features") to be formed on a separate layer of the IC. This pattern is transferred via exposure 104 on a radiation-sensitive material (etch-resistant) layer disposed on the substrate to a target portion (e.g., including portions, one or more dies) on the substrate 'W' (e.g., a silicon wafer). Typically, a single substrate will contain a network of continuously patterned adjacent target portions.

[0044] Known photolithography apparatuses irradiate each target portion by irradiating a patterning device, simultaneously positioning the target portion of the substrate at the image position of the patterning device. The irradiated target portion of the substrate is called the "exposure field," or simply the "field." The field layout on the substrate is typically a network of adjacent rectangles or other shapes aligned according to a Cartesian two-dimensional coordinate system (e.g., aligned along the X and Y axes, which are orthogonal to each other).

[0045] The requirement for photolithography apparatus is to accurately replicate the desired pattern onto the substrate. The location and size of the applied product features must be within certain tolerances. Positional errors can lead to overlap errors (commonly referred to as "overlap"). Overlap is the error in placing a first product feature within a first layer relative to a second product feature within a second layer. Photolithography apparatus reduces overlap errors by precisely aligning each wafer with a reference before patterning. This is done by measuring the location of alignment marks applied to the substrate. Based on the alignment measurements, the substrate position is controlled during the patterning process to prevent overlap errors that exceed tolerances. Alignment marks are typically created as part of the product image, thus forming a reference for measuring overlap. Alternatively, alignment marks from previously formed layers can be used.

[0046] When the applied dose associated with exposure 104 is outside specifications, critical dimension (CD) errors in the product features may occur. Therefore, the lithography apparatus 100 must be able to accurately control the radiation dose applied to the substrate. Exposure 104 is controlled by a measuring tool 102 integrated into the lithography apparatus 100. CD errors may also occur when the substrate is not correctly positioned relative to the focal plane associated with the patterned image. Focal position errors are typically related to the non-planarity of the substrate surface. The lithography apparatus reduces these focal position errors by measuring the substrate surface topography using a level sensor before patterning. Substrate height correction is applied during subsequent patterning to ensure that the patterning equipment is correctly imaged (focused) onto the substrate.

[0047] To verify overlap and CD errors associated with the photolithography process, the patterned substrate is examined using metrology apparatus 140. Common examples of metrology apparatuses are scatterometers and scanning electron microscopes. Scatterometers typically measure the characteristics of dedicated metrology targets. Besides being generally larger to allow for precise measurements, these metrology targets are representative of product features. Scatterometers measure overlap by detecting asymmetry in the diffraction pattern associated with the overlap metrology target. Critical dimensions are measured by analyzing the diffraction pattern associated with the CD metrology target. The CD metrology target is used to measure the results of the most recently exposed layer. The overlap target is used to measure the difference between the positions of the previous and most recent layers. Electron beam-based inspection tools, such as scanning electron microscopes (SEM), may be well-suited for measuring small overlap and CD values.

[0048] Within a semiconductor manufacturing facility, lithography apparatus 100 and metrology apparatus 140 form part of a "lithography unit" or "lithography cluster." The lithography cluster also includes a coating apparatus 108 for applying photoresist to a substrate W, a baking apparatus 110, a developing apparatus 112 for developing an exposed pattern into a physical resist pattern, an etching station 122, an apparatus 124 for performing a post-etch annealing step, and possible further processing apparatus 126, etc. The metrology apparatus is configured to inspect the substrate after development by the developing apparatus 112 or after further processing (e.g., etching at the etching station 122). The various apparatuses within the lithography unit are controlled by a supervisory control system (SCS), which issues control signals 166 to control the lithography apparatus via a lithography apparatus control unit (LACU) 106 to execute formulation R. The SCS allows operation of different apparatuses to provide maximum throughput and product yield. An important control mechanism is the feedback 146 from the metrology apparatus 140 to the various apparatuses (via the SCS), particularly to the lithography apparatus 100. Based on the characteristics of metrological feedback, corrective measures are determined to improve the processing quality of subsequent substrates. The SCS can be one or more computers, which may or may not communicate. Recipe R can be implemented as one recipe or multiple independent recipes. For example, a recipe for a process step such as etching may be completely independent of a recipe used to check the results of that process step (e.g., etching). For example, two or more recipes for a single step can be correlated to adjust one recipe to take into account the results of another recipe's execution on the same or different substrates.

[0049] The performance of lithography apparatuses is typically controlled and calibrated using methods such as Advanced Process Control (APC), as described, for example, in US2012008127A1. APC techniques utilize measurements of metrological targets applied to the substrate. The Manufacturing Execution System (MES) schedules the APC measurements and transmits the results to a data processing unit. The data processing unit converts the characteristics of the measurement data into a recipe that includes instructions for the lithography apparatus. This approach is highly effective in suppressing drift phenomena associated with lithography apparatuses.

[0050] Processing metrology data into corrective actions performed by processing devices is crucial for semiconductor manufacturing. In addition to metrology data, the characteristics of individual patterning equipment, substrates, processing devices, and other contextual data may be needed to further optimize the manufacturing process. The framework for using available metrology and contextual data to optimize the lithography process holistically is often referred to as part of holistic lithography. For example, contextual data related to CD errors on a mask can be used to control various devices (lithography apparatus, etching station) so that these CD errors do not affect the yield of the manufacturing process. Subsequent metrology data can be used to verify the effectiveness of the control strategy and to determine further corrective actions.

[0051] To qualify the process window, separate CD and overlap measurements are performed using one or more existing tools and combined into an edge placement error (EPE) budget. Typically, one metrology step may be performed after development (ADI) and another after etching (AEI), and there are inherent difficulties in calibrating two such different measurements to give equivalent results.

[0052] EPE (Extended Physical Expansion) is crucial for ensuring the proper functioning of semiconductor devices; for example, it can affect the availability of sufficient electrical contacts at the back end of a circuit module. This makes EPE measurements invaluable for ensuring that the process window accommodates a sufficient EPE budget and for controlling the process to remain within the window.

[0053] Figure 2A and Figure 2B Examples of SEM images with different noise levels are shown, indicating the presence of an artifact of an exemplary type. The two images were taken at two different locations on a semiconductor substrate, where it is assumed that these locations have the same structure. Figure 2A The image shown is larger than Figure 2B The image shown has more noise. The increased noise level results in... Figure 2A The contrast ratio of the image shown Figure 2B The image difference shown, Figure 2B The images in the image have relatively little noise. Noise sources in SEM images can be contributed by many different factors, including: primary electron noise from electrons in the SEM gun, secondary electron noise from electrons scattered from the sample, and detector noise due to dark current noise in the detector. Detector noise can also include contributions from signal amplification. As mentioned earlier, the presence of artifacts, in this case noise, can lead to errors in structural measurements in the image. Figure 2A and Figure 2B In the example shown, noise in the image may cause the line to be measured as wider than it actually is.

[0054] Figure 3A and Figure 3B An example of a SEM image showing SEM-induced charge artifacts is shown. Figure 3A In the image, SEM signal 200 is shown as an overlay SEM image. For example... Figure 3A As can be seen, the SEM signal 200 is asymmetrical within and immediately adjacent to slot 202. Since slot 202 is known to be symmetrical, this asymmetry is attributed to the substrate charge induced by the SEM. Nevertheless, due to the asymmetry in the image, it is difficult to accurately measure the features in the image. Figure 3BThese are SEM images used for tip-to-line measurements. Due to the induced charge in SEMs, such measurements are known to be affected by a 2nm scale. Since the dimensions of structures (i.e., features) on semiconductor substrates are typically very small, on the order of tens of nanometers, a 2nm error represents a significant portion of the measurement size.

[0055] Figure 4A and Figure 4B The graphs show two different examples where the resist line spacing CD changes with the increase of the average number of SEM frames used to obtain the CD measurement. Figure 4A The CD measurements for two lines are shown, each made of a different photoresist. Figure 4B The CD measurements for two trenches, each formed with a different photoresist, are shown. Exponential lines fit the two sets of data in each plot. Figure 4A and Figure 4B As shown in both examples, CD decreases with increasing average frame rate. However, CD varies considerably, for example, in... Figure 4A The wavelength drops from approximately 67.5 nm to 60 / 63 nm. This is a relatively large difference, which could cause problems when measuring from images of the substrate.

[0056] The method according to this disclosure aims to solve the above-mentioned problems and to be able to measure the structure on the substrate more accurately. Figure 5 A method for removing artifacts from an image 300 on a semiconductor substrate is illustrated schematically. In the first step, an image 300 of the structure on the semiconductor substrate is obtained. This can be performed, for example, by SEM or any other suitable method. The image 300 is then encoded 302 into a latent space 304 to form a first encoding. While in the latent space 304, artifact vectors representing artifacts in the image 300 are subtracted from the first encoding to form a second encoding. For example, the artifact vectors may represent charge-induced artifacts in the image. The second encoding is decoded 306 to obtain a decoded image 308. By removing the artifact vectors from the latent space 304, the decoded image 308 will no longer contain artifacts, or at least contain a reduced amount of artifacts. Therefore, with artifact removal, measurements can be made on the structure in the decoded image 308. These measurements can therefore be unaffected by artifacts in the original image 300.

[0057] The above steps can be performed by pre-training a variational autoencoder network, including an encoder and a decoder. Training the autoencoder network, i.e., optimizing the weights of the encoder and decoder, can be achieved by encoding and decoding training images to obtain an output image that is as close as possible to the input image. The weights can be adjusted accordingly to achieve this. This training can be performed using multiple training images, preferably a large number of images, containing varying levels of artifacts. For example, training images can be obtained using SEM, or images can be generated by combining different images.

[0058] The above about Figure 5 The exemplary methods described are also Figure 6 The process is described in the form of a flowchart. In step S1, an image of the structure on the semiconductor substrate is obtained. Upon obtaining the image, it is encoded into a latent space in step S2 to form a first code. If the image is represented as x', the first code is given by the following formula:

[0059] z' = encoder(x') (1)

[0060] Encoding an image can bring a high-dimensional image into a descriptive low-dimensional latent space. In forming the first code, the artifact vector represented by αu is subtracted in step S3 to form the second code z". This is mathematically represented as:

[0061] z”=z'-αu (2)

[0062] After removing the artifact vectors, the second encoding z” is then decoded in step S4 to provide the decoded image x”. This is mathematically represented as:

[0063] x”=decoder(z”)=decoder(encoder(x’)-αu) (3)

[0064] Therefore, the decoded image x” removes artifacts from it.

[0065] Figure 7A method for determining artifact vectors is described, which is used in step S3 as described above. According to this method, in step S5, multiple training images of semiconductor substrates are encoded into a latent space. The multiple training images can include any suitable images. For example, the multiple training images can include multiple images of the same semiconductor substrate, such as images of different locations on the same semiconductor substrate or images of different semiconductor substrates. The multiple images can include at least two sets of images, a first set in which artifacts of a first level are present, and a second set in which artifacts of a higher second level are present. For example, the first set of images may contain a relatively small amount of SEM induced charge, while the second set of images may contain a relatively large amount of SEM induced charge. The number of images in each set does not need to be large. This will be further described with reference to the following equation. The first set of images can be represented by (X... +1 The second set of images can be represented as (X). +2 The average code for each group is then determined using the following equation:

[0066] z +1 = E[encoder(x)], x∈X +1 (4)

[0067] z +2 = E[encoder(x)], x∈X +2 (5)

[0068] Here, E is the expectation operator.

[0069] When determining the average encoding for each training image in each set, step S6 is performed, where the artifact orientation in the latent space is determined. This can be achieved by normalizing the average encoding of the first set of images by subtracting the average encoding of the second set of images. Therefore, the artifact orientation is a unit-length vector u, given by the following equation:

[0070]

[0071] In step S7, the artifact intensity is determined, and in step S8, the artifact intensity and artifact direction are multiplied to give the artifact vector. Then, as described above, it can be... Figure 6 The method shown uses this artifact vector.

[0072] Figure 8 An exemplary method for determining artifact intensity is described. The process is repeated for a series of different test artifact intensity values. Figure 8The method shown is as follows. For each test artifact intensity value, the following method is performed. In step S9, the average encoding in the latent space of multiple training images is determined. With the average encoding for each image already determined, in step S10, the product of the artifact direction and the test artifact intensity value is subtracted from the average encoding of the multiple training images. This yields an adjusted encoding where the "test" artifact vector is subtracted. The adjusted encoding is then decoded in step S11 to provide an adjusted image. The above process is repeated for each value within the range of test artifact intensity values. To determine which test artifact intensity value most closely represents the actual artifact intensity in the image, the adjusted image is analyzed and the artifact intensity is determined as the test artifact intensity value of the adjusted image corresponding to the optimized image. The analyzed and optimized images may depend on many factors, specifically the type of artifact to be removed.

[0073] In an exemplary case of removing SEM charge-induced artifacts, if the measured geometry is symmetrical, the optimized image can be one with maximum symmetry. Taking the removal of SEM charge-induced artifacts as an example, in... Figure 8 The artifact intensity determined in the method shown can correspond to the charge intensity. In this case, for ease of use... Figure 8 The method shown concludes with optimization, where multiple training images can be selected for use in the process, including images with symmetrical geometry. By using such images, the symmetry in the final adjusted images can be sought during optimization to determine the test artifact intensity, which represents the actual artifact intensity. A set of training images with symmetrical geometry can be represented by X. sym Indicated. For this set of images, X sym This can thus form Figure 8 The method allows for the analysis of the adjusted symmetry. Symmetry search can be effectively performed by searching along the charge-sensitive direction Δz, maximizing the symmetry of the decoded image. Figure 8 The steps of the method shown, and the optimization for determining the artifact intensity that maximizes the symmetry of the adjusted image, are mathematically represented by the following equation, where α is the artifact intensity:

[0074]

[0075] In the case of SEM charge-induced artifacts, the reason for performing the above optimization based on symmetry is that charging introduces asymmetry into the image of other symmetrical patterns, which is often present on semiconductor substrates. Therefore, by minimizing the asymmetry, for example, finding the artifact intensity that provides maximum symmetry during removal, it is possible to find the potential shift length in the space that minimizes charging. These steps are helpful because it is difficult to obtain a clean image without charging.

[0076] The optimization performed above to maximize symmetry is merely one example of the type of optimization that can be performed to determine the intensity of artifacts, and it is particularly suitable for determining the intensity of SEM charge-induced artifacts. Any other suitable optimization can be performed.

[0077] Artifacts may be at least partially caused by noise in the image of the semiconductor substrate. In this case, the same process as described above for SEM charge-induced artifacts can be performed, except that the total variation can be considered, except that the symmetry of the adjusted image is not taken into account. The total variation can be minimized to determine the artifact intensity, which represents the noise vector within the image. Similar to the process above for SEM charge-induced artifacts, a line search along the noise-sensitive direction Δz can be performed, and the artifact intensity α of the noise artifact can be determined as the artifact intensity α that provides the adjusted image with the minimum total variation. Figure 8 The method shown and the optimization for reducing the total change are mathematically illustrated in the following equation:

[0078]

[0079] It is known that noise increases the total variation of an image. Therefore, by minimizing the total variation, we can find the artifact intensity of the noise artifact vector, for example, the length of the movement in the latent space, thus minimizing the noise. It is difficult to obtain an image free of any noise, so this technique provides a method for removing noise from such images. Of course, total variation is not the only measure of noise in an image; any other noise measure can be used for the optimization described above.

[0080] Similar processes to those described above can also be used to remove artifacts caused by resist shrinkage. This can be achieved by using... Figure 8 The method shown determines the artifact intensity, or artifact vector, of the resist shrinkage vector in a specific image set. Training images may also include images from which resist shrinkage artifacts will be removed. Similar to the method described above, based on... Figure 9 The line search of the method shown is performed along the shrinkage-sensitive direction Δz, minimizing a specific metric of shrinkage. One such metric that can be used is the area outside the resist formed on the semiconductor substrate, which can be called the complementary resist area (CRA). Resist shrinkage increases the area of ​​the image not covered by the resist. This area can be minimized so that the resist area is as close as possible to the actual area of ​​the resist on the semiconductor substrate. In this case, the optimized image corresponds to an image where the effect of resist shrinkage has been reduced. In such an example, the intensity α of the shrinkage vector can be determined according to the following equation.

[0081]

[0082] It is known that resist shrinkage increases the CRA of an image. Therefore, by minimizing the CRA, we can find the artifact intensity that minimizes the shrinkage artifact vector introduced by resist shrinkage.

[0083] In any of the methods described above, the artifact intensity can be determined from a set of training images, which may include images from which artifacts will be removed, i.e., images of the semiconductor substrate. This advantageously ensures that the artifact level in the image of interest from which artifacts ultimately need to be removed is comparable to the artifact level in the training set images. This can be used when removing SEM charge-induced artifacts, noise-induced artifacts, or resist shrinkage-induced artifacts.

[0084] Referring to the method described above that uses two sets of images with different encoding levels, Figure 9 The graph shows the encoding of two sets of images into the latent space z. Cross 400 indicates the encoding of the first set of images, in which a lower level of artifacts exists, and cross 402 indicates the encoding of the second set of images, in which a higher level of artifacts exists. Arrow 404 represents the artifact vector of the artifacts encoded into the latent space. Figure 9 The leftmost image is obtained using a SEM operating at normal scan speed, resulting in a relatively low level of artifacts. The rightmost image is obtained using a SEM running at half speed, resulting in a higher level of artifacts. In this case, the artifact of interest is the SEM charge-induced artifact. Figure 10A The graph in the lower right corner shows the normalized pixel intensity along the dashed line in the two images above. This graph illustrates how the pixel intensity at half speed is more asymmetrical than that at normal speed due to the stronger charge effect.

[0085] Figure 10A An image of a structure on a semiconductor substrate is shown. Figure 10B The image shown contains artifacts, which affect the accuracy of the measurements performed therefrom. Figure 10A It shows the relationship with Figure 1 The same image, except for artifact removal using the techniques disclosed herein. Removing artifacts from the image allows for more accurate measurements of the structure on the semiconductor substrate.

[0086] The training images used in the above methods can be any suitable training images. Training images can include images of semiconductor substrates containing artifacts. Training images can include images of multiple different semiconductor substrates containing artifacts. Furthermore, training images can include synthetic images, i.e., images that have already been manufactured. For example, synthetic images can include reflection, cropping, or other processing performed on an initial set of images of one or more semiconductor substrates.

[0087] In the above embodiments, a single type of artifact is subtracted in each case. However, a single image may include multiple artifacts present therein. Therefore, the method may include subtracting multiple different artifact vectors from the latent space. For example, charge-induced artifact vectors and noise artifact vectors may be removed to remove charge and noise from the image. Any combination of artifact vectors may be removed.

[0088] Figure 1 The metrology device 140 shown may include an imaging system configured to image a portion of a semiconductor substrate, and may also include an image analysis system configured to perform the methods disclosed herein. Similarly, an SCS or any other suitable system may include an image analysis system configured to perform the methods disclosed herein.

[0089] A method for manufacturing a semiconductor substrate is further disclosed herein, comprising the steps of: manufacturing at least a portion of the semiconductor substrate; performing a method for removing artifacts from an image of the semiconductor substrate as disclosed herein; analyzing and decoding the image to obtain a metric of the image; comparing the metric with a target metric, and taking remedial measures when the metric does not conform to the target metric. This manufacturing method can be used... Figure 1 The appropriate part of the device shown is used to perform the operation.

[0090] The techniques disclosed herein can be used to improve metrology, such as SEM metrology, without affecting throughput. Furthermore, the techniques disclosed herein can be adopted by existing commercial metrology products, such as SEM modeling products, to provide a rapid solution for removing additional artifacts from images obtained using metrology processes.

[0091] Advantageously, the techniques disclosed in this paper do not necessarily require the existence of an image free of artifacts in order to determine the artifact vector. Instead, an optimization problem is solved to determine the length of the artifact vector.

[0092] Some of the techniques disclosed herein advantageously minimize or even eliminate the need for other means of reducing artifacts in images of semiconductor substrates. For example, it may no longer be necessary to: optimize the landing energy of the electron beam, cover the target with a conductive alloy, use faster scans with lower charge doses, use more imaging frames, use opposite scan directions, perform multiple averaging, adjust the electron dose per pixel, perform model-based extrapolation, or flood the exposed target. All of these existing techniques are known to have limitations; for example, while some techniques reduce one type of artifact, they increase another type or have other negative effects, such as reduced resolution or signal-to-noise ratio. Therefore, by using the disclosed methods for artifact removal, optimal images with reduced levels of existing artifacts can be obtained without potentially negatively impacting the image, such as its resolution, in other ways.

[0093] The techniques disclosed in this article can reduce the complexity of the SEM process.

[0094] The techniques disclosed in this paper can be used for online measurement of control loops and wafer placement.

[0095] Although specific techniques have been described above, it should be understood that this disclosure may be implemented in ways other than those described.

[0096] Implementations may include a computer program containing one or more machine-readable instruction sequences configured to instruct as follows: Figure 1 The various devices shown perform measurement and optimization steps and control the subsequent exposure process as described above. For example, the computer program can... ​ The computer program is executed within a control unit (LACU) or a supervisory control system (SCS), or a combination of both. A data storage medium (e.g., semiconductor memory, magnetic disk, or optical disk) in which such a computer program is stored may also be provided.

[0097] While specific references to optical lithography may have been made above, it should be understood that the techniques disclosed herein can be used in other applications, such as imprint lithography. In imprint lithography, the morphology within a patterning apparatus defines the pattern created on a substrate. The morphology of the patterning apparatus can be pressed into a resist layer provided to the substrate, and the resist can then be cured by applying electromagnetic radiation, heat, pressure, or a combination thereof. After the resist has cured, the patterning apparatus is removed from the resist, leaving the pattern therein.

[0098] As used herein, the terms “radiation” and “beam” encompass all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., wavelengths of about 365, 355, 248, 193, 157, or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., wavelengths in the range of 1–100 nm), as well as particle beams such as ion beams or electron beams. The implementation of scatterometers and other inspection apparatus can be carried out using suitable sources at UV and EUV wavelengths, and this disclosure is by no means limited to systems using IR and visible radiation.

[0099] Where the context permits, the term "lens" can refer to any one or a combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic, and electrostatic optical components. Reflective components are likely used in devices operating in the UV or EUV range.

[0100] As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless impractical. For example, if a declared component may include A or B, then unless otherwise expressly stated or impractical, the component may include A, or B, or A and B. As a second example, if a declared component may include A, B, or C, then unless otherwise expressly stated or impractical, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0101] The various aspects of this disclosure are set forth in the following numbered clauses:

[0102] 1. A method for removing artifacts from an image of a semiconductor substrate, the method comprising:

[0103] Obtain an image of the structure on the semiconductor substrate;

[0104] The image of the structure is encoded into the latent space to form the first code;

[0105] Subtract the artifact vector representing the artifacts in the image from the encoding to form the second encoding; and

[0106] The second encoding is decoded to obtain the decoded image.

[0107] 2. The method according to Clause 1, wherein the artifact vector is determined by:

[0108] Multiple training images of semiconductor substrates are encoded into the latent space, wherein the multiple training images include at least two sets of images, the first set of images having artifacts of a first level present therein, and the second set of images having artifacts of a second and higher level present therein.

[0109] 3. The method described in Clause 2 further includes:

[0110] Determine the average encoding of the first group of images and determine the average encoding of the second group of images;

[0111] The artifact direction is determined by subtracting the average encoding of the first group of images from the average encoding of the second group of images after normalization.

[0112] Determine the intensity of the artifact; and

[0113] The artifact intensity and the artifact direction are multiplied to provide the artifact vector.

[0114] 4. The method according to Clause 3, wherein the artifact intensity is determined by:

[0115] For multiple training images, and for each value in the range of test artifact intensity values, perform the following steps:

[0116] Determine the average encoding of the plurality of training images in the latent space;

[0117] The adjusted encoding is formed by subtracting the artifact direction multiplied by the test artifact intensity value from the average encoding of the plurality of training images; and

[0118] The adjusted encoding is decoded to form the adjusted image;

[0119] The artifact intensity is determined to be a specific test artifact intensity value among the test artifact intensity values, and for the specific test artifact intensity value, the adjusted image corresponds to the optimized image.

[0120] 5. The method according to Clause 4, wherein the optimized image is an image with maximum symmetry.

[0121] 6. The method according to Clause 5, wherein the plurality of training images are selected to include an image having a symmetrical geometry.

[0122] 7. The method according to any one of clauses 4-6, wherein the optimized image is an image with minimum total change.

[0123] 8. The method according to any one of clauses 4-7, wherein the optimized image corresponds to an image in which the effect of resist shrinkage has been reduced.

[0124] 9. The method according to any one of clauses 2-8, wherein the plurality of training images includes an image of a semiconductor substrate from which artifacts are to be removed.

[0125] 10. The method according to any of the preceding clauses, wherein the step of obtaining an image of the structure on the semiconductor substrate includes obtaining the image using a scanning electron microscope.

[0126] 11. The method according to any of the preceding clauses, wherein the artifact is caused at least in part by the charge of the semiconductor substrate.

[0127] 12. The method according to any of the preceding clauses, wherein the artifact is caused at least in part by noise in the image of the semiconductor substrate.

[0128] 13. The method according to any of the preceding clauses, wherein the semiconductor substrate includes a photoresist thereon, and wherein the artifact is caused at least in part by the shrinkage of the photoresist.

[0129] 14. An inspection tool, comprising:

[0130] An imaging system is configured to image a portion of a semiconductor substrate; and

[0131] The image analysis system is configured as follows:

[0132] Obtain an image of the structure on the semiconductor substrate from the imaging system;

[0133] The image of the structure is encoded into a latent space to form a first code;

[0134] Subtract the artifact vector representing the artifacts in the image from the encoding to form the second encoding; and

[0135] The second encoding is decoded to obtain the decoded image.

[0136] 15. The inspection tool according to Clause 14, wherein the artifact vector is determined by:

[0137] Multiple training images of semiconductor substrates are encoded into the latent space, wherein the multiple training images include at least two sets of images, the first set of images having artifacts of a first level present therein, and the second set of images having artifacts of a second and higher level present therein.

[0138] 16. The inspection tools described in Clause 15 further include:

[0139] Determine the average encoding of the first group of images and determine the average encoding of the second group of images;

[0140] The artifact direction is determined by subtracting the average encoding of the first group of images from the average encoding of the second group of images after normalization.

[0141] Determine the intensity of the artifact; and

[0142] The artifact intensity and the artifact direction are multiplied to provide the artifact vector.

[0143] 17. The inspection tool according to Clause 16, wherein the intensity of the artifact is determined by:

[0144] For multiple training images, and for each value in the range of test artifact intensity values, perform the following steps:

[0145] Determine the average encoding of the plurality of training images in the latent space;

[0146] The adjusted encoding is formed by subtracting the artifact direction multiplied by the test artifact intensity value from the average encoding of the plurality of training images; and

[0147] The adjusted encoding is decoded to form the adjusted image;

[0148] The artifact intensity is determined to be a specific test artifact intensity value among the test artifact intensity values, and for the specific test artifact intensity value, the adjusted image corresponds to the optimized image.

[0149] 18. The inspection tool as described in Clause 17, wherein the optimized image is an image with maximum symmetry.

[0150] 19. The inspection tool as described in Clause 18, wherein the plurality of training images are selected to include an image having a symmetrical geometry.

[0151] 20. The inspection tool according to any one of clauses 17-19, wherein the optimized image is an image with minimal total change.

[0152] 21. The inspection tool according to any one of clauses 17-20, wherein the optimized image corresponds to an image in which the effect of resist shrinkage has been reduced.

[0153] 22. The inspection tool according to any one of clauses 15-21, wherein the plurality of training images includes an image of a semiconductor substrate from which artifacts are to be removed.

[0154] 23. The examination tool according to any one of clauses 14-22, wherein the imaging system comprises a scanning electron microscope.

[0155] 24. The inspection tool according to any one of clauses 14-23, wherein the artifacts are at least partially caused by the charge of the semiconductor substrate.

[0156] 25. The inspection tool according to any one of clauses 14-24, wherein the artifacts are at least partially caused by noise in the image of the semiconductor substrate.

[0157] 26. The inspection tool according to any one of clauses 14-25, wherein the semiconductor substrate includes a resist thereon, and wherein the artifact is caused at least in part by resist shrinkage.

[0158] 27. A method for manufacturing a semiconductor substrate, the method comprising the following steps:

[0159] To manufacture at least a portion of the semiconductor substrate;

[0160] Obtain an image of the structure on the semiconductor substrate;

[0161] The image of the structure is encoded into the latent space to form the first code;

[0162] The second code is formed by subtracting the artifact vector representing the artifacts in the image from the code;

[0163] The second encoding is decoded to obtain the decoded image;

[0164] Analyze the decoded image to obtain a metric of the image; and

[0165] The metric is compared with a target metric, and remedial measures are taken when the metric does not meet the target metric.

[0166] 28. The manufacturing method according to Clause 27, wherein the artifact vector is determined by:

[0167] Multiple training images of semiconductor substrates are encoded into the latent space, wherein the multiple training images include at least two sets of images, a first set of images having a first level of artifacts present therein, and a second set of images having a higher second level of artifacts present therein.

[0168] 29. The manufacturing method according to Clause 28 further includes: determining the average code of the first set of images and determining the average code of the second set of images;

[0169] The artifact direction is determined by subtracting the average encoding of the first group of images from the average encoding of the second group of images after normalization.

[0170] Determine the intensity of the artifact; and

[0171] The artifact intensity and the artifact direction are multiplied to provide the artifact vector.

[0172] 30. The manufacturing method according to Clause 29, wherein the intensity of the artifact is determined by:

[0173] For multiple training images, and for each value in the range of test artifact intensity values, perform the following steps:

[0174] Determine the average encoding of the plurality of training images in the latent space;

[0175] The adjusted encoding is formed by subtracting the artifact direction multiplied by the test artifact intensity value from the average encoding of the plurality of training images; and

[0176] The adjusted encoding is decoded to form the adjusted image;

[0177] The artifact intensity is determined to be a specific test artifact intensity value among the test artifact intensity values, and the adjusted image corresponds to the optimized image for the specific test artifact intensity value.

[0178] 31. The manufacturing method according to Clause 30, wherein the optimized image is an image with maximum symmetry.

[0179] 32. The manufacturing method according to Clause 31, wherein the plurality of training images are selected to include an image having a symmetrical geometry.

[0180] 33. The manufacturing method according to any one of clauses 27-32, wherein the optimized image is an image with minimal total change.

[0181] 34. The manufacturing method according to any one of clauses 27-33, wherein the optimized image corresponds to an image in which the effect of resist shrinkage has been reduced.

[0182] 35. The manufacturing method according to any one of clauses 27-34, wherein the plurality of training images includes an image of a semiconductor substrate from which artifacts are to be removed.

[0183] 36. A manufacturing method according to any one of clauses 27-35, wherein the step of obtaining an image of the structure on the semiconductor substrate includes obtaining the image using a scanning electron microscope.

[0184] 37. The manufacturing method according to any one of clauses 27-36, wherein the artifacts are at least partially caused by the charge of the semiconductor substrate.

[0185] 38. The manufacturing method according to any one of clauses 27-37, wherein the artifacts are caused at least in part by noise in an image of the semiconductor substrate.

[0186] 39. The manufacturing method according to any one of clauses 29-38, wherein the semiconductor substrate includes a photoresist thereon, and wherein the artifacts are caused at least in part by the shrinkage of the photoresist.

[0187] The breadth and scope of the technology disclosed herein should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method of removing artifacts from an image of a semiconductor substrate, the method comprising: obtaining an image of a structure on the semiconductor substrate; encoding the image of the structure into a latent space, thereby forming a first encoding; subtracting an artifact vector representing an artifact in the image from the encoding, thereby forming a second encoding; and decoding the second encoding to obtain a decoded image.

2. The method of claim 1, wherein, The artifact vector is determined by: encoding a plurality of semiconductor substrate training images into the latent space, wherein the plurality of training images comprises at least two groups of images, a first group of images having a first level of artifacts present therein, and a second group of images having a higher second level of artifacts present therein.

3. The method of claim 2, further comprising: determining an average encoding of the first group of images and determining an average encoding of the second group of images; determining an artifact direction by normalizing a subtraction of the average encoding of the first group of images from the average encoding of the second group of images; determining an artifact strength; and multiplying the artifact strength and the artifact direction to provide the artifact vector.

4. The method of claim 3, wherein the artifact strength is determined by: performing the following steps for a plurality of the training images, and for each value in a range of test artifact strength values: determining an average encoding of the plurality of training images in the latent space; subtracting a product of the artifact direction and the test artifact strength value from the average encoding of the plurality of training images, thereby forming an adjusted encoding; and decoding the adjusted encoding to form an adjusted image; wherein the artifact strength is determined to be a particular one of the test artifact strength values for which the adjusted image corresponds to an optimized image.

5. The method of claim 4, wherein the optimized image is an image having a maximum symmetry.

6. The method of claim 5, wherein the plurality of training images are selected to include images having a symmetric geometric shape therein.

7. The method of claim 4, wherein the optimized image is an image having a minimum total variation.

8. The method of claim 4, wherein the optimized image corresponds to the image in which effects of resist shrinkage have been reduced.

9. The method of claim 2, wherein the plurality of training images includes the image of the semiconductor substrate from which the artifact is to be removed.

10. The method of any one of the preceding claims, wherein the step of obtaining an image of a structure on the semiconductor substrate comprises obtaining an image using a scanning electron microscope.

11. The method of claim 1, wherein the artifact is caused at least in part by a charging of the semiconductor substrate.

12. The method of claim 1, wherein the artifact is caused at least in part by noise in the image of the semiconductor substrate. ​ 13. The method of claim 1, wherein the semiconductor substrate includes resist thereon, and wherein the artifact is caused at least in part by resist shrinkage.

14. An inspection tool comprising: an imaging system configured to image a portion of a semiconductor substrate; and an image analysis system configured to: obtain an image of a structure on the semiconductor substrate from the imaging system; encode the image of the structure into a latent space, thereby forming a first encoding; subtract an artifact vector representing an artifact in the image from the encoding, thereby forming a second encoding; and decode the second encoding to obtain a decoded image.

15. The inspection tool of claim 14, wherein the artifact vector is determined by: encoding a plurality of semiconductor substrate training images into the latent space, wherein the plurality of training images includes at least two sets of images, a first set of images having a first level of the artifact present therein, and a second set of images having a second, higher level of the artifact present therein.

16. The inspection tool of claim 15, further comprising: determining an average encoding of the first set of images and determining an average encoding of the second set of images; determining an artifact direction by normalizing a subtraction of the average encoding of the first set of images from the average encoding of the second set of images; determining an artifact strength; and multiplying the artifact strength and the artifact direction to provide the artifact vector.

17. The inspection tool of claim 16, wherein the artifact strength is determined by: performing the following steps for a plurality of training images, and for each value in a range of test artifact strength values: determining an average encoding of the plurality of training images in the latent space; subtracting a product of the artifact direction and the test artifact strength value from the average encoding of the plurality of training images, thereby forming an adjusted encoding; and decoding the adjusted encoding to form an adjusted image; wherein the artifact strength is determined to be a particular one of the test artifact strength values for which the adjusted image corresponds to an optimized image.

18. The inspection tool of claim 17, wherein the optimized image is an image having maximum symmetry.

19. The inspection tool of claim 18, wherein the plurality of training images are selected to include images having symmetric geometric shapes therein.

20. The inspection tool of claim 17, wherein the optimized image is an image having minimum total variation.

21. The inspection tool of claim 17, wherein the optimized image corresponds to an image in which effects of resist shrinkage have been reduced.

22. The inspection tool of claim 15, wherein the plurality of training images includes the image of the semiconductor substrate from which the artifact is to be removed.

23. The inspection tool of claim 14, wherein the imaging system comprises a scanning electron microscope. ​ 24. The inspection tool of claim 14, wherein the artifact is caused at least in part by charging of the semiconductor substrate.

25. The inspection tool of claim 14, wherein the artifact is caused at least in part by noise in the image of the semiconductor substrate.

26. The inspection tool of claim 14, wherein the semiconductor substrate includes resist thereon, and wherein the artifact is caused at least in part by resist shrinkage.

27. A method of manufacturing a semiconductor substrate, the method comprising the steps of: manufacturing at least part of the semiconductor substrate; obtaining an image of a structure on the semiconductor substrate; encoding the image of the structure into a latent space, thereby forming a first encoding; subtracting an artifact vector representing an artifact in the image from the encoding, thereby forming a second encoding; decoding the second encoding to obtain a decoded image; analyzing the decoded image to obtain a metric of the image; and comparing the metric to a target metric and taking remedial action when the metric does not conform to the target metric.

28. The method of manufacturing of claim 27, wherein the artifact vector is determined by: encoding a plurality of semiconductor substrate training images into the latent space, wherein the plurality of training images includes at least two groups of images, a first group of images having a first level of artifacts present therein, and a second group of images having a higher second level of artifacts present therein.

29. The manufacturing method of claim 28, further comprising: determining an average encoding of the first group of images and determining an average encoding of the second group of images; determining an artifact direction by normalizing a subtraction of the average encoding of the first group of images from the average encoding of the second group of images; determining an artifact strength; and multiplying the artifact strength and the artifact direction to provide the artifact vector.

30. The method of manufacturing of claim 29, wherein the artifact strength is determined by: for a plurality of the training images, and for each value in a range of test artifact strength values, performing the steps of: determining an average encoding of the plurality of training images in the latent space; subtracting a product of the artifact direction and the test artifact strength value from the average encoding of the plurality of training images, thereby forming an adjusted encoding; and decoding the adjusted encoding to form an adjusted image; wherein the artifact strength is determined to be a particular one of the test artifact strength values for which the adjusted image corresponds to an optimized image.

31. The method of manufacturing of claim 30, wherein the optimized image is an image having maximum symmetry.

32. The method of manufacturing of claim 31, wherein the plurality of training images are selected to include images having symmetric geometric shapes therein.

33. The method of manufacturing of claim 27, wherein the optimized image is an image having minimum total variation. ​ 34. The manufacturing process of claim 27, wherein the optimized image corresponds to an image in which effects of resist shrinkage have been reduced.

35. The manufacturing process of claim 28, wherein the plurality of training images comprises images of the semiconductor substrate from which artifacts are to be removed.

36. The manufacturing process of claim 27, wherein the step of obtaining an image of a structure on the semiconductor substrate comprises using a scanning electron microscope to obtain the image.

37. The manufacturing process of claim 27, wherein the artifact is caused at least in part by charging of the semiconductor substrate.

38. The manufacturing process of claim 27, wherein the artifact is caused at least in part by noise in the image of the semiconductor substrate.

39. The manufacturing process of claim 29, wherein the semiconductor substrate comprises resist thereon, and wherein the artifact is caused at least in part by resist shrinkage.

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