Power supply circuit with reduced leakage current

Abstract

Apparatuses and methods for reducing leakage current are presented. An apparatus includes a switch circuit configured to power a circuit block, a delay circuit configured to delay enabling the switch circuit to power the circuit block and configured to be powered down, and a bypass circuit configured to bypass the delay circuit to disable the switch circuit to power the circuit block. A method includes powering a circuit block by a switch, powering down a delay circuit, and bypassing the delay circuit by a bypass circuit to disable the switch to power the circuit block.

Description

[0001] CLAIM

[0002] This patent application claims priority to Provisional First Filing Patent Application in India, Application No. 202041018624, filed on May 1, 2020, entitled “POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT,” which is assigned to the assignee of the present application and is hereby expressly incorporated by reference herein. TECHNICAL FIELD

[0003] The present disclosure relates generally to methods and apparatuses of power supply circuits with reduced leakage current, and more particularly, to methods and apparatuses of power supply circuits with powering down a delay circuit to reduce leakage current. BACKGROUND

[0004] Computing devices (e.g., laptops, mobile phones, etc.) can include processors on one or more semiconductor dies to perform various functions, such as telephony, internet access, camera / video functionality, etc. The processors can include various circuit blocks to perform these functions. These circuit blocks and other circuit blocks draw power when in operation. The circuit blocks can be powered by a power source, such as a battery and a wall plug-in, via a power / voltage regulation circuit. For example, the power source can generate a supply voltage, and the power supply circuit can be configured to provide the supply voltage to the circuit blocks. SUMMARY

[0005] This summary identifies some example aspects and is not an exclusive or exhaustive description of the subject matter disclosed. Additional features and aspects are described and will become apparent to those skilled in the art upon consideration of the following detailed description and appended claims with reference to the accompanying drawings.

[0006] An apparatus according to at least one embodiment includes a switch circuit configured to power a circuit block, a delay circuit configured to delay enabling the switch circuit to power the circuit block and configured to be powered down, and a bypass circuit configured to bypass the delay circuit to disable the switch circuit to power the circuit block.

[0007] Aspects of a method of reducing leakage current according to at least one embodiment are presented. The method includes powering a circuit block by a switch, powering down a delay circuit, and bypassing the delay circuit by a bypass circuit to disable the switch circuit to power the circuit block. Bypassing the delay circuit to disable the switch circuit to power the circuit block allows the delay circuit to be powered down. In this way, the contribution of the delay circuit to leakage current in a standby mode or a powered down mode can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0008] Various aspects of apparatuses and methods will now be presented in the detailed description with reference to the accompanying drawings, by way of example and not limitation, in which:

[0009] Figure 1 An apparatus 100 having a power supply circuit with reduced leakage current, in accordance with certain aspects of the present disclosure, is illustrated.

[0010] Figure 2 An example circuit of an apparatus, in accordance with certain aspects of the present disclosure, is illustrated. Figure 1

[0011] An example operation of an apparatus, in accordance with certain aspects of the present disclosure, is illustrated. Figure 3 Figure 1 An example operation of an apparatus 100 during power up on a supply voltage, in accordance with certain aspects of the present disclosure, is illustrated.

[0012] Figure 4 Figure 1 An example circuit of a next stage power supply circuit 104, in accordance with certain aspects of the present disclosure, is illustrated.

[0013] Figure 5 An additional portion of a method of reducing leakage current when powering a circuit block, in accordance with certain aspects of the present disclosure, is illustrated. Figure 1

[0014] An additional portion of a method of reducing leakage current when powering a circuit block, in accordance with certain aspects of the present disclosure, is illustrated. Figure 6

[0015] An additional portion of a method of reducing leakage current when powering a circuit block, in accordance with certain aspects of the present disclosure, is illustrated. Figure 7

[0016] An additional portion of another method of reducing leakage current when powering a circuit block, in accordance with certain aspects of the present disclosure, is illustrated. Figure 8

[0017] An additional portion of another method of reducing leakage current when powering a circuit block, in accordance with certain aspects of the present disclosure, is illustrated. Figure 9

[0018] An additional portion of another method of reducing leakage current when powering a circuit block, in accordance with certain aspects of the present disclosure, is illustrated. Figure 10

[0019] An additional portion of another method of reducing leakage current when powering a circuit block, in accordance with certain aspects of the present disclosure, is illustrated. Figure 11 DETAILED DESCRIPTION

[0020] ​​​The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0021] As used herein, the term "coupled to" of various forms of the verb "couple" can mean that element A is directly connected to element B, or that other elements can be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "coupled to" can also be used herein to mean that element A and element B are electrically connected using a wire, a trace, or other conductive material (as well as any components electrically connected between them). In some examples, the term "coupled to" indicates that there is current flow between element A and element B. In some examples, the term "electrically connected" can indicate that there is current flow between element A and element B. The term "node" can mean an electrical connection, a conductor, or wiring.

[0022] The terms "first," "second," "third," etc. are employed for ease of reference and can not have substantive meaning. An example can include a "first" control signal.

[0023] As computing device functionality grows and physical size shrinks, reducing power consumption is becoming of increasing concern. For example, a computing device can enter a standby mode in which the computing device can power down certain circuit blocks and / or not respond to certain control signals. In the standby mode, the computing device will continue to draw leakage current. For example, in the standby mode, a power supply circuit that provides a supply voltage to a circuit block can continue to draw leakage current even though there is no operation.

[0024] Further, in the powered down mode, the supply voltage can be powered down (e.g., grounded) to reduce power consumption. The power supply circuit can likewise draw leakage current in the powered down mode. Further, powering up the supply voltage network to exit the powered down mode can cause a large inrush current to flow through the power supply circuit. Accordingly, the power supply circuit can include multiple portions that operate in a staggered manner. For example, the power supply circuit can include a power supply circuit and a next stage power supply circuit, each of which can include a delay circuit. Upon powering up the supply voltage, the power supply circuit can begin to power up a first circuit block and then, after a delay by the delay circuit, a second circuit block is powered up by the next stage power supply circuit. Staggering the power supply circuit upon powering up the supply voltage reduces the peak of the inrush current, but the delay circuit can draw more leakage current in the standby mode or the powered down mode.

[0025] Methods and apparatuses to reduce leakage in a power supply circuit (e.g., in a standby mode) are presented. For example, a delay circuit can be powered down to reduce leakage current in a standby mode or power down mode. In some examples, a power supply circuit can be configured to receive a plurality of control signals, e.g., a first control signal and a second control signal. In certain operations, a delay circuit can be powered down by the first control signal or the second control signal.

[0026] Figure 1 An apparatus 100 having a power supply circuit with reduced leakage current is illustrated in accordance with certain aspects of the present disclosure. For example, the apparatus 100 can be one of a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop computer, a cellular phone, a vehicle, etc.), an Internet of Things device, and / or a virtual reality or augmented reality system. The apparatus 100 includes a power supply circuit 102 and a next stage power supply circuit 104, a control circuit 111, and a circuit block 112 and a circuit block 114. The power supply circuit 102 is coupled to a supply voltage VDD2 and is configured to supply power from the supply voltage VDD2 to a circuit block 122. The next stage power supply circuit 104 is coupled to the supply voltage VDD2 and is configured to supply power from the supply voltage VDD2 to a second circuit block 124. The circuit blocks 122 and 124 can perform various functions and can include, for example, a processing unit or a memory.

[0027] The control circuit 111 can be configured to control the functions (presented below) of the power supply circuit 102 and the next stage power supply circuit 104 via signaling S113 (e.g., via one or more electrical connections). Certain portions of the control circuit 111 can be coupled to and / or powered by a supply voltage VDD1, and other portions can be coupled to and / or powered by a supply voltage VDD2. The supply voltages VDD1 and VDD2 can be different. Certain portions of the control circuit 111 can thus operate based on the supply voltage VDD1 and can be in a first voltage domain. The power supply circuit 102 and the next stage power supply circuit 104, the circuit block 112 and the circuit block 114, and other portions of the control circuit 111 that are powered by and / or operate based on the supply voltage VDD2 can be in a second voltage domain.

[0028] In some examples, the power supply circuit 102 and the next stage power supply circuit 104 can power (e.g., restart powering) the circuit blocks 112 and 114 in an interleaved manner, for example, to exit a standby mode or a power-off mode. For example, the power supply circuit 102 can be configured to first power the circuit block 122, and then provide signaling S103 (e.g., via one or more electrical connections) to the next stage power supply circuit 104. In response to the signaling S103, the next stage power supply circuit 104 can be configured to power the circuit block 114 after a delay. In this way, a peak of an inrush current to exit the standby mode or the power-off mode can be reduced.

[0029] Figure 2 FIG. 1 illustrates an example circuit of an apparatus in accordance with certain aspects of the present disclosure. Figure 1 FIG. 2 illustrates an example circuit of an apparatus in accordance with certain aspects of the present disclosure. Figure 2 FIG. 3 illustrates an example circuit of an apparatus in accordance with certain aspects of the present disclosure. Figure 1 The power supply circuit 102, the control circuit 111, and the circuit block 122 of FIG. 1. As illustrated, the power supply circuit 102 can include a delay circuit 202, a bypass circuit 204, and / or a switch circuit 206. The control circuit 111 can include a power-off circuit 212, control logic-1 214, a voltage shifter circuit 216, and control logic-2 218.

[0030] The switch circuit 206 can be configured to power the circuit block 122. As illustrated, the switch circuit 206 can include a p-type transistor 258. The p-type transistor 258 can be configured to have a source coupled to the node N23, and to have a drain coupled to the node N22. The drain can also be coupled to the circuit block 122 via the node N22. The p-type transistor 258 can be configured to receive power via the node N23, and to power the circuit block 122 via the node N22. The p-type transistor 258 can also be configured to have a gate coupled to the node N21. The p-type transistor 258 (and thus the switch circuit 206) can be configured to turn on (or turn off) based on signaling on the node N21 to power (or not power) the circuit block 122.

[0031] The node N23 can provide a supply voltage VDD2, and the switch circuit 206 can be configured to provide the supply voltage VDD2 to the circuit block 122. Thus, the switch circuit 206 can be configured to power the circuit block 122 in a second voltage domain. For example, the switch circuit 206 can be configured to power the circuit block 122 based on the supply voltage VDD2 in the second voltage domain. In this way, the switch circuit 206 can be configured to operate based on the supply voltage VDD2.

[0032] Bypass circuit 204 can be configured to drive switch circuit 206 to enable and disable switch circuit 206 to power circuit block 122. Bypass circuit 204 can also be configured to drive switch circuit 206 based on first and second control signals (e.g., control signal SLP and control signal CLAMP, respectively; see Figure 3 and Figure 4 ). As illustrated, bypass circuit 204 includes NAND gate 225 and inverter 257 arranged in series via node N20. NAND gate 225 can be configured to receive input via nodes N19 and N16 (e.g., first and second inputs, respectively) and output via node N20. Inverter 257 can be configured to receive input from node N20 and output to switch circuit 206 via node N21. For example, bypass circuit 204 can be configured to drive the gate of p-type transistor 258 of switch circuit 206 via inverter 257 to turn p-type transistor 258 on and off to enable and disable switch circuit 206 to power circuit block 122. Further, signaling on node N21 (e.g., signaling S103 in Figure 1 may be provided to next stage power circuit 104 (see Figure 1 and Figure 5 ).

[0033] In some examples, bypass circuit 204 can be in the second power domain. For example, bypass circuit 204 (e.g., NAND gate 225 and / or inverter 257) can be configured to be coupled to and powered via node N23, which is configured to provide supply voltage VDD2. Thus, bypass circuit 204 (e.g., NAND gate 225 and / or inverter 257) can be configured to be powered by and / or operate based on supply voltage VDD2 in the second voltage domain.

[0034] Delay circuit 202 can be configured to delay signaling to bypass circuit 204. In some examples, delay circuit 202 delays the signaling for a predetermined period of time. In some examples, the only or primary purpose of delay circuit 202 is to delay the signaling. In some examples, the delayed signaling can be based on control signal SLP. In some examples, delay circuit 202 can be configured to delay enabling switch circuit 206 to power circuit block 122 and can be configured to be powered down (e.g., as instructed by control circuit 111).

[0035] As illustrated, the delay circuit 202 can include N-stages of inverters 253_1 through 253_N arranged in series. For example, an output of the inverter 253_1 can be provided as an input to the inverter 253_2, and so on. The inverters 253_1 through 253_N can be configured to be powered via a node N18. The delay circuit 202 can be configured to receive signaling via a node N17, delay the received signaling, and output the delayed signaling to the bypass circuit 204 via a node N19. As utilized herein, the term "delay" can refer to a delay of a signal by a delay circuit, such as the delay circuit 202. For example, the delay circuit 202 can be configured to delay a signal received via the node N17 by a delay of the inverters 253_1 through 253_N. In some examples, the delay circuit 202 can be configured to delay the signal received via the node N17 by a delay of 1 nanosecond (ns), 2 ns, 3 ns, 4 ns, 5 ns, 6 ns, 7 ns, 8 ns, 9 ns, 10 ns, 20 ns, 30 ns, 40 ns, 50 ns, 60 ns, 70 ns, 80 ns, 90 ns, 100 ns, 200 ns, 300 ns, 400 ns, 500 ns, 600 ns, 700 ns, 800 ns, 900 ns, 1000 ns, 2000 ns, 3000 ns, 4000 ns, 5000 ns, 6000 ns, 7000 ns, 8000 ns, 9000 ns, 10000 ns, or any other delay. Figure 3 As illustrated, the signaling on the node N17 can be based on a control signal SLP.

[0036] In some examples, the delay circuit 202 can be in a second power domain. For example, the delay circuit 202 (e.g., the N-stages of inverters 253_1 through 253_N) can be configured to be coupled to and powered via a node N23 configured to provide a supply voltage VDD2 (see below for a description of the control circuit 111). Thus, the delay circuit 202 (e.g., the N-stages of inverters 253_1 through 253_N) can be configured to be powered by and operate based on the supply voltage VDD2 in the second voltage domain. See below for a description of the control circuit 111.

[0037] As described above, the bypass circuit 204 can be configured to bypass the delay circuit 202 to disable the switch circuit 206 that powers the circuit block 122. The bypass circuit can include a first input (e.g., the node N19) and a second input (e.g., the node N16). The delay circuit 202 can be configured to delay enabling the switch circuit 206 that powers the circuit block 122 via the first input (e.g., the node N19). The bypass circuit 204 can be further configured to bypass the delay circuit 202 to disable the switch circuit 206 that powers the circuit block 122 based on signaling received via the second input (e.g., the node N16). In some examples, the bypass circuit 204 can include a gate, such as a NAND gate 255, coupled to the first input (e.g., the node N19) and the second input (e.g., the node N16).

[0038] The control circuit 111 can be configured to enable and disable the power supply circuit 102 that supplies power to the circuit block 122 based on a control signal SLP (e.g., a first control signal) and via the delay circuit 202 and the bypass circuit 204. The control signal SLP can be in the voltage domain (e.g., a first voltage domain) of the supply voltage VDD1 and can be in a logic 1 state or a logic 0 state. The control circuit 111 can also be configured to cause the bypass circuit 204 to drive the switch circuit 206 to disable the switch circuit 206 that supplies power to the circuit block 122, bypass the delay circuit 202 based on a control signal CLAMP (e.g., a second control signal). The second control signal CLAMP can be in the voltage domain (e.g., a second voltage domain) of the supply voltage VDD2 and can be in a logic 1 state or a logic 0 state.

[0039] The power down circuit 212 can be coupled to and powered via the node N11 and configured to receive an input via the node N02. The node N11 can be configured to provide the supply voltage VDD1. The power down circuit 212 can be configured to provide power to the control logic-1 214 via the node N15 and further configured to power down the control logic-1 214 based on the control signal CLAMP received via the node N02. For example, the power down circuit 212 can be configured to provide power from the node N11 to the control logic-1 214 via the node N15 in response to the CLAMP signal being in a first state (e.g., logic 1). The power down circuit 212 can also be configured to stop powering the control logic-1 214 via the node N15 (e.g., configured to power down) in response to the CLAMP signal being in a second state (e.g., logic 0). In some examples, the power down circuit 212 can include a p-type transistor (not shown) having a source coupled to the node N11, a drain coupled to the node N15, and a gate coupled to the node N02.

[0040] The control logic-1 214 can be configured to receive the control signal SLP via the node N04 and output a state of the SLP signal to the voltage shifter circuit 216 via the node N14. The control logic-1 214 can be configured to be powered via the node N15 to implement various functions (e.g., those presented below) to control the power supply circuit 102. For example, the control logic-1 214 can be configured to output a state of the SLP signal to the voltage shifter circuit 216 via the node N14. For example, the control logic-1 214 can be configured to output a logic 0 to the voltage shifter circuit 216 via the node N14 in response to the SLP signal being in a logic 0 state.

[0041] In some examples, node N11 can be configured to provide a supply voltage VDD1 that is different from the supply voltage VDD2. As the de-energizing circuit 212 and the control logic-1 214 operate based on and / or are powered by the supply voltage VDD1, the de- energizing circuit 212 and the control logic-1 214 can be in a first voltage domain. In some examples, the SLP signal can be in the first voltage domain. Circuits and signals that operate based on and / or are powered by the supply voltage VDD2 can be in a second voltage domain. The CLAMP signal can be in the second voltage domain.

[0042] The voltage shifter circuit 216 can be configured to convert signaling in the first voltage domain (e.g., received from node N14) to signaling in the second voltage domain (output to nodes N12 and N13). In some examples, the signaling at node N12 or node N13 can be an inverted state of the input at node N14. The voltage shifter circuit 216 can also be configured to output signaling in the second voltage domain to the control logic-2 218 via nodes N12 and N13. The control logic-2 218 can be configured to receive inputs on nodes N12, N13 and the CLAMP signal on node N06. The control logic-2 218 can also be configured to output various signals on nodes N16, N17, and N18 to cause the supply circuit 102 to operate. In this way, the control circuit 111 can be configured to provide signaling to a second input (e.g., node N16) via the voltage shifter circuit 216. In some examples, the control logic-2 218 can be configured to receive and be powered by the supply voltage VDD2 via node N23. The control logic-2 218 powered by and / or operating based on the supply voltage VDD2 can thus be in the second voltage domain.

[0043] The control circuit 111 can be configured to enable and disable the switching circuit 206 that powers the circuit block 122 based on the control signal SLP (which can be referred to as a first control signal) and via the delay circuit 202 and the bypass circuit 204. The control circuit 111 can also be configured to, in response to a state of the control signal CLAMP (which can be referred to as a second control signal) and independent of the control signal SLP, de-energize the delay circuit 202 and cause the bypass circuit 204 to drive the switching circuit 206 to disable the switching circuit 206 that powers the circuit block 122. The control circuit 111 can also be configured to, in response to a second state of the control signal CLAMP, enable and disable the switching circuit 206 that powers the circuit block 122 based on the control signal SLP and via the delay circuit 202, allowing the bypass circuit 204 to drive the switching circuit 206. These and other functions and operations of the control circuit 111 are presented with reference to Figure 3 ​

[0044] Figure 3 FIG. illustrates an example operation of the apparatus 100 in accordance with certain aspects of the present disclosure. Figure 1 In the example of FIG. 2, the node N17 is labeled “delay circuit input”; the node N19 is labeled “delay circuit output”; the node N18 is labeled “delay circuit power”; the node N16 is labeled “bypass circuit control”; and the node N21 is labeled “switch circuit control” for reference. Figure 3

[0045] In the example of FIG. 2, the supply voltages VDD1 and VDD2 are both on and at their respective supply voltage levels. The control signal SLP (which can be referred to as a first control signal and can be in a first voltage domain) and the control signal CLAMP (which can be referred to as a second control signal and can be in a second voltage domain) are toggled and trigger operations to reduce current leakage in the supply circuit 102 (e.g., the delay circuit 202 and the bypass circuit 204). Figure 3 At TO, the control signal CLAMP is at logic 0 (e.g., ground), i.e., a state in which the delay circuit 202 and the bypass circuit 204 (e.g., the supply circuit 102) are not turned off. Also, at TO, the control signal SLP is at logic 1 (e.g., at VDD1), i.e., a state in which the delay circuit 202 and the bypass circuit 204 are not turned off. Thus, the input to the switch circuit 206 is at logic 0, and the switch circuit 206 is on and supplies power to the circuit block 122. Figure 2 Figure 2 At T1, the control signal SLP transitions to logic 0 (e.g., ground). As presented below, based on the control signal SLP transitioning to logic 0 and via the delay circuit 202 and the bypass circuit 204, the control circuit 111 disables the switch circuit 206 that supplies power to the circuit block 122. At 32, in response to the control signal SLP transitioning to logic 0, the input to the delay circuit 202 at the node N17 transitions to logic 1. Referring to Figure 2 , in response to the control signal SLP transitioning to logic 0, the control logic-1 214 outputs logic 0 at N14. Based on the signaling at N14, the voltage shifter circuit 216 outputs logic 1 at the node N12. In response to the node N13 transitioning to logic 1, the control logic-2 218 outputs logic 1 at N17 via the NOR gate 222 and the inverter 223.

[0046] Figure 2

[0047] ​​​​At 34, following the input to the delay circuit 202 at node N17 transitioning to logic 1, after the delay through the delay circuit 202, the delay circuit 202 outputs a logic 1 at node N19. At 36, in response to the control signal SLP transitioning to logic 0 (node N14 going to logic 0 and node N13 going to logic 1), the control logic-1 214 outputs a logic 0 at node N18 via the NOR gate 222 to power down the delay circuit 202. For example, by setting node N18 to logic 0, power is disabled to one or more stages in the delay circuit 202 (e.g., a stage among inverters 253_1 through 253_N) (e.g., via the supply voltage VDD2 of the NOR gate 222 of the control logic-2 218). In this way, leakage current of the delay circuit 202 in the standby state is reduced. In this way, in response to the control signal SLP being logic 0, the control circuit 111 powers down the delay circuit 202.

[0048] At 38, in response to the control signal SLP transitioning to logic 0 (node N14 going to logic 0 and node N12 going to logic 1), the control logic-1 214 outputs a logic 1 (e.g., at the supply voltage VDD2) at node N16 via the NOR gates 224 and 225. At 39, in response to node N16 going to logic 1, the bypass circuit 204 outputs a logic 1 at node N21 to the switch circuit 206 to turn off the p-type transistor 258 that powers the circuit block 122. In this way, based on the control signal SLP (which can be referred to as a first control signal) and the control signal CLAMP being de-asserted, the control circuit 111 can be configured to provide signaling on node N16 to bypass the delay circuit 202 and disable the switch circuit 206 that powers the circuit block 122. Further, based on the control signal SLP and the control signal CLAMP being de-asserted, the control circuit 111 can be configured to power down the delay circuit 202.

[0049] As presented above, the control circuit 111 can be configured to provide signaling to a second input (e.g., node N16) to bypass the delay circuit 202 to disable the switch circuit 206 that powers the circuit block 122 based on a first control signal (e.g., the control signal SLP). For example, the control circuit 111 provides a logic 1 on node N16 to disable the switch circuit 206 that powers the circuit block 122 independent of the action of the delay circuit 202. Further, the control circuit 111 can also be configured to power down the delay circuit 202 via the voltage shifter circuit 216 based on the control signal SLP.

[0050] At T2, the control signal CLAMP is asserted (transitioned to logic 1) to implement the functionality presented herein. In response, the VDDl power down circuit 212 of the control circuit 111 powers down the control logic-1 circuit 214. For example, the VDDl power down circuit 212 can turn off the supply voltage VDDl provided to the control logic-1 214 via node N15. As a result, the leakage current of the control circuit 111 can be further reduced in a standby mode (e.g., a mode in which the control circuit 111 is not operating and / or not responsive to certain control signal transitions). With Figure 4 This functionality and other functionality of the control signal CLAMP is further presented. At T3, the control signal CLAMP is transitioned to logic 0 (de-asserted) and, in response, the VDDl power down circuit 212 powers up the control logic-1 214. For example, the VDDl power down circuit 212 provides the supply voltage VDDl via node N15, allowing the control logic-1 214 to operate and / or be responsive to the control signal SLP.

[0051] At T4, the control signal SLP is transitioned to logic 1 (e.g., the supply voltage VDDl). As presented below, based on the control signal SLP being transitioned to logic 1 (e.g., the supply voltage VDDl) and via the delay circuit 202 and the bypass circuit 204, the control circuit 111 enables the switching circuit 206 to power the circuit block 122. At 42, node N18, via which power (e.g., the supply voltage VDD2) is provided to the delay circuit 202, is transitioned to logic 1 to power up the delay circuit 202. For example, in response to the control signal SLP being transitioned to logic 1, the control logic-1 214 outputs a logic 1 onto node N14 and the voltage shifter circuit 216 outputs a logic 0 on node N12. The control logic-2 218 outputs a logic 1 via the NOR gate 222.

[0052] At 44, node N16 (control of the bypass circuit 204) is transitioned to logic 0 to enable the bypass circuit 204 (e.g., the bypass circuit 204 will operate based on node N19 and node N16 being at logic 0). For example, the control logic-2 218 outputs a logic 0 at node N16 via the NOR gates 224 and 225. In some examples, via the voltage shifter circuit 216 and the control logic-2 218, the control circuit 111 can delay the output N16 to become a logic 0 after node N18 is powered up to ensure that node N19 follows node N17. In this way, the possibility of an erroneous state on node N19 is removed.

[0053] At 46, node N17 (the input to delay circuit 202) transitions to logic 0. For example, in response to control signal SLP transitioning to logic 1, control logic-1 214 outputs logic 1 at node N14, and voltage shifter circuit 216 outputs logic 0 at node N13. Control logic-2 218 outputs logic 0 at node N17 via NOR gate 222 and inverter 223. At 48a, delay circuit 202 is powered on via node N18. At 48, node N19 (the output of delay circuit 202) transitions to logic 0 after a delay via delay circuit 202. At 49, in response to node N19 transitioning to logic 0, node N21 transitions to logic 0. For example, based on node N19, bypass circuit 204 outputs logic 0 at node N21 via NOR gate 255 and inverter 257 to turn on the switching circuit 206 that powers circuit block 122. In this way, based on the control signal SLP (e.g., when the control signal CLAMP is not asserted), the control circuit 111 enables the switching circuit 206 to power the circuit block 122 via the delay circuit 202 and the bypass circuit 204. Furthermore, the logic 0 at node N21 can be provided as signaling S103 to the next-stage power supply circuit 104 (e.g., ...). Figure 1 and Figure 5 ).

[0054] Figure 4 The illustrations depict certain aspects of this disclosure. Figure 1 Example operation of device 100 during power-on of the supply voltage. Figure 4 In this diagram, for ease of reference, node N18 is labeled "Delay Circuit Power," and node N16 is labeled "Bypass Circuit Control." In some examples, during the power-up of supply voltages VDD1 and VDD2, device 100 de-energizes delay circuit 202 to reduce leakage current. At P0, supply voltages VDD1 and VDD2 are grounded. At P1, supply voltage VDD2 is powered on, while supply voltage VDD1 remains grounded. At P2, the control signal CLAMP follows supply voltage VDD2 and rises to supply voltage VDD2.

[0055] As an example, the control signal CLAMP is asserted in response to powering on the supply voltage VDD2 to perform at least some of the functions presented below. For example, the control signal CLAMP can be asserted to de-energize the delay circuit 202 and / or disable the switching circuit 206 that powers circuit block 122. At 442, in response to the control signal CLAMP being asserted (e.g., converted to logic 1), node N18 becomes logic 0 (e.g., grounded). For example, in response to the control signal CLAMP being logic 1, control logic 2 outputs logic 0 at node N18 via NOR gate 222, regardless of the control signal SLP. Figure 4The illustration shows the control signal SLP in an indeterminate state, independent of the control circuit 111 that powers off node N18 (and therefore the delay circuit 202). In this way, in response to the logic 1 state of the control signal CLAMP, the control circuit 111 powers off the delay circuit 202, regardless of the control signal SLP.

[0056] At 444, in response to the control signal CLAMP being asserted (e.g., converted to logic 1), node N16 becomes logic 1, causing bypass circuit 204 to disable the switching circuit 206 that powers circuit block 122. For example, refer to... Figure 2 In response to the assertion of the control signal CLAMP, control logic -2 outputs logic 1 at node N16 via gates 224 and 225. In this way, control circuit 111 can be configured to provide signaling to node N16 in response to the assertion of the control signal CLAMP and independently of the control signal SLP, to bypass delay circuit 202 to disable the switching circuit 206 powering circuit block 122. At P3, supply voltage VDD1 is powered on. At 446, control signal SLP is ready to be powered on after supply voltage VDD1 is powered on.

[0057] Figure 5 The illustrations depict certain aspects of this disclosure. Figure 1 Example circuit of the next-stage power supply circuit 104. (See reference) Figure 1 The next-stage power supply circuit 104 can be configured to supply power to the second circuit block 124 based on signaling S103 from the power supply circuit 102. In some examples, the power supply circuit 102 supplying power to circuit block 122 and the next-stage power supply circuit 104 supplying power to the second circuit block 124 can be configured to interleave according to signaling from the control circuit 111. For example, the power supply circuit 102 can be configured to first power on circuit block 122, and then the next-stage power supply circuit 104 powers on the second circuit block 124. In some examples, the control circuit 111 can be configured to simultaneously shut down the power supply circuit 102 supplying power to circuit block 122 and the next-stage power supply circuit 104 supplying power to the second circuit block 124.

[0058] Figure 5 The diagram illustrates a next-stage power supply circuit 104, a second circuit block 124, and a control circuit 111. In some examples, the next-stage power supply circuit 104 may be an instance of power supply circuit 102, and the description relating to power supply circuit 102 may apply to the next-stage power supply circuit 104. The second circuit block 124 may be an instance of circuit block 122, and the description relating to circuit block 122 may apply to the second circuit block 124. Figure 5The next stage power supply circuit 104 can include a second delay circuit 502, a second bypass circuit 504, and / or a second switch circuit 506, as illustrated.

[0059] The second switch circuit 506 can be configured to power the second circuit block 124. As illustrated, the second switch circuit 506 can include a p-type transistor 558. The p-type transistor 558 can be configured to have a source coupled to node N23 and a drain coupled to node N52, and the drain is coupled to the second circuit block 124 via node N52. The p-type transistor 558 can be configured to receive power via node N23 and power the second circuit block 124 via node N52. The p-type transistor 558 can be further configured to have a gate coupled to node N51. The p-type transistor 558 (and thus the second switch circuit 506) can be configured to turn on (or turn off) based on signaling on node N51 to power (or not power) the second circuit block 124.

[0060] The second bypass circuit 504 can be configured to drive the second switch circuit 506 to enable and disable the second switch circuit 506 for powering the second circuit block 124. As illustrated, the second bypass circuit 504 includes an NOR gate 555 and an inverter 557 arranged in series via node N50. The NOR gate 525 can be configured to receive inputs via nodes N59 and N56 and output via node N50. The inverter 557 can be configured to receive input from node N50 and output to the second switch circuit 506 via node N51. For example, the second bypass circuit 504 can be configured to drive the gate of the p-type transistor 558 of the second switch circuit 506 via the inverter 557 to turn on and turn off the p-type transistor 558 to enable and disable the second switch circuit 506 for powering the second circuit block 124.

[0061] The second delay circuit 502 can be configured to delay the second bypass circuit 504 that drives the second switch circuit 506. As illustrated, the second delay circuit 502 includes N number of inverters 553_1 to 553_N arranged in series. For example, the output of inverter 553_1 can be provided as input to inverter 553_2, and so on. The inverters 553_1 to 553_N can be configured to be powered via node N58. The second delay circuit 502 can be configured to receive signaling (see Figure 2 , which can include Figure 1 S103) via node N21, delay the received signaling, and output the delayed signaling to the second bypass circuit 504 via node N59.

[0062] As with the first stage power supply circuit 104, the second stage power supply circuit 104 can be configured to power the second circuit block 124 based on the signaling received from the first stage power supply circuit 104, as illustrated. Figure 1The second switch circuit 506 can be configured to power the second circuit block 124 as presented by the power supply circuit 102. The second bypass circuit 504 can be configured to drive the second switch circuit 506 to enable and disable the second switch circuit 506 to power the second circuit block 124 based on the control signal SLP and the control signal CLAMP. For example, the control circuit 111 can be configured to cause the second bypass circuit 504 to drive the second switch circuit 506 to disable the second switch circuit 506 to power the second circuit block 124, bypassing the second delay circuit 502 based on the control signal CLAMP. For example, the control circuit 111 can be configured to output a logic 0 (e.g., ground) on the node N58 and a logic 1 on the node N56 in response to the control signal CLAMP being at a logic 1 (e.g., the supply voltage VDD2). The node N58 being at a logic 0 de-energizes the second delay circuit 502 to reduce leakage current when the next stage power supply circuit 104 is in a standby mode (e.g., inactive or not responsive to certain control signals). The node N56 being at a logic 1 causes the second bypass circuit 504 to output a logic 1 on the node N51 and disable the second switch circuit 506 to power the second circuit block 124.

[0063] Further, the second delay circuit 502 can be configured to delay signaling to the second bypass circuit 504 that is based on the control signal SLP. For example, the second delay circuit 502 can be configured to receive signaling from the power supply circuit 102 on the node N21 (see Figure 2 ), and delay the received signaling via the N-stage inverters 553_1 through 553_N. As presented by the power supply circuit 102 with reference to Figure 2 , the signaling on the node N21 is based on (e.g., controlled by) the control signal SLP. The second delay circuit 502 can also be configured to output the delayed signaling to the second bypass circuit 504 (via the node N59) and the second switch circuit 506 (via the node N51). In this way, the control circuit 111 can also be configured to enable and disable the second switch circuit 506 to power the second circuit block 124 based on the control signal SLP and via the second delay circuit 502 and the second bypass circuit 504.

[0064] Further, the second bypass circuit 504 can also be configured to drive the second switch circuit 506 to enable the second switch circuit 506 to power the second circuit block 124 conditioned on the bypass circuit 204 driving the switch circuit 206 to enable the switch circuit 206 to power the circuit block 122. For example, with reference to Figure 2Bypass circuit 204 can be configured to output logic 0 to node N21 to enable switching circuit 206 that powers circuit block 122. Second delay circuit 502 can be configured to receive logic 0 on node N21, delay the signaling, and provide logic 0 on node N59 to second bypass circuit 504. In response, second bypass circuit 504 can be configured to output logic 0 to second switching circuit 506 via node N51, enabling second switching circuit 506 and powering it.

[0065] As presented above, the second delay circuit 502 can be configured to delay the activation of the second switch circuit 506 that powers the second circuit block 124 when the switch circuit 206 powers the circuit block 122. For example, the second delay circuit 502 can be configured to receive N21 (from...) Figure 2 The signaling received on node N56 is used to delay the output to node N59. The second bypass circuit 504 can be configured to enable the second switching circuit 506 powering the second circuit block 124 in response to a signaling received on node N59. The second delay circuit 502 can also be configured to be de-energized, for example, via node N58. For example, the second delay circuit 502 can be configured to be powered and therefore de-energized via node N58. The second bypass circuit 504 can also be configured to bypass the second delay circuit 502 to disable the second switching circuit 506 powering the second circuit block 124. For example, the second bypass circuit 504 can be configured to disable the second switching circuit 506 powering the second circuit block 124 in response to a logic 1 on node N56, independent of the signaling on node N59 (and therefore independent of the second delay circuit 502).

[0066] Figures 6-8 The illustration shows a portion of a method for reducing leakage current when supplying power to a circuit block (e.g., circuit block 122 or second circuit block 124) according to certain aspects of this disclosure. Figures 6-8 The operation can be performed by, for example, using Figures 1-5 The presented device 100 implements this. Arrows indicate certain relationships in the operation, but not necessarily sequential relationships. At 610, the circuit block is powered by a switching circuit. For example, refer to... Figure 2 The switching circuit 206 includes a p-type transistor 258. The bypass circuit 204 turns on the p-type transistor 258 via node N21 to supply the supply voltage VDD2 at node N23 to the switching circuit 206.

[0067] At 620, a bypass circuit drives a switching circuit based on a first control signal and a second control signal to enable and disable the switching circuit supplying power to the circuit block. For example, refer to... Figure 2The bypass circuit 204 drives the switch circuit 206 via node N21 to turn on and off the p-type transistor 258. The bypass circuit 204 includes an NOR gate 255 that receives inputs from nodes N16 and N19, the inputs on N16 and N19 are based on a control signal SLP and a control signal CLAMP. For example, based on the control signal SLP and the control signal CLAMP, the control circuit 111 outputs to the NOR gate 255 via node N16 and via node N19 (via the delay circuit 202).

[0068] At 630, signaling to the bypass circuit is delayed by a delay circuit, the signaling is based on a first control signal. For example, the delay circuit 202 delays the signaling on node N17 and provides the delayed signaling to the bypass circuit 204 via node N19. At 640, a switch circuit that supplies power to a circuit block is enabled and disabled by a control circuit based on the first control signal. For example, when the control signal CLAMP is at logic 0, the control circuit 111 outputs to node N17 based on the control signal SLP (see Figure 2 ). For example, in response to the control signal SLP being at logic 0 (and the control signal CLAMP being at logic 0), the control circuit 111 outputs a logic 1 to node N17. In response to the control signal SLP being at logic 1 (and the control signal CLAMP being at logic 0), the control circuit 111 outputs a logic 0 to node N17. In response to node N17 being at logic 0, the bypass circuit 204 drives the switch circuit 206 to enable the switch circuit 206 that supplies power to the circuit block 122. In response to node N17 being at logic 1, the bypass circuit 204 drives the switch circuit 206 to disable the switch circuit 206 that supplies power to the circuit block 122.

[0069] At 650, the bypass circuit is caused by the control circuit to drive the switch circuit to disable the switch circuit that supplies power to the circuit block, the delay circuit is bypassed. At 660, in response to a first state of a second control signal and independent of the first control signal, the delay circuit is powered down by the control circuit and the bypass circuit is caused by the control circuit to drive the switch circuit to disable the switch circuit that supplies power to the circuit block. For example, in response to the control signal CLAMP being at logic 1, the control circuit 111 outputs a logic 1 to node N16, forcing the bypass circuit 204 to output a logic 1 to node N21 (see Figure 2 ). In response, the switch circuit 206 that supplies power to the circuit block 122 is disabled independent of the signaling on node N19, the delay circuit 202 is bypassed. Further, in response to the control signal CLAMP being at logic 1, the control circuit 111 outputs a logic 0 to node N18 to power down the delay circuit 202.

[0070] At 670, in response to the second state of the second control signal, the bypass circuit is caused to drive the switch circuit to enable the switch circuit that supplies power to the circuit block by the control circuit based on the first control signal and via the delay circuit. For example, in response to the control signal CLAMP being at logic 0, the control circuit 111 outputs logic 0 at node N16 to enable the bypass circuit 204 to operate based on signaling on node N19 (see Figure 2 ) with the control signal SLP at logic 1, the control circuit 111 outputs logic 1 on node N18 to power up the delay circuit 202, and the control circuit 111 outputs logic 0 on node N17. The delay circuit 202 delays the signaling on node N17 and outputs logic 0 on node N19 to the bypass circuit 204. In response, the bypass circuit 204 drives the switch circuit 206 via node N21 to enable the switch circuit 206 that supplies power to the circuit block 122. By powering up the delay circuit and enabling the switch circuit 206 that supplies power to the circuit block via the delay circuit, the delay circuit and the switch circuit are powered up in a staggered manner, thereby reducing the peak of inrush current.

[0071] At 680, in response to the second state of the second control signal and based on the first control signal, the bypass circuit is caused to drive the switch circuit to disable the switch circuit that supplies power to the circuit block by the control circuit, and the delay circuit is caused to power down by the control circuit. For example, in response to the control signal CLAMP being at logic 0 and based on the control signal SLP being at logic 0, the control circuit 111 outputs logic 1 at node N16 to cause the bypass circuit 204 to output logic 1 on node N21 (see Figure 2 ). Node N21 at logic 1 turns off the switch circuit 206, and thus, the bypass circuit 204 drives the switch circuit 206 to disable the switch circuit 206 that supplies power to the circuit block 122. Further, with the control signal CLAMP at logic 0 and the control signal SLP at logic 0, the control circuit 111 outputs logic 0 on node N18 to power down the delay circuit 202. In summary, in response to the control signal CLAMP being at logic 0, the bypass circuit 204 drives the switch circuit 206 to disable the switch circuit 206 that supplies power to the circuit block 122, and the delay circuit is powered down based on the control signal SLP being at logic 0.

[0072] At 710, in response to the state of the second control signal and independent of the first control signal, the first portion of the control circuit is powered down. For example, with reference to Figure 2The control circuit 111 includes control logic-1 214 (e.g., a first portion). The power down circuit 212 provides power from VDD1 at node N16 to the control logic-1 214 via node N15. In response to the control signal CLAMP being at a logic 1, the power down circuit 212 turns off power to the control logic-1 214, powering down the control logic-1 214. For example, the power down circuit 212 can include a p-type transistor controlled by the control signal CLAMP.

[0073] At 720, signaling from the delay circuit and the control circuit is received by the gate of the bypass circuit, directly or indirectly. At 730, signaling from the delay circuit and signaling from the control circuit are received by the gate of the bypass circuit directly, the signaling from the delay circuit instructing the bypass circuit to drive the switch circuit to enable and disable the switch circuit powering the circuit block based on the first control signal, the signaling from the control circuit causing the bypass circuit to drive the switch circuit to disable the switch circuit powering the circuit block in response to a first state of the second control signal and independent of the first control signal. For example, see Figure 2 The bypass circuit 204 includes an NAND gate 255 that receives signaling from the delay circuit 202 on node N19 and signaling from the control circuit 111 on node N16. In other examples, the NAND gate 255 can receive the signaling on nodes N16 and N19 via intermediate circuitry (not shown). As presented with 710, the signaling from the delay circuit 202 on node N19 instructs the bypass circuit 204 to drive the switch circuit 206 to enable and disable the switch circuit 206 powering the circuit block 122 based on the control signal SLP. As presented with 660, the signaling from the control circuit 111 on node N16 causes the bypass circuit 204 to drive the switch circuit 206 to disable the switch circuit 206 powering the circuit block independent of the control signal SLP in response to a logic 1 of the control signal CLAMP.

[0074] At 810 (e.g., after operation 670), the second circuit block is powered by the second switch circuit. For example, see Figure 5 The second switch circuit 506 powers the second circuit block 124. At 820, the second switch circuit is driven by the second bypass circuit to enable and disable the second switch circuit powering the second circuit block based on the first control signal and the second control signal. For example, see Figure 5The second bypass circuit 504 drives the second switch circuit 506 via node N51 to turn on and off the p-type transistor 558. The second bypass circuit 504 includes an NOR gate 555 that receives inputs from nodes N56 and N59 (e.g., first and second inputs of the second bypass circuit 504, respectively), the inputs on N56 and N59 are based on the control signal SLP and the control signal CLAMP. For example, based on the control signal SLP and the control signal CLAMP, the control circuit 111 outputs to the NOR gate 555 via node N56 and via node N59 (via the second delay circuit 502).

[0075] At 830, signaling to the second bypass circuit is delayed by the second delay circuit, the signaling is based on the output of the bypass circuit. For example, the second delay circuit 502 delays the signaling on node N21 and provides the delayed signaling to the second bypass circuit 504 via node N59. At 840, the second switch circuit that supplies power to the second circuit block is enabled and disabled by the control circuit based on the first control signal. For example, when the control signal CLAMP is at logic 0, the control circuit 111 outputs to node N21 based on the control signal SLP (see Figure 5 ). For example, in response to the control signal SLP being at logic 0 (and the control signal CLAMP being at logic 0), the control circuit 111 outputs a logic 1 to node N21. In response to the control signal SLP being at logic 1 (and the control signal CLAMP being at logic 0), the control circuit 111 outputs a logic 0 to node N21. In response to node N21 being at logic 0, the second bypass circuit 504 drives the second switch circuit 506 to enable the second switch circuit 506 that supplies power to the second circuit block 124. In response to node N21 being at logic 1, the second bypass circuit 504 drives the second switch circuit 506 to disable the second switch circuit 506 that supplies power to the second circuit block 124.

[0076] At 850, the second bypass circuit is caused by the control circuit to drive the second switch circuit to disable the second switch circuit that supplies power to the second circuit block, the second delay circuit is bypassed. For example, in response to the control signal CLAMP being at logic 1, the control circuit 111 outputs a logic 1 to node N56, forcing the second bypass circuit 504 to output a logic 1 to node N51 (see Figure 5 ). In response, the second switch circuit 506 that supplies power to the second circuit block 124 is disabled, independent of the signaling on node N59, the second delay circuit 502 is bypassed. Further, in response to the control signal CLAMP being at logic 1, the control circuit 111 outputs a logic 0 to node N58 to power down the second delay circuit 502.

[0077] At 860, the second switch circuit is driven by the second bypass circuit to enable the second switch circuit to power the second circuit block, conditional on the switch circuit being driven by the bypass circuit to enable the switch circuit to power the circuit block. For example, the bypass circuit 204 drives the switch circuit 206 by outputting a logic 0 on node N21 to enable the switch circuit 206 to power the circuit block 122 (see Figure 2 ). In Figure 5 , the second delay circuit 502 receives signaling on N21 (from Figure 2 ) and delays an output onto node N59 based on the signaling. Responsive to node N59 (and node N21) being at a logic 0, the second delay circuit 502 drives the second switch circuit 506 to enable the second switch circuit 506 to power the second circuit block 124.

[0078] Figures 9-11 FIG. illustrates portions of another method of reducing leakage current when powering a circuit block (e.g., the circuit block 122 or the second circuit block 124), in accordance with certain aspects of the present disclosure. Figures 9-11 The operations of FIG. can be implemented, for example, by the apparatus 100 presented with reference to Figures 1-5 . Arrows indicate certain relationships among the operations but not necessarily sequenced relationships. At 910, a circuit block is powered by a switch circuit. For example, referring to Figure 2 , the switch circuit 206 includes a p-type transistor 258. The bypass circuit 204 turns on the p-type transistor 258 via node N21 to provide a power supply voltage VDD2 on node N23 to the switch circuit 206.

[0079] At 920, a delay circuit is powered down. At 980, the delay circuit is powered down by a control circuit based on a first control signal and a second control signal. At 990, the delay circuit is powered down by the control circuit via a voltage shifter circuit. For example, referring to Figure 2 , the control signal CLAMP (e.g., the second control signal) being asserted (e.g., to a logic 1) causes the control circuit 111 to output a logic 0 onto node N18 via the NAND gate 222 to power down the delay circuit 202. Further, when the control signal CLAMP is not asserted, the control circuit 111 can power down the delay circuit 202 based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP being at a logic 0 causes the control circuit 111 to output a logic 0 onto node N18 via the voltage shifter circuit 216 and the NAND gate 222 to power down the delay circuit 202.

[0080] At 930, the delay circuit is bypassed by the bypass circuit to disable the switch circuit that supplies power to the circuit block. At 950, the delay circuit is bypassed by the bypass circuit based on signaling received via a second input of the bypass circuit to disable the switch circuit that supplies power to the circuit block. At 960, the signaling on the second input to bypass the delay circuit to disable the switch circuit that supplies power to the circuit block is provided by the control circuit based on the first control signal and the second control signal. At 970, the signaling on the second input is provided via a voltage shifter circuit of the control circuit. For example, referring to Figure 2 the control signal CLAMP (e.g., the second control signal) is asserted (e.g., is logic 1) to cause the control circuit 111 to output logic 1 onto node N16 (e.g., the second input of the bypass circuit 204) via gates 224 and 225. In response to the logic 1 on node N16, the bypass circuit 204 bypasses the delay circuit 202 (e.g., operates independent of the delay circuit 202 or without the delay circuit 202) and disables the switch circuit 206 that supplies power to the circuit block 122 by outputting logic 1 onto node N21. Further, when the control signal CLAMP is not asserted, the control circuit 111 can output logic 1 onto node N16 based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP at logic 0 causes the control circuit 111 to output logic 1 onto node N16 via the voltage shifter circuit 216 and gates 224 and 225 to bypass the delay circuit 202 while disabling the switch circuit 206 that supplies power to the circuit block 122.

[0081] At 940, the switch circuit that supplies power to the circuit block is enabled via a first input of the bypass circuit by the delay circuit. For example, when the control signal CLAMP is de-asserted (e.g., is logic 0), the control circuit 111 delays the switch circuit 206 that supplies power to the circuit block 122 via the delay circuit 202 and node N19 (e.g., the first input of the bypass circuit 204). For example, the control signal SLP at logic 1 causes the control circuit 111 to output logic 0 at node N17 via the voltage shifter circuit 216 and gates 222 and 223. The delay circuit 202 delays from node N17 and then outputs logic 0 onto node N19 (the first input). The switch circuit 206 is thus enabled to supply power to the circuit block 122.

[0082] At 1010 (e.g., at Figure 9the second control signal is asserted and independent of the first control signal, by the control circuitry. At 1020, in response to the second control signal being asserted and independent of the first control signal, the delay circuit is de-energized by the control circuitry. For example, the control signal CLAMP (e.g., the second control signal) being asserted (e.g., as a logic 1) causes the control circuitry 111, via gate 224 and gate 225, to output a logic 1 onto node N16 (e.g., a second input of the bypass circuit 204). In response to the logic 1 on node N16, the bypass circuit 204 bypasses the delay circuit 202 (e.g., operates independent of or regardless of the delay circuit 202) and disables the switch circuit 206 that supplies power to the circuit block 122 by outputting a logic 1 to node N21. Further, with reference to Figure 2 the control signal CLAMP (e.g., the second control signal) being asserted (e.g., as a logic 1) causes the control circuitry 111, via NAND gate 222, to output a logic 0 onto node N18 to de-energize the delay circuit 202 independent of the control signal SLP.

[0083] At 1030, in response to the second signal not being asserted and based on the first control signal, the switch circuit that supplies power to the circuit block is enabled by the control circuitry via the delay circuit. For example, with reference to Figure 2 the control signal CLAMP not being asserted allows the control circuitry to respond to the control signal SLP to, for example, enable the switch circuit 206 that supplies power to the circuit block 122 via the delay circuit 202. For example, when the control signal CLAMP is not asserted, the control circuitry 111 can output a logic 1 onto node N16 based on the control signal SLP (e.g., the first control signal). When the control signal CLAMP is de-asserted (e.g., as a logic 0), the control circuitry 111 delays the switch circuit 206 that supplies power to the circuit block 122 via the delay circuit 202 and node N19 (e.g., a first input of the bypass circuit 204). For example, the control signal SLP at a logic 1 causes the control circuitry 111, via voltage shifter circuit 216 and gates 222 and 223, to output a logic 0 at node N17. The delay circuit 202 delays from node N17 and then outputs a logic 0 to node N19 (the first input). The switch circuit 206 is thus enabled to supply power to the circuit block 112.

[0084] At 1040, in response to the second control signal not being asserted and based on the first control signal, signaling is provided by the control circuit onto a second input of the bypass circuit for bypassing the delay circuit to disable the switching circuit that supplies power to the circuit block. For example, when the control signal CLAMP is not asserted, the control circuit 111 can output a logic 1 onto the node N16 based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP being at a logic 0 causes the control circuit 111 to output a logic 1 onto the node N16 via the voltage shifter circuit 216 and the gates 224 and 225 to bypass the delay circuit 202 while disabling the switching circuit 206 that supplies power to the circuit block 122.

[0085] At 1050, in response to the second control signal not being asserted and based on the first control signal, the second delay circuit is de-energized by the control circuit. For example, when the control signal CLAMP is not asserted, the control circuit 111 can de-energize the delay circuit 202 based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP being at a logic 0 causes the control circuit 111 to output a logic 0 onto the node N18 via the voltage shifter circuit 216 and the NOR gate 222 to de-energize the delay circuit 202.

[0086] At 1110 (e.g., after 990 of FIG. 9), the second circuit block is powered by the second switching circuit. For example, referring to Figure 9 At 1120, under conditions in which the switching circuit is powering the circuit block, the second delay circuit delays enabling the second switching circuit that powers the second circuit block. For example, referring to Figure 5 The second switching circuit 506 includes a p-type transistor 558. The second bypass circuit 504 turns on the p-type transistor 558 via the node N51 to provide the supply voltage VDD2 on the node N23 to the second switching circuit 506. At 1120, under conditions in which the switching circuit is powering the circuit block, the second delay circuit delays enabling the second switching circuit that powers the second circuit block. For example, referring to Figure 5 The second delay circuit 502 receives signaling on N21 (from the first delay circuit 201) and delays output onto the node N59 based on the signaling. In response to the signaling received on the node N59, the second bypass circuit 504 enables the second switching circuit 506 that powers the second circuit block 124. Figure 2 The second delay circuit 502 receives signaling on N21 (from the first delay circuit 201) and delays output onto the node N59 based on the signaling. In response to the signaling received on the node N59, the second bypass circuit 504 enables the second switching circuit 506 that powers the second circuit block 124.

[0087] At 1130, the second delay circuit is de-energized. For example, referring to Figure 5, the control signal CLAMP (e.g., the second control signal) is asserted (e.g., to logic 1) to cause the control circuit 111 to output a logic 0 onto the node N58 via the NOR gate 222 to de-energize the second delay circuit 502. At 1140, the second delay circuit is bypassed by the second bypass circuit to disable the second switch circuit that supplies power to the second circuit block. For example, referring to Figure 5 , the control signal CLAMP (e.g., the second control signal) is asserted (e.g., to logic 1) to cause the control circuit 111 to output a logic 1 onto the node N56 (e.g., a second input of the second bypass circuit 504) via the NOR gate 222. In response to the logic 1 on the node N56, the second bypass circuit 504 bypasses (e.g., operates without or independent of) the second delay circuit 502 and disables the second switch circuit 506 that supplies power to the second circuit block 124 by outputting a logic 1 onto the node N51.

[0088] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of the group consisting of A, B, and C,” “one or more of the group consisting of A, B, and C,” and “A, B, and / or C or any combination thereof’ include in various embodiments any combination of A, B, and / or C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of the group consisting of A, B, and C,” “one or more of the group consisting of A, B, and C,” and “A, B, and / or C or any combination thereof’ can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combination can contain one or more member(s) of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module,” “mechanism,” “element,” “device,” and the like can not be a substitute for the word “means.” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”

Claims

1. An apparatus comprising: The switching circuit is configured to supply power to the circuit block; The delay circuit is configured as follows: Delay the activation of the switching circuit that powers the circuit block, and Power outage; A bypass circuit is configured to bypass the delay circuit to disable the switching circuit that powers the circuit block. The bypass circuit includes a first input and a second input. The delay circuit is configured to delay the activation of the switching circuit supplying power to the circuit block via the first input, and The bypass circuit is further configured to: based on signaling received via the second input, bypass the delay circuit to disable the switching circuit that supplies power to the circuit block; as well as A control circuit configured to provide the signaling to a second input based on a first control signal and a second control signal, to bypass the delay circuit to disable the switching circuit supplying power to the circuit block. in: The control circuit further includes a voltage shifter circuit and is configured to provide the signaling to the second input via the voltage shifter circuit, or The control circuit is further configured to de-energize the delay circuit based on the first control signal and the second control signal.

2. The apparatus of claim 1, wherein the bypass circuit includes a gate coupled to the first input and the second input.

3. The apparatus of claim 1, wherein the control circuit further comprises a voltage shifter circuit; the control circuit is further configured to de-energize the delay circuit via the voltage shifter circuit.

4. The apparatus according to claim 1, wherein the first control signal is in a first voltage domain having a first supply voltage, the second control signal is in a second voltage domain having a second supply voltage, and the second supply voltage is different from the first supply voltage.

5. The apparatus of claim 1, wherein the control circuit is further configured to: in response to the assertion of the second control signal and independent of the first control signal, provide the signaling to the second input to bypass the delay circuit to disable the switching circuit supplying power to the circuit block.

6. The apparatus of claim 5, wherein the control circuit is further configured to: de-energize the delay circuit in response to the assertion of the second control signal and independently of the first control signal.

7. The apparatus of claim 6, wherein the control circuit is further configured to: enable the switching circuit supplying power to the circuit block via the delay circuit in response to the second control signal not being asserted and based on the first control signal.

8. The apparatus according to claim 7, wherein the control circuit is further configured to: The signaling is provided on the second input to bypass the delay circuit, thereby disabling the switching circuit that powers the circuit block. In response to the second control signal not being asserted and based on the first control signal, the delay circuit is de-energized.

9. The apparatus according to claim 5, wherein the first control signal is in a first voltage domain having a first supply voltage, and the second control signal is in a second voltage domain having a second supply voltage, wherein the second supply voltage is different from the first supply voltage.

10. The apparatus of claim 9, wherein the second control signal is asserted in response to powering on the second supply voltage.

11. The apparatus according to claim 1, comprising: The second switching circuit is configured to supply power to the second circuit block; The second delay circuit is configured as follows: Under the condition that the switching circuit supplies power to the circuit block, the activation of the second switching circuit supplying power to the second circuit block is delayed, and Power outage; A second bypass circuit is configured to bypass the second delay circuit to disable the second switching circuit that powers the second circuit block.

12. The apparatus of claim 1, comprising a device selected from the group consisting of a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, the device including the switching circuit, the circuit block, the bypass circuit, and the delay circuit.

13. A method for reducing leakage current, comprising: The circuit block is powered by a switching circuit; Disconnect the power from the delay circuit; The delay circuit is bypassed by a bypass circuit to disable the switching circuit that powers the circuit block; The switching circuit that supplies power to the circuit block is activated delayed by the delay circuit via the first input of the bypass circuit; Based on the signaling received via the second input of the bypass circuit, the delay circuit is bypassed by the bypass circuit to disable the switching circuit that supplies power to the circuit block; Based on the first control signal and the second control signal, the control circuit provides the signaling at the second input to bypass the delay circuit to disable the switching circuit that supplies power to the circuit block; as well as The signaling is provided at the second input via the voltage shifter circuit of the control circuit, or the delay circuit is powered off by the control circuit based on the first control signal and the second control signal.

14. The method of claim 13, wherein the bypass circuit includes a gate coupled to the first input and the second input.

15. The method of claim 13, further comprising: The delay circuit is de-energized by the control circuit via its voltage shifter circuit.

16. The method according to claim 13, wherein the first control signal is in a first voltage domain having a first supply voltage, and the second control signal is in a second voltage domain having a second supply voltage, wherein the second supply voltage is different from the first supply voltage.

17. The method of claim 13, further comprising: In response to the assertion of the second control signal and independent of the first control signal, the control circuit provides the signaling at the second input to bypass the delay circuit to disable the switching circuit that powers the circuit block.

18. The method of claim 17, further comprising: In response to the assertion of the second control signal and independent of the first control signal, the control circuit de-energizes the delay circuit.

19. The method of claim 18, further comprising: In response to the second control signal not being asserted and based on the first control signal, the control circuit enables the switching circuit that supplies power to the circuit block via the delay circuit.

20. The method of claim 19, further comprising: In response to the second control signal not being asserted and based on the first control signal, the control circuit provides the signaling to the second input of the bypass circuit to bypass the delay circuit to disable the switching circuit that supplies power to the circuit block; as well as In response to the second control signal not being asserted and based on the first control signal, the control circuit de-energizes the delay circuit.

21. The method according to claim 17, wherein the first control signal is in a first voltage domain having a first supply voltage, and the second control signal is in a second voltage domain having a second supply voltage, wherein the second supply voltage is different from the first supply voltage.

22. The method of claim 21, wherein the second control signal is asserted in response to powering on the second supply voltage.

23. The method of claim 13, comprising: The second circuit block is powered by the second switching circuit; Under the condition that the switching circuit supplies power to the circuit block, the second delay circuit delays the activation of the second switching circuit that supplies power to the second circuit block; Power off the second delay circuit; The second delay circuit is bypassed by the second bypass circuit to disable the second switching circuit that supplies power to the second circuit block.

Images