Configurable resistivity for lines in memory devices

Abstract

This application is directed to configurable resistivity of lines in memory devices. For example, metal lines at different levels of a memory device can be oxidized to different degrees so that the lines at different levels of the memory device have different resistivities. This can allow the resistivity of the lines to be adjusted on a level-by-level basis without having to change the manufacturing techniques and related parameters used to initially form the lines at the different levels, which can have benefits at least with respect to reducing cost and complexity. The lines can be oxidized to a controlled degree using a dry or wet process.

Description

[0001] Cross-reference

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2021 / 012301, filed January 6, 2021, entitled “Configurable Resistivity for Lines in a Memory Device” by Banerjee et al., claiming priority to U.S. Patent Application No. 16 / 781,975, filed February 4, 2020, entitled “Configurable Resistivity for Lines in a Memory Device” by Banerjee et al., and each of these applications is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to configurable resistivity of lines used in memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, typically represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states into the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. Even in the absence of an external power supply, non-volatile memory (such as FeRAM) can maintain its stored logic state for an extended period of time. Volatile memory devices (such as DRAM) may lose their stored state when disconnected from an external power supply. Summary of the Invention

[0006] A method is described. The method may include: forming a first set of access lines for a memory device; oxidizing the first set of access lines to a first degree; forming a second set of access lines for the memory device after oxidizing the first set of access lines; and oxidizing the second set of access lines to a second degree.

[0007] An apparatus is described. The apparatus may include: a first memory cell stack coupled to a first set of access lines, wherein each of the first set of access lines includes a metal oxide having a first thickness; and a second memory cell stack above the first memory cell stack, wherein the second memory cell stack is coupled to a second set of access lines, and wherein each of the second set of access lines includes a metal oxide having a second thickness.

[0008] A method is described. The method may include: forming a plurality of memory cell stacks; forming a plurality of access line sets, wherein each of the plurality of access line sets is coupled to at least one of the plurality of memory cell stacks; and oxidizing the access line sets included in the plurality of access line sets. Attached Figure Description

[0009] Figure 1 An example memory device is shown that supports configurable resistivity of lines in a memory array, according to the examples disclosed herein.

[0010] Figure 2 Examples of memory arrays supporting configurable resistivity of lines in a memory array are shown, based on the examples disclosed herein.

[0011] Figure 3 A flowchart illustrating an example method for configuring the resistivity of lines in a memory array, based on the examples disclosed herein.

[0012] Figure 4 A flowchart illustrating an example method for configuring the resistivity of lines in a memory array, based on examples disclosed herein.

[0013] Figure 5 A flowchart is shown illustrating a method for supporting the configuration of resistivity for lines in a memory array, based on examples disclosed herein.

[0014] Figure 6 A flowchart is shown illustrating a method for supporting the configuration of resistivity for lines in a memory array, based on examples disclosed herein.

[0015] Figure 7 A flowchart is shown illustrating a method for supporting the configuration of resistivity for lines in a memory array, based on examples disclosed herein.

[0016] Figure 8 A flowchart is shown illustrating a method for supporting the configuration of resistivity for lines in a memory array, based on the examples disclosed herein. Detailed Implementation

[0017] Accessing a memory cell (e.g., during a read or write operation) may involve applying a non-zero voltage across the memory cell to read (e.g., sense) the logic state stored in the memory cell or write (e.g., program) the memory cell to store a desired logic state. Memory cells within an array may be coupled to different access lines and located at the intersections of said access lines; therefore, accessing a memory cell may involve applying a corresponding voltage to the different access lines coupled to the memory cell. Each access line may be coupled to a corresponding driver (e.g., through one or more vias or other interconnects, wherein the driver is located outside the array), and the distance of the current path (signal path) between the memory cell and the driver for the access line may be referred to as the electrical distance (ED) of the memory cell, at least in the context of the access line or driver.

[0018] Memory cells with relatively large edge counts (EDs) are called far memory cells, and memory cells with relatively small edge counts (EDs) are called near memory cells. Within an array, multiple memory cells can be coupled to each individual access line. For example, memory cells can be arranged in rows and columns, where each row of memory cells is coupled to a corresponding row line (which may also be called a word line), and each column of memory cells is coupled to a corresponding column line (which may also be called a digital line or bit line).

[0019] For distant memory cells coupled to access lines, it may be necessary to configure the access lines to have a relatively low resistivity. A relatively low resistivity of the access lines can, for example, reduce the amount of drive current required to access the distant memory cell. However, for near memory cells, it may be necessary to configure the access lines to have a relatively high resistivity. A relatively high resistivity of the access lines can, for example, reduce the intensity (amplitude, magnitude) of current spikes (e.g., transient currents) passing through the near memory cell when accessing it (e.g., charge accumulation due to parasitic capacitance within the array, which can be discharged through the memory cell when it is conducting) and thus extend the lifetime (reduce losses) of the near memory cell. Therefore, for a given access line, the desired (target) resistivity can be determined as a compromise (middle, midpoint, sweet spot) value based on competing considerations between the distant and near memory cells coupled to the access line.

[0020] Some memory arrays may contain multiple access line levels. For example, each memory cell stack may contain a collection of memory cells arranged in a two-dimensional (2D) array (e.g., arranged as rows and columns in a plane), and multiple memory cell stacks may be manufactured or otherwise arranged (e.g., stacked) on top of each other. Alternatively, in the context of a single memory cell stack, some access lines may be located below the memory cells of the stack, while others may be located above the memory cells of the stack. The desired resistivity of the access lines may depend on the memory array level in which the access lines are located, because access lines at different levels may be located at different distances from their corresponding drivers and therefore at different EDs. For example, if the drivers are located below the array, then access lines at higher array levels may be farther from their corresponding drivers than access lines at lower array levels. Therefore, in such instances, the minimum and maximum EDs of memory cells coupled to higher access lines will be larger relative to the minimum and maximum EDs of memory cells coupled to lower access lines. In addition, multi-level arrays may be prone to variations or defects because different aspects of the stacks can be manufactured independently, and parasitic capacitance associated with the array and related problems associated with transient currents may become more severe as the number of layers in the array increases.

[0021] In light of the foregoing, or for other reasons that may be understood by one of ordinary skill in the art, it may be necessary to configure (adjust) access lines at different memory array levels to have different resistivities (e.g., access lines at higher array levels have lower resistivities than access lines at lower array levels to compensate for access lines at higher levels that are further from their associated drivers). However, due to cost, complexity, or other considerations, it may also be necessary to manufacture access lines at different memory array levels using the same materials and the same initial target dimensions. For example, changing the initial cross-sectional area (e.g., width or height, thickness) of access lines at different levels may provide various performance benefits, but may also have associated cost or complexity-related drawbacks.

[0022] However, as described herein, different access lines at different memory array levels can be configured (adjusted, regulated) to have different resistivities by oxidizing the access lines at different levels to different degrees. For example, access lines at different array levels can initially be formed to have the same resistivity (e.g., the same material, the same thickness), so the same manufacturing process can be used in two levels related to the formation of the access lines. However, the access lines at one level can be oxidized to a greater degree than the access lines at the other level, so that the more oxidized access lines have higher resistivity. Oxidation can be achieved using, for example, wet or dry techniques, and the resistivity of the access lines at a given level can be configured (controlled, adjusted, regulated) based on controlling the degree of oxidation.

[0023] The features of the present invention are initially described in reference to Figure 1 and 2 The example memory array is described in the context of the example. See also: Figures 3 to 8 The various process flows and flowcharts described further illustrate and describe these and other features of the invention.

[0024] Figure 1 An example memory device 100 is shown, which supports configurable resistivity of lines in a memory device according to the examples disclosed herein. The memory device 100 may also be referred to as an electronic memory device. Figure 1 This is an illustrative representation of the various components and features of the memory device 100. Therefore, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships, not their actual physical locations within the memory device 100. Furthermore, although included in... Figure 1 Some elements are marked with numerical indicators, while other corresponding elements are not marked, but the elements are the same or will be understood to be similar in order to improve the visibility and clarity of the depicted features.

[0025] exist Figure 1 In an illustrative example, memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 programmable to store different states. In some instances, each memory cell 105 is programmable to store one of two states represented as logic 0 and logic 1, and thus stores one bit of information. In some instances, memory cells 105 may be configured to store more than one of two logic states, and thus store more than one bit of information.

[0026] 3D memory array 102 may comprise two or more two-dimensional (2D) memory arrays formed on top of each other. Compared to 2D arrays, this increases the number of memory cells that can be placed or formed on a single die or substrate, thereby reducing manufacturing costs or increasing the performance of the memory device, or both. Memory array 102 may comprise two stacks (hierarchies) of memory cells 105 and can therefore be considered a 3D memory array; however, the number of stacks is not limited to two and may in some cases be one or more. Each stack may be aligned or positioned such that the memory cells 105 in one stack can be aligned (precisely aligned, overlapped, or substantially aligned) with the memory cells in another stack, thereby forming a memory cell stack 145.

[0027] In some instances, memory cell 105 may be a self-select memory cell, a phase-change memory (PCM) cell, and / or another type of resistive or threshold-based memory cell. Self-select memory cell 105 may include one or more components of material (e.g., chalcogenide material) that each acts as both a memory element and a cell selector (selection) element, thereby eliminating the need for a separate cell selector circuitry (a selector circuitry that does not contribute to memory). Such a component may be referred to as a memory and selector assembly (or element), or a self-select memory assembly (or element). In contrast, other types of memory cells, such as dynamic random access memory (DRAM) or PCM cells, may each include a separate (dedicated) cell selector element, such as a three-terminal selector element (e.g., a transistor) or a two-terminal selector element (e.g., a diode), to facilitate the selection or non-selection of memory cells without contributing to the memory of any logical state.

[0028] Memory array 102 may include multiple word lines 110 (e.g., row lines) labeled WL_1 to WL_M for each stack, and multiple bit lines 115 (e.g., column lines) labeled BL_1 to BL_N, where M and N depend on the array size. In some instances, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. In some cases, word lines 110 and bit lines 115 may generally be referred to as access lines because they allow access to memory cells 105. In some instances, word lines 110 may also be referred to as row lines 110, and bit lines 115 may also be referred to as number lines 115 or column lines 115. References to access lines, word lines, and bit lines, etc., are interchangeable without diminishing understanding or operation. Enabling or selecting a word line 110 or bit line 115 may involve applying a voltage to the corresponding line. The word line 110 and bit line 115 may be made of conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductively doped semiconductors or other conductive materials, alloys, compounds, etc.

[0029] Word lines 110 and bit lines 115 may be substantially perpendicular (i.e., orthogonal) to each other or otherwise intersect to form a memory cell array. For example... Figure 1As shown, two memory cells 105 in memory cell stack 145 can share a common conductive line, such as bit line 115. That is, bit line 115 can electronically communicate with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105 in memory cell stack 145. Other configurations may be possible; for example, a third stack (not shown) can share access line 110 with either the lower or upper stack shown. Generally, a memory cell 105 can be located at the intersection of two conductive lines, such as word line 110 and bit line 115. This intersection can be referred to as the address of memory cell 105. The target memory cell 105 can be a memory cell 105 located at the intersection of word line 110 and bit line 115 that is powered; that is, word line 110 and bit line 115 can be powered to read, write, or otherwise access the memory cell 105 at its intersection. Other memory cells 105 that are electronically communicated (e.g., connected) with the same word line 110 or bit line 115 may be referred to as non-target memory cells 105.

[0030] Electrodes may be coupled to memory cell 105 and word line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact with memory cell 105. Electrodes may comprise traces, wires, conductive lines, conductive layers, etc., providing conductive paths between elements or components of memory device 100. In some instances, memory cell 105 may comprise a plurality of selectable or other memory components (e.g., selectable components and storage components) separated from each other by electrodes and from access lines 110, 115. As previously described, for selectable memory cell 105, a single component (e.g., a portion or layer of chalcogenide material within memory cell 105) may serve as both a storage element (e.g., for storing or facilitating the storage of the state of memory cell 105) and a selector element (e.g., for selecting or facilitating the selection of memory cell 105).

[0031] The electrodes within the memory cell stack 145 may each have the same material (e.g., carbon) or may have various (different) materials. In some cases, the electrodes may be made of a material different from the access lines. In some instances, the electrodes may protect materials contained in select or other memory components (e.g., chalcogenide materials) from word lines 110, bit lines 115, and from each other, preventing chemical interactions between the materials and word lines 110, bit lines 115, or another memory component.

[0032] Operations such as reading and writing can be performed on memory cell 105 by activating or selecting the corresponding word line 110 and bit line 115. Access to memory cell 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. This process can be referred to as decoding a row or word line address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate bit line 115. This process can be referred to as decoding a column or bit line address. For example, row decoder 120 and / or column decoder 130 may be instances of decoders implemented using decoder circuitry. In some cases, row decoder 120 and / or column decoder 130 may include charge pump circuitry configured to increase the voltage applied to word line 110 or bit line 115, respectively.

[0033] When memory cell 105 is accessed, memory cell 105 can be read (e.g., sensed) by sensing component 125 (e.g., in cooperation with memory controller 140, row decoder 120, and / or column decoder 130) to determine the logical state stored in memory cell 105. Sensing component 125 can provide an output signal indicating (e.g., at least in part based on) the logical state stored in memory cell 105 to one or more components (e.g., column decoder 130, input / output component 135, memory controller 140). In some instances, the detected logical state can be provided to a host device (e.g., a device that uses memory cell 100 for data storage, a processor coupled to memory cell 100 in an embedded application), wherein the signaling can be provided directly from input / output component 135 or via memory controller 140.

[0034] Sensing component 125 may include various transistors or amplifiers to detect and amplify differences in signals obtained based on read memory unit 105; this operation may be referred to as latching. The detected logic state of memory unit 105 can then be output via column decoder 130, which serves as input / output component 135. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120. Those skilled in the art will understand that sensing components can be associated with column decoders or row decoders without losing their functional purpose.

[0035] Although row decoder 120 and column decoder 130 are shown on the side of memory array 102 for clarity, in some cases they may be below memory array 102. Each decoder 120, 130 may include or be coupled to one or more drivers configured to drive access lines 110, 115 to a desired voltage (e.g., to access one or more associated memory cells 105). In some cases, drivers may be distributed across an area below memory array 102. Vias may extend through one or more layers or stacks of memory device 100 to couple drivers to their corresponding access lines 110, 115. For example, if access lines 110, 115 are considered to extend in a horizontal direction (e.g., the x-direction or y-direction), then vias may extend in a vertical (z-direction). In some cases, one or more layers between the driver and the access line may contain metallic wiring, which may be referred to as interconnect layers or collectively as interconnect layers, wherein the driver may be coupled to a corresponding line in the interconnect layer, and vias may extend between the interconnect layer and the layer containing the access line 115.

[0036] In some cases, access lines at different levels of memory array 102 may have different resistivities. For example, word lines 110 at the bottom of memory array 102 (associated with the lower stack) may have a different (e.g., higher) resistivity than word lines 110 at the top of memory array 102 (associated with the upper stack). As another example, word lines 110 at the bottom of memory array 102 (associated with the lower stack) may have a different (e.g., higher) resistivity than bit lines 115 shown. Alternatively, word lines 110 at the top of memory array 102 (associated with the upper stack) may have a different (e.g., lower) resistivity than bit lines 115 shown. The different resistivities of access lines at different levels may be related to the different degrees to which access lines at different levels are oxidized, as described herein. Access lines with higher resistivity may be oxidized to a greater degree than access lines with lower resistivity.

[0037] Figure 2 An example of a 3D memory array 200 supporting configurable resistivity for lines in a memory array 200, according to the examples disclosed herein, is shown. The memory array 200 may be used as a reference. Figure 1 An example of a portion of the described memory array 102. The memory array 200 may include a first memory cell array or stack 205-a positioned above a substrate 204 and a second memory cell array or stack 205-b positioned above the first array or stack 205-a. Although the example of the memory array 200 includes two stacks 205-a, 205-b, it should be understood that one stack 205 (e.g., a 2D memory array) or more than two stacks 205 are also possible. Furthermore, although included in... Figure 2Some elements are marked with numerical indicators, while other corresponding elements are not marked, but the elements are the same or will be understood to be similar, in order to improve the visibility and clarity of the depicted features.

[0038] The memory array 200 may also include word lines 210 and bit lines 215, which can be referenced. Figure 1 Examples of word line 110 and bit line 115 described herein. Word line 210 and bit line 215 may initially be formed (manufactured) from corresponding metal layers, and therefore may initially comprise metallic materials such as tungsten (W), copper (Cu), aluminum (Al), gold (Au), titanium (Ti), or metal alloys.

[0039] After formation (e.g., patterning), word lines 210 and bit lines 215 may be oxidized, as described in more detail elsewhere herein, to configure word lines 210 and bit lines 215 at a given level of memory array 200 to have a desired resistivity. In some cases, the resistivity of the access lines may be expressed as the amount of resistance per unit length of the access line (e.g., resistivity may in some cases be expressed in ohm-meters, i.e., the number of ohms per meter of length multiplied by the cross-sectional area of ​​the access line expressed in square meters, thus obtaining a fixed amount of resistance per unit length of access line with a constant cross-sectional area of ​​the access line). Alternatively or additionally, the resistivity of the access lines may be expressed as sheet resistance, which may be a measure of the resistivity of a material comprising a thin sheet of material having a uniform thickness or a material formed from a thin sheet of material. In some cases, sheet resistance may be expressed in ohm squares, which may be equal in dimension to ohms (e.g., obtained by dividing the resistivity unit ohm-meter by the uniform sheet thickness expressed in meters), but may specifically mean sheet resistance (e.g., rather than the bulk resistance of, for example, a conventional resistor).

[0040] The memory cell of the first stack 205-a may include a first electrode 225-a, a memory element 220-a, and a second electrode 225-b. Additionally, the memory cell of the second stack 205-b may include a first electrode 225-c, a memory element 220-b, and a second electrode 225-d. In some embodiments, the memory cells of the first stack 205-a and the second stack 205-b may have a common conductive line, such that the corresponding memory cells of each stack 205-a and 205-b can be as described in the reference. Figure 1 The described shared bit line 215 or word line 210. For example, the first electrode 225-c of the second stack 205-b and the second electrode 225-b of the first stack 205-a can be coupled to bit line 215-a, such that bit line 215-a is shared by vertically adjacent memory cells.

[0041] The architecture of memory array 200 may be referred to as a crossover architecture in some cases, in which memory cells are formed at the topological crossover points between word lines 210 and bit lines 215, such as... Figure 2 As shown in the diagram. The crossover architecture can provide relatively high-density data memory with lower manufacturing costs compared to at least some other memory architectures. For example, the crossover architecture can have reduced memory cells, and therefore can have increased memory cell density compared to at least some other architectures.

[0042] Although each memory cell is shown as a single memory element 220 for clarity, the memory cells of the first stack 205-a and the second stack 205-b may each contain one or more memory elements 220 (e.g., elements of memory material configurable to store information), which may or may not be optional memory elements. In some instances, the memory element 220 may, for example, comprise a chalcogenide material or other alloy containing selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, a chalcogenide material primarily containing selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some instances, the SAG alloy may also contain silicon (Si), and such a chalcogenide material may be referred to as a SiSAG alloy. In some other instances, the SAG alloy may also contain indium (In), and such a chalcogenide material may be referred to as an InSAG alloy in some cases. In some instances, chalcogenides may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0043] In some cases, memory element 220 may be included in a PCM cell. Within the PCM cell, memory element 220 can switch from amorphous to crystalline and vice versa. Therefore, the memory element 220 can be heated above its melting temperature by applying a voltage across it and thus allowing current to flow through it. The state is then written to the memory cell containing memory element 220 by removing the voltage and current according to various timing parameters configured to place the memory element 220 in the desired state (e.g., amorphous or crystalline). The heating and quenching of memory element 220 can be achieved by controlling the current flowing through it, which in turn can be achieved by controlling the voltage difference between the corresponding word line 210 and the corresponding bit line 215.

[0044] Crystalline memory element 220 may have atoms arranged in a periodic structure, which can produce relatively low resistance (e.g., in a set state). In contrast, amorphous memory element 220 may have little or no periodic atomic structure, which can result in relatively high resistance (e.g., in a reset state). The difference in resistance between the amorphous and crystalline states of memory element 220 can be significant; for example, the amorphous material may have a resistance one or more orders of magnitude greater than that of the material in its crystalline state. In some cases, the amorphous state may have an associated threshold voltage, and current may not flow until it exceeds Vth. Some PCM cells may include one memory element 220 configured to undergo a phase transition and thus act as a storage element, and another memory element 220 configured to act as a diode (e.g., a surge diode) and thus act as a selection element. The selection element may be configured to remain in an amorphous state even when the storage element in the same PCM cell is in a crystalline state.

[0045] In some cases, memory element 220 may be partially amorphous and partially crystalline, and its resistance may have a value between the resistance of memory element 220 in a completely crystalline state and a completely amorphous state. Memory element 220 can therefore be used for applications other than binary logic applications, i.e., the number of possible states stored in the material may exceed two.

[0046] In some cases, the memory element 220 included in the self-selected memory cell can be operated to prevent phase transitions during normal operation of the memory cell (e.g., due to the composition of the memory (e.g., chalcogenide) material, and / or due to the operable voltage and current configured to maintain the memory element 220 in a single phase (e.g., an amorphous or glassy phase). For example, the memory element 220 may contain a chemical element, such as arsenic, that inhibits the crystallization of the chalcogenide material and thus remains in an amorphous state. Here, some or all of the set of logic states supported by the memory cell (e.g., including the memory element 220 and electrode 225) may be associated with the amorphous state of the memory element 220 (e.g., stored by the memory element 220 when it is in an amorphous state). For example, both logic state '0' and logic state '1' may be associated with the amorphous state of the memory element 220 (e.g., stored by the memory element 220 when it is in an amorphous state). In some cases, the memory element 220 may be configured to store logic states corresponding to information bits.

[0047] During a programming (writing) operation of a memory cell (e.g., including electrode 225-a, memory element 220-a, and electrode 225-b), the polarity used for programming (writing) or whether the memory element 220 is programmed to be amorphous or crystalline can affect (determine, set, program) specific characteristics or features of the memory element 220, such as the threshold voltage or resistance of the memory element 220. The difference between the threshold voltage or resistance of the memory element 220 depending on the logic state stored by the memory element 220 (e.g., the difference between the threshold voltages or resistances when the memory element 220 is storing a logic state '0' opposite to logic state '1') can correspond to the read window of the memory element 220.

[0048] Word line 210-a may be located at a first level of memory array 200, bit line 215-a may be located at a second level of memory array 200, and word line 210-c may be located at a third level of memory array 200. Each word line 210 and bit line 215 may include a corresponding metal portion 230 and a metal oxide portion 235. As discussed above and elsewhere herein, word line 210 or bit line 215 may initially be formed (manufactured) from a corresponding metal layer, and the corresponding metal portion 230 may include the same metal material. Similarly, as discussed above and elsewhere herein, word line 210 or bit line 215 may subsequently be oxidized to form the corresponding metal oxide portion 235. The metal oxide portion 235 may include an oxide of the metal contained in the metal portion 230 (e.g., if the metal portion 230 includes tungsten (W), then the metal oxide portion 235 may include tungsten oxide (W)). x O y If the metal portion 230 includes aluminum (Al), then the metal oxide portion 235 may include aluminum oxide (Al). x O y (and so on).

[0049] For word lines 210 or bit lines 215, the resistivity of the access line can be determined by the thickness (cross-sectional area) of the corresponding metal portion 230 and the thickness of the corresponding metal oxide portion 235. For example, the metal portion 230 may have a lower resistivity than the metal oxide portion; therefore, a thicker metal portion 230 may have a lower resistivity (greater conductivity), while a thinner metal portion 230 may have a higher resistivity (less conductivity). If the total cross-sectional area of ​​the access line is fixed (e.g., constant within or across layers of the memory array 200), then a thicker metal oxide portion 235 may correspond to a thinner metal portion 230 and therefore to a higher resistivity, while a thinner metal oxide portion 235 may correspond to a thicker metal portion 230 and therefore to a lower resistivity. Thus, for the same total cross-sectional area, an access line oxidized to a greater extent may have a higher resistivity than an access line oxidized to a lesser extent.

[0050] Therefore, the resistivity adjustment (configuration) of access lines (e.g., word lines 210 or bit lines 215) at different levels of the memory array 200 can be achieved by selectively oxidizing the access lines to different degrees to form corresponding metal portions 230 and metal oxide portions 235 with desired thicknesses. For example, metal portion 230-c may be thicker than metal portion 230-a (e.g., due to metal oxide portion 235-c being thinner than metal oxide portion 235-a, and word lines 210-c and 210-a initially being formed from the same material and having the same total cross-sectional area). Thus, access lines at different stacks 205 of the memory array 200 may have different resistivities. Alternatively, in some cases, access lines within the same stack 205 of the memory array 200 but at different levels may have different resistivities. For example, metal portion 230-b may be thicker than metal portion 230-a (for example, due to metal oxide portion 235-b being thinner than metal oxide portion 235-a, and bit line 215-a and word line 210-a being initially formed of the same material and having the same total cross-sectional area).

[0051] Oxidation of access lines can be achieved through various oxidation processes that incorporate wet and dry processing techniques. For example, the oxidation of access lines can be achieved through a wet processing technique in which the access lines are exposed to liquid hydrogen peroxide (or another liquid oxidant). Alternatively, the oxidation of access lines can be achieved through a dry processing technique in which the access lines are exposed to oxygen (e.g., in gaseous or plasma form). Wet and / or dry processing techniques can be modulated (controlled, adjusted) to configure the thickness of the oxide portion 235 to achieve the desired resistivity of the access lines. In some cases, access lines at different levels of the memory array 200 can be sequentially executed (e.g., access lines at higher levels can be formed after access lines at lower levels have been formed). Access lines at a given level of the memory array 200 can be oxidized after and before the formation of access lines at another (e.g., higher) level.

[0052] although Figure 2 The example shows metal portion 230 and metal oxide portion 235 as distinct sublayers, wherein the sublayer corresponding to metal oxide portion 235 is above the sublayer corresponding to the corresponding metal portion 230. However, those skilled in the art will understand that metal portion 230 and metal oxide portion 235 of the same access line may be distributed in other ways depending on the manufacturing technology and the manufacturing stage of the oxidized access line. For example, when the upper surface of the access line is exposed to an oxidant (e.g., liquid hydrogen peroxide, oxygen in gaseous or plasma form), oxidizing the access line may cause metal oxide portion 235 to form as a sublayer above metal portion 230, but metal oxide portion 235 may additionally or alternatively form on the sidewall of metal portion 230.

[0053] Furthermore, those skilled in the art, or those generally skilled in the art, should understand that some access lines (e.g., at one level) may be oxidized without oxidation to achieve low resistivity, while access lines at one or more other levels may be oxidized to one or more different degrees to achieve one or more higher resistivity. Additionally, the concept of resistivity described herein can alternatively be expressed based on conductivity, which can be the reciprocal of resistivity.

[0054] Figure 3 A flowchart illustrating an example method 300 for configuring the resistivity of metal lines in a memory device, according to an example disclosed herein. In some cases, for example, method 300 can be used to configure access lines (e.g., refer to...). Figure 1 The described memory array 102 or reference Figure 2 The resistivity of the access lines of the described memory array 200. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are necessary in every embodiment. Other process flows are possible.

[0055] At 305, metal lines can be formed at the first level of the memory device. For example, the metal lines can be access lines (e.g., word lines or bit lines) within a memory array. A variety of masking (e.g., patterning), removal (e.g., etching), or formation (e.g., deposition) techniques can be used to form the metal lines. For example, a metal layer (material) can be formed over a substrate (e.g., over an intervening material stack also formed over the substrate), and the metal layer can be patterned to form any number of metal lines.

[0056] At 310, the metal wire in the first layer can be exposed to oxygen according to the first set of parameter values. Exposing the metal wire to oxygen oxidizes the metal forming the metal wire, thereby increasing the resistivity of the metal wire (e.g., reducing the effective thickness). The first set of parameters can be selected (adjusted) to configure the degree of oxidation of the metal wire in the first layer and thus configure the resistivity of the metal wire in the first layer. The total cross-sectional area of ​​the metal wire in the first layer can remain the same after 310 and after 305, but the effective thickness of the metal within the metal wire in the first layer can be reduced proportionally to the degree of oxidation. Therefore, it is possible to adjust the resistivity of the metal wire in the first layer regardless of how the metal wire was initially formed at 305.

[0057] The metal wire formed at 305 can be exposed to oxygen in a variety of ways. For example, the metal wire formed at 305 can be exposed to oxygen in the form of gas and / or plasma, which may be referred to as a dry process or technique, and can oxidize the metal wire (e.g., tungsten wire) to form a metal oxide (e.g., tungsten oxide).

[0058] In some cases, 310 may include the use of a diffusion process. For example, a metal wire may be exposed to oxygen plasma in a plasma chamber used for diffusion. Examples of diffusion processes may be chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PCDEV), or other processes that can utilize oxygen plasma. In these processes, the metal can be selectively converted from a more conductive metal to a less conductive metal oxide to a desired degree (e.g., the desired thickness of the metal oxide portion 235) based on various parameters that can be adjusted for the diffusion process. As an example parameter, the pressure of the plasma chamber can be varied to achieve the desired degree of oxidation. In this case, the higher the pressure of the plasma chamber, the greater the degree of oxidation can be due to the increased amount of oxygen available for oxidizing the metal within the chamber. As another example parameter, the exposure time (e.g., the duration of metal exposure to oxygen plasma) can be varied to achieve the desired degree of oxidation. In this case, the longer the metal is exposed to oxygen, the greater the degree of oxidation can be. As yet another example parameter, the excitation power of the oxygen plasma can be varied to achieve the desired degree of oxidation. In this case, the greater the excitation power of the plasma, the greater the degree of metal oxidation. In some instances, other parameters of the diffusion process can be adjusted. And as yet another example, the oxygen content within the oxygen plasma can be altered to achieve the desired degree of oxidation. In this case, the greater the oxygen concentration, the greater the degree of metal oxidation. In some instances, other parameters of the diffusion process can be adjusted. These or many other parameters associated with the diffusion process can be set (adjusted, configured) independently or in combination to regulate the degree of oxidation and thus the resistivity of the metal wire formed at 305.

[0059] In some cases, 310 may include the use of a dry etching process. In a dry etching process, a metal wire may be exposed to oxygen that has been ignited in a dry etching chamber. When the metal wire is exposed to oxygen, a voltage may be applied to bias an electrostatic chuck in the dry etching chamber. For example, the metal wire may be in electronic communication with the electrostatic chuck via a substrate over which the metal wire is formed or otherwise, and the bias voltage applied to the electrostatic chuck may be selectively adjusted (configured) to affect the degree of oxidation of the metal wire (e.g., by adjusting the voltage potential difference between the metal wire and the ion deposition tool). Thus, as an example parameter, the voltage difference may be varied to achieve the desired degree of oxidation (e.g., by varying the bias voltage of the chuck, the ion deposition tool, or both). In this case, a larger voltage difference may result in a greater degree of oxidation.

[0060] Dry etching processes also support 310 other configurable parameters for controlling the degree of oxidation. For example, similar to diffusion processes, the dry etching chamber pressure, exposure time, and excitation power can be adjusted. In some cases, additional parameters can be adjusted in the dry etching process to further increase the selectivity (controllability) of the oxidation degree. As an example parameter, the oxygen ratio of the plasma can be adjusted to achieve the desired oxidation degree. In this case, a higher oxygen content in the plasma results in a greater degree of oxidation. As another example parameter, the radio frequency (RF) power of the magnetic field in the dry etching chamber can be adjusted. In this case, a higher RF power results in a greater degree of oxidation. As yet another example parameter, the ratio of the internal to external coils in the dry etching chamber can be adjusted to modify the power distribution within the chamber. In this case, adjusting the ratio of the internal to external coils in the dry etching chamber can affect the oxidation uniformity across different aspects of the wafer or other structure (e.g., a higher internal to external coil ratio results in a greater degree of oxidation near the center of the wafer or other structure than further away, while a lower internal to external coil ratio results in a lesser degree of oxidation near the center of the wafer or other structure than further away). Therefore, for example, the degree of oxidation (and thus resistivity) of the access lines at a given level of a memory device can vary along the length of the access line in some cases (e.g., portions further from the center of the associated wafer have less oxidation and therefore lower resistance). And as another example parameter, the temperature of the chuck, the metal line, or the associated wafer, or the temperature of another aspect of the dry etching chamber or process, can be adjusted. In this case, higher temperatures can result in a greater degree of oxidation. These or many other parameters associated with the diffusion process can be set (adjusted, configured) independently or in combination to regulate the degree of oxidation and thus the resistivity of the metal lines formed at 305.

[0061] At 315, metal lines can be formed at a second level of the memory device. For example, the metal lines can be access lines (e.g., word lines or bit lines) within a memory array. A variety of masking (e.g., patterning), removal (e.g., etching), or formation (e.g., deposition) techniques can be used to form the metal lines at the second level. For example, a metal layer (material) can be formed at the second level, which may be above the first level (e.g., above an intervening stack of one or more materials or structures also formed above the first level), and the metal layer at the second level can be patterned to form any number of metal lines at the second level. In some cases, the metal lines formed at 315 can be formed using the same or similar process as that used to form the metal lines at 305, but applied at a different level of the memory device. Therefore, in some cases, the material and cross-sectional area of ​​the metal lines formed at 315 may be the same as or at least substantially the same as those formed at 305.

[0062] In some cases, the set of metal lines formed at 305 and the set of metal lines formed at 310 may be of the same type (e.g., both sets may be word lines, or both sets may be bit lines). In other cases, the set of metal lines formed at 305 and the set of metal lines formed at 310 may be of different types (e.g., one set may be word lines, and the other set may be bit lines). Furthermore, any number of additional materials or structures may be formed below the metal lines at the first level, above the metal lines at the second level, or between the first and second levels. For example, the first and second levels may both be contained in the same stack 205 of the memory cells or may be contained in different stacks 205 of the memory cells.

[0063] At 320, the metal wire at the second level can be exposed to oxygen according to the second set of parameter values. Any of the techniques described with reference to 310 can be used alone or in any combination at 320 to oxidize the metal wire at the second level to the desired degree. For example, any number of various parameters described with reference to 320 can be adjusted alone or in any combination (e.g., the second set of parameters at 320 can be different from the first set of parameters at 310) so that the metal wire at the second level achieves a different degree of oxidation and therefore a different resistivity compared to the metal wire at the first level. Thus, for example, any parameter described with reference to 310 can have a first value (set) at 310 and a second value at 320.

[0064] One or more operations associated with 310 may be performed when at least a portion of the access line formed at 305 is exposed (e.g., at least one surface of each of the access lines formed at 305 is exposed on the surface of the wafer), and one or more operations associated with 320 may be performed when at least a portion of the access line formed at 315 is exposed (e.g., at least one surface of each of the access lines formed at 315 is exposed on the surface of the wafer). In some cases, a first cleaning operation may be performed between 305 and 310, and a second cleaning operation may be performed between 315 and 320.

[0065] Figure 4 A flowchart illustrating an example method 400 for configuring the resistivity of a line in a memory device, according to an example disclosed herein. In some cases, for example, method 400 can be used to configure access lines (e.g., refer to...). Figure 1 The described memory array 102 or reference Figure 2 The resistivity of the access lines of the described memory array 200. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are necessary in every embodiment. Other process flows are possible.

[0066] At 405, metal lines can be formed at the first level of the memory device. For example, the metal lines can be access lines (e.g., word lines or bit lines) within a memory array. A variety of masking (e.g., patterning), removal (e.g., etching), or formation (e.g., deposition) techniques can be used to form the metal lines. For example, a metal layer (material) can be formed over a substrate (e.g., over an intervening material stack also formed over the substrate), and the metal layer can be patterned to form any number of metal lines.

[0067] At 410, the metal wire at the first level can be exposed to an oxidant (e.g., a solution) according to the first set of parameter values. In some cases, the oxidant may be or contain a peroxide. For example, the oxidant may be hydrogen peroxide or a solution containing hydrogen peroxide. In some cases, the oxidant may be contained in a solution that can also serve as a cleaning solution. For example, a solution containing ammonium, ammonium hydroxide, and hydrogen peroxide (possibly excluding deionized water) may be used as an oxidant and additionally or alternatively as a cleaning solution. Such a solution may in some cases be referred to as APM or Standard Clean 1 (SC1) solution.

[0068] Exposing the metal wire to an oxidant at 410 oxidizes the metal forming the wire, thereby increasing the resistivity of the metal wire (e.g., reducing the effective thickness). A first set of parameters can be selected (adjusted) to configure the degree of oxidation of the metal wire at the first layer and thus configure the resistivity of the metal wire formed at 405. The total cross-sectional area of ​​the metal wire at the first layer can remain the same after 410 and after 405, but the effective thickness of the metal within the metal wire at the first layer can be reduced proportionally to the degree of oxidation. Therefore, the resistivity of the metal wire at the first layer can be adjusted regardless of how the metal wire is initially formed at 405.

[0069] The metal wire formed at 305 can be exposed to an oxidant in several ways. For example, a solution or oxidant can be used to expose the metal wire formed at 305 to an oxidant; this operation is called a wet process. In some cases, after the metal wire is formed at 405, a cleaning process can be performed to prepare the structure containing the metal wire for subsequent processing. The cleaning process may involve exposing the metal wire formed at 405 to a cleaning solution. The cleaning solution may contain, for example, ammonium hydroxide. In some cases, an oxidant can be added to the cleaning solution (e.g., hydrogen peroxide can be added to the cleaning solution), so that cleaning and oxidation are performed in parallel at 410. In other cases, the metal wire formed at 405 can be exposed to an oxidant after a cleaning process (e.g., cleaning the metal wire formed at 405 with a cleaning solution that does not contain an oxidant), so that cleaning is performed between 405 and 410. Even when different cleaning steps using a cleaning solution lacking an oxidant are used between 405 and 410, the oxidant used at 410 can still be contained in a solution with cleaning capabilities (e.g., a first cleaning solution lacking an oxidant can be used as part of the cleaning process between 405 and 410, and a second, different cleaning solution containing an oxidant can subsequently be used at 410). Furthermore, in some cases, more than one oxidant can be used in parallel or sequentially (e.g., as part of a single solution or as part of solutions applied in different sequences).

[0070] In wet processes, the metal can be selectively converted from a more conductive metal to a less conductive metal oxide to a desired degree (e.g., the desired thickness of the metal oxide portion 235) based on various parameters that can be adjusted for the wet process. As an example parameter, the concentration of the oxidant (e.g., peroxide, such as hydrogen peroxide) in the solution to which the metal wire is exposed at 410 can be varied to achieve the desired oxidation level. In this case, a higher concentration of the oxidant results in a greater degree of oxidation. As another example parameter, the exposure time (e.g., the duration for which the metal wire is exposed to the oxidant at 410) can be varied to achieve the desired oxidation level. As yet another example parameter, the oxidant can be selected (and thus varied by layer) to achieve the desired oxidation level. In this case, a stronger oxidant (e.g., more oxidizing at a given concentration and exposure time) results in a greater degree of oxidation. These or many other parameters associated with wet processes can be set (adjusted, configured) independently or in combination to regulate the degree of oxidation and thus the resistivity of the metal wire formed at 405.

[0071] At 415, metal lines can be formed at a second level of the memory device. For example, the metal lines can be access lines (e.g., word lines or bit lines) within a memory array. A variety of masking (e.g., patterning), removal (e.g., etching), or formation (e.g., deposition) techniques can be used to form the metal lines at the second level. For example, a metal layer (material) can be formed at the second level, which may be above the first level (e.g., above an intervening stack of one or more materials or structures also formed above the first level), and the metal layer at the second level can be patterned to form any number of metal lines at the second level. In some cases, the metal lines formed at 415 can be formed using the same or similar process as that used to form the metal lines at 405, but applied at a different level of the memory device. Therefore, in some cases, the material and cross-sectional area of ​​the metal lines formed at 415 may be the same as or at least substantially the same as those formed at 405.

[0072] In some cases, the set of metal lines formed at 405 and the set of metal lines formed at 410 may be of the same type (e.g., both sets may be word lines, or both sets may be bit lines). In other cases, the set of metal lines formed at 405 and the set of metal lines formed at 410 may be of different types (e.g., one set may be word lines, and the other set may be bit lines). Furthermore, any number of additional materials or structures may be formed below the metal lines at the first level, above the metal lines at the second level, or between the first and second levels. For example, the first and second levels may both be contained in the same stack 205 of the memory cells or may be contained in different stacks 205 of the memory cells.

[0073] At 420, the metal wire at the second level can be exposed to the oxidant according to the second set of parameter values. Any of the techniques described with reference to 410 can be used alone or in any combination at 420 to oxidize the metal wire at the second level to the desired degree. For example, any number of various parameters described with reference to 420 can be adjusted alone or in any combination (e.g., the second set of parameters at 420 can be different from the first set of parameters at 410) so that the metal wire at the second level achieves a different degree of oxidation and therefore a different resistivity compared to the metal wire at the first level. Thus, for example, any parameter described with reference to 410 can have a first value (set) at 410 and a second value at 420.

[0074] One or more operations associated with 410 may be performed when at least partially exposed access lines formed at 405 (e.g., at least one surface of each of the access lines formed at 405 is exposed on the surface of the wafer), and one or more operations associated with 420 may be performed when at least partially exposed access lines formed at 415 (e.g., at least one surface of each of the access lines formed at 415 is exposed on the surface of the wafer). Furthermore, the metal lines may be exposed to an oxidant at 420 in a manner similar to that described with respect to 410, either simultaneously with or after the cleaning process.

[0075] Figure 5 The flowchart illustrates one or more methods 500 for supporting configurable resistivity of lines in a memory device according to aspects of the invention. The operation of method 500 can be carried out by forming tools, dry processing tools, wet processing tools, or components thereof, as described herein.

[0076] At point 505, a first set of access lines for a memory device can be formed. Operation of point 505 can be performed according to the methods described herein. In some instances, aspects of the operation of point 505 can be performed by forming tools.

[0077] At 510, the first access line set can be oxidized to a first degree. The operation at 510 can be performed according to the method described herein. In some instances, aspects of the operation at 510 can be performed using either wet or dry processing tools.

[0078] At point 515, after oxidizing the first set of access lines, a second set of access lines for a memory device can be formed. The operation at point 515 can be performed according to the method described herein. In some instances, aspects of the operation at point 515 can be performed using a forming tool.

[0079] At 520, the second access line set can be oxidized to a second degree. The operation at 520 can be performed according to the method described herein. In some instances, aspects of the operation at 520 can be performed using either wet or dry processing tools.

[0080] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include operations, features, or components for forming a first set of access lines for a memory device, oxidizing the first set of access lines to a first degree, forming a second set of access lines for a memory device after oxidizing the first set of access lines, and oxidizing the second set of access lines to a second degree.

[0081] In some instances of the method 500 and device described herein, the second set of access lines may be above the first set of access lines.

[0082] In some instances of the method 500 and device described herein, the second degree may be less than the first degree.

[0083] Some examples of the method 500 and apparatus described herein may further include operations, features, or components for forming a first memory cell stack coupled to a first set of access lines and for forming a second memory cell stack coupled to a second set of access lines.

[0084] In some examples of the method 500 and apparatus described herein, the operation, feature, or component for oxidizing the first access line set may include the operation, feature, or component for exposing the first access line set to an oxygen-containing plasma, and the operation, feature, or component for oxidizing the second access line set may include the operation, feature, or component for exposing the second access line set to an oxygen-containing plasma.

[0085] In some instances of the method 500 and apparatus described herein, a first access line set may be exposed to an oxygen-containing plasma as part of a first dry etching process, and a second access line set may be exposed to an oxygen-containing plasma as part of a second dry etching process.

[0086] In some instances, the first access line set and the second access line set may be formed on a wafer. Some instances of the method 500 and apparatus described herein may further include operations, features, or components for applying a first voltage to the wafer (wherein the first degree may be based on the first voltage) when the first access line set may be exposed to an oxygen-containing plasma and for applying a second voltage to the wafer (wherein the second degree may be based on the second voltage) when the second access line set may be exposed to an oxygen-containing plasma.

[0087] In some instances of the method 500 and apparatus described herein, a first access line set may be exposed to an oxygen-containing plasma for a first time amount, a first degree based on the first time amount, and a second access line set may be exposed to an oxygen-containing plasma for a second time amount, a second degree based on the second time amount.

[0088] In some instances, the first access line set and the second access line set may be formed on a wafer. Some examples of the method 500 and apparatus described herein may further include operations, features, or components for heating the wafer to a first temperature (wherein the first degree may be based on the first temperature) when the first access line set may be exposed to an oxygen-containing plasma and for heating the wafer to a second temperature (wherein the second degree may be based on the second temperature) when the second access line set may be exposed to an oxygen-containing plasma.

[0089] Some examples of the method 500 and apparatus described herein may further include operations, features, or components for exciting a plasma to which a first set of access lines can be exposed using a first power amount (wherein the first degree may be based on the first power amount) and for exciting a plasma to which a second set of access lines can be exposed using a second power amount (wherein the second degree may be based on the second power amount).

[0090] In some instances of the method 500 and apparatus described herein, a first access line assembly may be exposed to an oxygen-containing plasma at a first pressure level, the first degree being based on the first pressure level, and a second access line assembly may be exposed to an oxygen-containing plasma at a second pressure level, the second degree being based on the second pressure level.

[0091] In some instances of the method 500 and apparatus described herein, a first access line set may be exposed to a plasma containing a first concentration of oxygen, the first degree being based on the first concentration, and a second access line set may be exposed to a plasma containing a second concentration of oxygen, the second degree being based on the second concentration.

[0092] In some examples of the method 500 and apparatus described herein, the operation, feature, or component for oxidizing the first access line set may include the operation, feature, or component for exposing the first access line set to hydrogen peroxide, and the operation, feature, or component for oxidizing the second access line set may include the operation, feature, or component for exposing the second access line set to hydrogen peroxide.

[0093] Some examples of the methods 500 and apparatus described herein may further include operations, features, or components for exposing a first access line set to ammonium hydroxide when the first access line set is exposed to hydrogen peroxide and for exposing a second access line set to ammonium hydroxide when the second access line set is exposed to hydrogen peroxide.

[0094] Examples of the methods 500 and apparatus described herein may further include operations, features, or components for exposing a first access line set to ammonium hydroxide before the first access line set can be exposed to hydrogen peroxide and for exposing a second access line set to ammonium hydroxide before the second access line set can be exposed to hydrogen peroxide.

[0095] In some instances of the method 500 and apparatus described herein, a first access line set may be exposed to hydrogen peroxide for a first time amount, a first degree based on the first time amount, and a second access line set may be exposed to hydrogen peroxide for a second time amount, a second degree based on the second time amount.

[0096] In some examples of the method 500 and apparatus described herein, the operation, feature, or component for exposing a first access line set to hydrogen peroxide may include the operation, feature, or component for exposing the first access line set to a first solution containing a first concentration of hydrogen peroxide, and the operation, feature, or component for exposing a second access line set to hydrogen peroxide may include the operation, feature, or component for exposing the second access line set to a second solution containing a second concentration of hydrogen peroxide.

[0097] Figure 6 The flowchart illustrates one or more methods 600 according to aspects of the invention to support configurable resistivity of lines in a memory device. The operation of method 600 can be carried out by forming tools or dry processing tools or components thereof, as described herein.

[0098] At 605, a first set of access lines for a memory device can be formed. The operation at 605 can be performed according to the method described herein. In some instances, aspects of the operation at 605 can be performed by forming tools.

[0099] At 610, the first access line set may be oxidized to a first degree, which may include exposing the first access line set to an oxygen-containing plasma. The operation at 610 may be performed according to the methods described herein. In some instances, aspects of the operation at 610 may be performed using dry processing tools.

[0100] At 615, after oxidizing the first set of access lines, a second set of access lines for a memory device can be formed. The operation at 615 can be performed according to the method described herein. In some instances, aspects of the operation at 615 can be performed by forming tools.

[0101] At 620, the second access line set may be oxidized to a second degree, which may include exposing the second access line set to an oxygen-containing plasma. The operation at 620 may be performed according to the methods described herein. In some instances, aspects of the operation at 620 may be performed using dry processing tools.

[0102] Figure 7 The flowchart illustrates one or more methods 700 according to aspects of the invention to support configurable resistivity of lines in a memory device. The operation of method 700 can be carried out by forming tools or wet processing tools or components thereof, as described herein.

[0103] At 705, a first set of access lines for a memory device can be formed. Operation at 705 can be performed according to the methods described herein. In some instances, aspects of the operation at 705 can be performed by forming tools.

[0104] At 710, the first access line set may be oxidized to a first degree, which may include exposing the first access line set to hydrogen peroxide. The operation at 710 may be performed according to the methods described herein. In some instances, aspects of the operation at 710 may be performed using wet processing tools.

[0105] At 715, after oxidizing the first set of access lines, a second set of access lines for a memory device can be formed. The operation at 715 can be performed according to the method described herein. In some instances, aspects of the operation at 715 can be performed using a forming tool.

[0106] At 720, the second access line set may be oxidized to a second degree, which may include exposing the second access line set to hydrogen peroxide. The operation at 720 may be performed according to the methods described herein. In some instances, aspects of the operation at 720 may be performed using wet processing tools.

[0107] Figure 8 The flowchart illustrates one or more methods 800 for supporting configurable resistivity of lines in a memory device according to aspects of the invention. The operation of method 800 can be carried out by forming tools, dry processing tools, wet processing tools, or components thereof, as described herein.

[0108] At 805, a set of stacks of memory cells can be formed. Operations at 805 can be performed according to the methods described herein. In some instances, aspects of the operations at 805 can be performed using forming tools.

[0109] At 810, multiple sets of access lines can be formed, each of which is coupled to at least one of the memory cell stacks. Operations at 810 can be performed according to the methods described herein. In some instances, aspects of the operations at 810 can be performed by forming tools.

[0110] At 815, an access line set included in a plurality of access line sets can be oxidized. Operation at 815 can be performed according to the methods described herein. In some instances, aspects of operation at 815 can be performed using either wet or dry processing tools.

[0111] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include an array of stacks of memory cells, an array of multiple access line sets (each of the multiple access line sets being coupled to at least one of the memory cell stacks), and operations, features, or components included in one of the multiple access line sets.

[0112] Some examples of the method 800 and apparatus described herein may further include operations, features, or components for oxidizing a second set of access lines included in a plurality of sets of access lines. In some examples, oxidizing the set of access lines includes forming a corresponding first metal oxide layer having a first thickness in each access line of the set, and oxidizing the second set of access lines includes forming a corresponding second metal oxide layer having a second thickness in each access line of the second set.

[0113] Some examples of the methods 800 and apparatus described herein may include operations, features, or components for oxidizing the access line assembly based on exposing the access line assembly to an oxygen-containing plasma or exposing the access line assembly to hydrogen peroxide.

[0114] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0115] An apparatus is described. The apparatus may include a first memory cell stack coupled to a first set of access lines, each of the first set of access lines comprising a metal oxide having a first thickness, and a second memory cell stack above the first memory cell stack, wherein the second memory cell stack is coupled to a second set of access lines, and wherein each of the second set of access lines comprises a metal oxide having a second thickness.

[0116] In some instances, the first thickness may be greater than the second thickness.

[0117] In some instances, the first set of access lines may each comprise a metal of a third thickness beneath a metal oxide of a first thickness, and the second set of access lines may each comprise a metal of a fourth thickness beneath a metal oxide of a second thickness. In some instances, the fourth thickness may be greater than the third thickness.

[0118] In some instances, the first access line set and the second access line set may each contain tungsten, and the metal oxide may contain tungsten oxide.

[0119] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, those skilled in the art will understand that the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0120] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) with each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0121] The term "coupling" refers to the condition that allows signals to move between components from an open-circuit relationship where signals cannot currently travel between components via conductive paths to a closed-circuit relationship where signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0122] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, the controller affects the change that prevents signals from flowing between the components using previously permitted conductive paths.

[0123] As used herein, the term "layer" or "level" refers to a hierarchy or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0124] As used herein, the term “generally” means that the modified characteristic (e.g., a verb or adjective modified by the term “generally”) does not have to be an absolute value but is close enough to achieve the advantages of the characteristic.

[0125] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can serve as an electrical contact with other components of a memory cell or memory array. An electrode may comprise a trace, wire, conductive line, conductive layer, or the like that providing a conductive path between elements or components of the memory array.

[0126] The devices comprising memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be, for example, silicon-on-glass (SOG) or silicon-on-sapphire (SOP) substrates, silicon-on-insulator (SOI) substrates, or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0127] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. These terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0128] The embodiments described herein, in conjunction with the accompanying drawings, are exemplary configurations and do not represent all embodiments that are implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and does not imply "preferred" or "superior to other examples." Specific details are included to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagrams to avoid obscuring the concepts of the described examples.

[0129] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numeral and a second numeral to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0130] The information and signals described herein can be represented by any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0131] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0132] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this invention and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed so that portions of the functions are implemented in different physical locations. Furthermore, as used herein (included in the claims), “or” when used in a list of items (e.g., a list of items ending with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase “based on” should not be considered as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0133] The description herein is provided to enable those skilled in the art to make or use the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for forming a memory device, comprising: Forming a first set of access lines for the memory device; The first access line set is oxidized to a first time measure to a first degree, the first degree being associated with a first resistivity; After oxidizing the first set of access lines, a second set of access lines for the memory device is formed; and The second access line set is oxidized to a second time amount that is different from the first time amount to a second degree, the second degree being associated with a second resistivity that is different from the first resistivity.

2. The method of claim 1, wherein the second set of access lines is above the first set of access lines.

3. The method of claim 2, wherein the second degree is less than the first degree.

4. The method of claim 1, further comprising: Forming a first memory cell stack coupled to the first access line set; and A second memory cell stack is formed that is coupled to the second set of access lines.

5. The method according to claim 1, wherein: Oxidizing the first access line set includes exposing the first access line set to a plasma comprising oxygen; and Oxidizing the second access line set includes exposing the second access line set to a plasma comprising oxygen.

6. The method according to claim 5, wherein: The first access line assembly is exposed to oxygen-containing plasma as part of a first dry etching process; and The second access line assembly is exposed to oxygen-containing plasma as part of a second dry etching process.

7. The method of claim 5, wherein the first access line set and the second access line set are formed on a wafer, the method further comprising: When the first access line assembly is exposed to a plasma including oxygen, a first voltage is applied to the wafer, wherein the first degree is at least partially based on the first voltage; and When the second access line set is exposed to a plasma including oxygen, a second voltage is applied to the wafer, wherein the second degree is at least partially based on the second voltage.

8. The method according to claim 5, wherein: The first access line assembly was exposed to plasma including oxygen for the first duration, and the first degree was at least partially based on the first duration; and The second access line set is exposed to plasma including oxygen for the second time duration, the second degree being at least partially based on the second time duration.

9. The method of claim 5, wherein the first access line set and the second access line set are formed on a wafer, the method further comprising: When the first access line assembly is exposed to a plasma including oxygen, the wafer is heated to a first temperature, wherein the first degree is at least partially based on the first temperature; and When the second access line assembly is exposed to a plasma including oxygen, the wafer is heated to a second temperature, wherein the second degree is at least partially based on the second temperature.

10. The method of claim 5, further comprising: The plasma to which the first access line assembly is exposed is excited using a first power quantity, wherein the first degree is at least partially based on the first power quantity; and The plasma to which the second access line assembly is exposed is excited using a second power quantity, wherein the second degree is at least partially based on the second power quantity.

11. The method according to claim 5, wherein: The first access line assembly is exposed to a plasma including oxygen at a first pressure level, the first degree being at least partially based on the first pressure level; and The second access line assembly is exposed to a plasma including oxygen at a second pressure level, the second degree being at least partially based on the second pressure level.

12. The method according to claim 5, wherein: The first access line assembly is exposed to plasma comprising a first concentration of oxygen, the first degree being at least partially based on the first concentration; and The second access line assembly is exposed to plasma comprising a second concentration of oxygen, the second degree being at least partially based on the second concentration.

13. The method according to claim 1, wherein: Oxidizing the first access line set includes exposing the first access line set to hydrogen peroxide; and Oxidizing the second set of access lines includes exposing the second set of access lines to hydrogen peroxide.

14. The method of claim 13, further comprising: While the first access line set is exposed to hydrogen peroxide, the first access line set is also exposed to ammonium hydroxide; and While the second access line set is exposed to hydrogen peroxide, the second access line set is also exposed to ammonium hydroxide.

15. The method of claim 13, further comprising: The first access line set is exposed to ammonium hydroxide before being exposed to hydrogen peroxide; and The second access line set is exposed to ammonium hydroxide before being exposed to hydrogen peroxide.

16. The method of claim 13, wherein: The first access line set was exposed to hydrogen peroxide for the first time duration, and the first degree was at least partially based on the first time duration; and The second access line set is exposed to hydrogen peroxide for the second time amount, the second degree being at least partially based on the second time amount.

17. The method of claim 13, wherein: Exposing the first access line set to hydrogen peroxide includes exposing the first access line set to a first solution comprising a first concentration of hydrogen peroxide, the first extent being at least partially based on the first concentration; and Exposing the second access line set to hydrogen peroxide includes exposing the second access line set to a second solution comprising a second concentration of hydrogen peroxide, the second degree being at least partially based on the second concentration.

18. A memory device comprising: A first memory cell stack coupled to a first set of access lines, wherein each of the first set of access lines has a first resistivity based at least in part on a metal oxide of the first set of access lines having a first thickness; and A second memory cell stack is located above the first memory cell stack, wherein the second memory cell stack is coupled to a second set of access lines, and wherein each of the second set of access lines has a second thickness and includes a second resistivity based at least in part on the metal oxide of the second set of access lines.

19. The memory device of claim 18, wherein the first thickness is greater than the second thickness.

20. The memory device according to claim 18, wherein: Each of the first access line sets includes a metal of a third thickness beneath the metal oxide having the first thickness; and The second set of access lines each includes a metal of a fourth thickness beneath the metal oxide of the second thickness.

21. The memory device of claim 20, wherein the fourth thickness is greater than the third thickness.

22. The memory device of claim 18, wherein: The first access line set and the second access line set each include tungsten; and The metal oxide includes tungsten oxide.

23. A method for forming a memory device, comprising: Forming multiple memory cell stacks; A plurality of access line sets are formed, wherein each of the plurality of access line sets is coupled to at least one of the plurality of memory cell stacks; Oxidizing a first access line set included in the plurality of access line sets to a first time amount to a first degree, the first degree being associated with a first resistivity, wherein oxidizing the first access line set includes forming a corresponding first metal oxide layer having a first thickness within each access line of the first access line set; and The second access line set included in the plurality of access line sets is oxidized to a second time amount that is different from the first time amount to a second degree, the second degree being associated with a second resistivity that is different from the first resistivity.

24. The method of claim 23, wherein oxidizing the second set of access lines includes forming a corresponding second metal oxide layer having a second thickness in each access line of the second set of access lines.

25. The method according to claim 23, wherein: Oxidizing the first access line set is based at least in part on exposing the first access line set to a plasma including oxygen or exposing the first access line set to hydrogen peroxide.

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