Memory circuit, memory device, and operating method thereof

Abstract

In some aspects of the present case, a memory circuit, a memory device, and a method of operating the same are disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.

Description

Technical Field

[0001] This case relates to a memory circuit, a memory device, and a method of operating thereof, and more particularly to a memory circuit, a memory device, and a method of operating thereof in which a plurality of memory cells share a stacked transistor selector. Background Technology

[0002] Memory circuits, including fuses, antifuses, and some emerging memory types, typically require high voltages to program memory cells. The memory's peripheral circuitry and array are under voltage stress during programming. Summary of the Invention

[0003] One embodiment of this invention provides a memory circuit including a first storage element, a first transistor, a second storage element, a second transistor, and a third transistor. The first storage element is coupled to a first bit line. The first transistor is coupled between the first storage element and a central node. The second storage element is coupled to a second bit line. The second transistor is coupled between the second storage element and the central node. The third transistor is coupled between the central node and a reference node.

[0004] One embodiment of this invention provides a method for operating a memory device, comprising: receiving a first bit line signal via a first bit line coupled to a first memory cell; receiving a second bit line signal via a second bit line coupled to a second memory cell; and receiving a first word line signal via a first word line coupled to a first transistor shared by the first memory cell and the second memory cell.

[0005] One embodiment of this invention provides a memory device including a first memory cell and a second memory cell. Each of the first memory cell and the second memory cell includes a plurality of active structures, a plurality of gate-defined structures, and a first conductive structure. The active structures extend along a first lateral direction, a first portion of the active structure defining a first signal node, a second portion of the active structure defining a second signal node, and a third portion of the active structure defining a first reference node. The gate-defined structures extend along a second lateral direction perpendicular to the first lateral direction, are disposed above the active structures, a first number of gate-defined structures are coupled to word lines, and a second number of gate-defined structures are coupled to stacked gate lines. The first conductive structure extends along the first lateral direction and is disposed above the second portion of the active structures. The first conductive structure of the first memory cell is coupled to the first conductive structure of the second memory cell. Attached Figure Description

[0006] The nature of this case will be best understood by reading it in conjunction with the accompanying drawings and the following detailed description. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1A The figure shows a circuit diagram of a memory circuit according to some embodiments of this case;

[0008] Figure 1B The diagram illustrates the circuit layout of the memory circuit according to various embodiments;

[0009] Figure 1C The diagram illustrates the circuit layout of the memory cell according to various embodiments;

[0010] Figure 1D The diagram illustrates the circuit layout of two memory cells according to various embodiments;

[0011] Figure 1E The diagram illustrates the circuit layout of the memory cell according to various embodiments;

[0012] Figure 2A The figure shows a circuit diagram of a memory circuit according to some embodiments of this case;

[0013] Figure 2B The diagram illustrates the circuit layout of the memory cell according to various embodiments;

[0014] Figure 3A The figure shows a circuit diagram of a memory circuit according to some embodiments of this case;

[0015] Figure 3B The diagram illustrates the circuit layout of the memory cell according to various embodiments;

[0016] Figure 4 The figure shows a circuit diagram of a memory circuit according to some embodiments of this case;

[0017] Figure 5A The figure shows a circuit diagram of a memory circuit according to some embodiments of this case;

[0018] Figure 5B The diagram illustrates the circuit layout of the memory cell according to various embodiments;

[0019] Figure 6 The figure shows a circuit diagram of a memory circuit according to some embodiments of this case;

[0020] Figure 7 The figure shows a circuit diagram of a memory circuit according to some embodiments of this case;

[0021] Figures 8 to 13The illustration shows a circuit diagram of a memory circuit implemented in a p-type metal-oxide-semiconductor (PMOS) according to some embodiments of this case;

[0022] Figure 14 The diagram illustrates a flowchart of a method for operating a memory circuit according to some embodiments of this case.

[0023] [Symbol Explanation]

[0024] 100: Memory Circuit

[0025] 200: Memory Circuit

[0026] 240: Memory Unit

[0027] 300: Memory Circuit

[0028] 340: Memory Unit

[0029] 400: Memory Circuit

[0030] 500: Memory Circuit

[0031] 540: Memory Unit

[0032] 600: Memory Circuit

[0033] 700: Memory Circuit

[0034] 800: Memory Circuit

[0035] 900: Memory Circuit

[0036] 1000: Memory Circuit

[0037] 1100: Memory Circuit

[0038] 1200: Memory Circuit

[0039] 1400: Method

[0040] 1410: Operation

[0041] 1420: Operation

[0042] BL[0]: Bit line

[0043] BL[N]: Bit line

[0044] BL0: Bitline

[0045] BL1: Bitline

[0046] BL2: Bitline

[0047] BL3: Bitline

[0048] CS[0]: Transistor

[0049] CS[N]: Transistor

[0050] CS00: Transistor

[0051] CS01: Transistor

[0052] PU: Pickup device

[0053] PUL0: Pull-up cable

[0054] R[0]: Storage element

[0055] R00: Resistor

[0056] R01: Resistor

[0057] SW0: Switch

[0058] SWL0: Switch gate line

[0059] UC00: Memory Unit

[0060] UC01: Memory Unit

[0061] UC02: Memory Unit

[0062] UC03: Memory Unit

[0063] UC10: Memory Unit

[0064] UC11: Memory Unit

[0065] VC0: Node

[0066] VD0: Node

[0067] WL0: Wordline

[0068] WLS[0]: Second transistor

[0069] WLS0: Transistor

[0070] WLS0[0]: Second transistor

[0071] WLS1: Transistor

[0072] CG0: Overlapping gate line

[0073] CG1: Overlapping gate line

[0074] CS10: Transistor

[0075] CS11: Transistor

[0076] R10: Resistor

[0077] R11: Resistor

[0078] VD1: Node

[0079] WL1: Wordline Detailed Implementation

[0080] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the subject matter. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0081] In addition, for ease of description, this document uses spatially relative terms (such as "below," "under," "lower part," "above," "upper part," and the like) to describe the relationship between one element or feature illustrated in the figures and another element or feature. Besides the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatially relative descriptive terms used herein can be interpreted in the same way.

[0082] In high-voltage applications such as fuses, antifuses, and one-time-programmable (OTP) memory, stacked transistor selectors are used instead of single-transistor selectors to ensure device reliability by reducing the voltage stress on each transistor in the stacked selector. However, stacking transistors requires doubling the size of each transistor to maintain the same drive capability. Therefore, without further improvements, stacked transistor selectors can occupy approximately four times the area of ​​a single-transistor selector. Furthermore, the larger memory cell size increases the voltage drop across memory cell interconnects due to parasitic resistance of interconnects and the longer distance current travels during read and write operations.

[0083] This application provides various embodiments of memory circuits, methods, and apparatuses in which two or more memory cells share a portion of a stacked transistor selector. That is, in various embodiments, the stacked transistors of two or more stacked transistor selectors share a common source transistor. Advantageously, the disclosed embodiments of memory circuits, methods, and apparatuses can achieve several benefits. In some embodiments, by sharing a portion of the stacked transistor selector, the disclosed embodiments of memory circuits, methods, and apparatuses reduce the area of ​​the memory cells (e.g., by up to 25% or any of other various percentages). In some embodiments, by sharing a portion of the stacked transistor selector, the disclosed embodiments of memory circuits, methods, and apparatuses expand the drive capability of the stacked transistor selector without increasing the area of ​​the memory cells or degrading reliability. In some embodiments, by sharing a portion of the stacked transistor selector, the disclosed embodiments of memory circuits, methods, and apparatuses reduce parasitic voltage drops without degrading drive capability or reliability.

[0084] Figure 1A The figure shows a circuit diagram of a memory circuit 100 according to some embodiments of this invention. The memory circuit 100 may also be referred to as a memory array. The memory circuit 100 includes several memory cells, such as memory cells UC00, UC01, UC10, and UC11. A memory cell may also be referred to as a unit cell. The memory cells can be arranged in a row-column configuration, wherein each column has a bit line (BL) and a cascode gate line (CGL), and each row has a word line (WL). The BL and CGL of each column are respectively coupled to several memory cells arranged in that column, and each memory cell in that column is arranged in a different row and coupled to a corresponding (different) WL. Similarly, the WL of each row is respectively coupled to several memory cells arranged in that row, and each memory cell in that row is arranged in a different column and coupled to a corresponding (different) BL and CGL.

[0085] See also Figure 1A More specifically, for illustrative purposes, four memory cells UC00, UC01, UC10, and UC11 are illustrated in memory circuit 100. Memory cells UC00 and UC10 are arranged along a first column and coupled to bit line BL0 and stacked gate line CG0; memory cells UC01 and UC11 are arranged along a second column and coupled to bit line BL1 and stacked gate line CG1; memory cells UC00 and UC01 are arranged along a first row and coupled to word line WL0; and memory cells UC10 and UC11 are arranged along a second row and coupled to word line WL1. Although Figure 1AThe memory circuit 100 is illustrated as a two-by-two array of memory cells. The memory circuit 100 may include any number of rows (and corresponding WL) and any number of columns (and corresponding BL), while still within the scope of this application.

[0086] like Figure 1A As shown, each memory cell includes a storage element, a first transistor coupled to the storage element, and a second transistor coupled to the first transistor. For example, memory cell UC00 includes a resistor R00 as a storage element, a transistor CS00 as the first transistor coupled to the resistor R00, and a transistor WLS0 as the second transistor coupled to the transistor CS00. Specifically, in some embodiments, one end of the resistor R00 is coupled to the drain of the transistor CS00, and the source of the transistor CS00 is coupled to the drain of the transistor WLS0. The node between the storage element and the first transistor may be referred to as VD. For example, the node between the resistor R00 and the transistor CS00 is VD0.

[0087] In each memory cell, a corresponding BL is coupled to a storage element, a corresponding CGL is coupled to a first transistor, and a corresponding WL is coupled to a second transistor. For example, in memory cell UC00, bit line BL0 is coupled to resistor R00, stacked gate line CG0 is coupled to transistor CS00, and word line WL0 is coupled to transistor WLS0. Specifically, in some embodiments, bit line BL0 is coupled to the second end of resistor R00, stacked gate line CG0 is coupled to the gate of transistor CS00, and word line WL0 is coupled to the gate of transistor WLS0.

[0088] Two or more memory cells have separate first transistors and storage elements. For example, memory cell UC01 includes a resistor R01 as its storage element and a transistor CS01 as its first transistor.

[0089] Two or more memory cells share a second transistor. For example, memory cells UC00 and UC01 share transistor WLS0 as their respective second transistors. The shared second transistor is coupled to the first transistors of the two or more memory cells at the same node (VC). For example, transistor WLS0 is coupled to transistor CS00 of memory cell UC00 and transistor CS01 of memory cell UC01 at node VC0. Specifically, in some embodiments, the drain of transistor WLS0 is coupled to the source of transistor CS00 of memory cell UC00 and the source of transistor CS01 of memory cell UC01.

[0090] like Figure 1AAs shown, the memory element is a resistor. In some embodiments, a resistor is used as a memory element when programming the memory element includes providing current to destroy the memory element. In some embodiments, the memory element may be any of a memristor, capacitor, inductor, or other various types of memory element or a suitable element for an electric fuse, all of which are still within the scope of this invention. In some embodiments, a capacitor is used as a memory element when programming the memory element includes providing voltage to destroy the memory element.

[0091] like Figure 1A As shown, each of the first transistor (e.g., transistor CS00) and the second transistor (e.g., transistor WLS0) is an n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, the advantage of using NMOS transistors for the first and second transistors is that NMOS devices are faster than PMOS devices, with faster read and write operations. Specifically, in some embodiments, the mobility of electrons (charge carriers in the case of NMOS transistors) is approximately twice that of holes (charge carriers in PMOS transistors).

[0092] The first and second transistors can be any of various other transistor types, while still within the scope of this application. The first and second transistors can be MOS device types having any of the following: standard threshold voltage (SVT), low threshold voltage (LVT), high threshold voltage (HVT), high voltage (HV), input / output (IO), or various other MOS device types. Each first transistor can be referred to as a stacked transistor, and each second transistor can be referred to as a common-source transistor. The first and second transistors can be collectively referred to as a selector, a stacked selector, or a stacked selector transistor.

[0093] Transistor WLS0 is coupled to the first reference node. For example, as... Figure 1A As shown, transistor WLS0 is coupled to ground. Specifically, in some embodiments, the source of transistor WLS0 is coupled to ground. Transistor WLS0 may be coupled to any of various other reference nodes, while still remaining within the scope of this application.

[0094] In some embodiments, a write operation is performed on a memory cell (e.g., memory cell UC10), thereby receiving a BL signal of a first value via its corresponding BL line, a CGL signal of a second value via its corresponding CGL line, and a WL signal of a third value via its corresponding WL line. The first value may be 1.8V, the second value may be 0.9V, and the third value may be 0.9V, although each of the BL, CGL, and WL signals may have any of various values, which are still within the scope of this invention. Due to the write operation, the state (e.g., resistance) of a storage element (e.g., resistor R00) is changed. The write operation may be referred to as a programming operation.

[0095] In some embodiments, a read operation is performed on a memory cell, thereby receiving a BL signal of a fourth magnitude via its corresponding BL line, a CGL signal of a fifth magnitude via its corresponding CGL line, and a WL signal of a sixth magnitude via its corresponding WL line. The fourth magnitude may be 0.4V, the fifth magnitude may be 0.75V, and the sixth magnitude may be 0.75V, although each of the BL, CGL, and WL signals may have any of various magnitudes, which are still within the scope of this application.

[0096] Table 1 illustrates the bias conditions. Each bias condition includes the corresponding semaphore values ​​for WL, BL, CGL, VD, and VC when a memory cell is written to, read from, or either of these actions (e.g., spare). Selecting only WL or only BL implies that a second memory cell in the same row or column is being written to or read from. When the second memory cells are in the same row, it is assumed that the memory cell and the second memory cell share the same WLS transistor. The term "~X" means that the value is X or substantially close to X, where X is the quantity.

[0097]

[0098] Table 1

[0099] Figure 1BThe illustration shows the circuit layout of a memory circuit 100 according to various embodiments. Each memory cell of the memory circuit 100 includes a plurality of active (OD) structures extending in a first lateral direction and spaced apart from each other along a second lateral direction perpendicular to the first lateral direction. For example, memory cell UC00 includes a plurality of OD structures. In some embodiments, the OD structures are doped (e.g., with p-type or n-type dopant) semiconductor materials. In some embodiments, the OD structures are disposed above a semiconductor substrate. In some embodiments, well (e.g., n-well or p-well) structures are disposed above the OD structures. It will be understood that when A is disposed above B, it means that A is spaced apart from B in a vertical direction perpendicular to the first and second lateral directions, although A can still be coupled to B (e.g., the space may include vias extending in the vertical direction, thereby coupling A to B).

[0100] Each unit cell of the memory circuit 100 includes a plurality of gate-defined (GD) structures extending in a second lateral direction and spaced apart from each other along the first lateral direction. The GD structures are disposed above the OD structure. The plurality of GD structures in each memory cell (e.g., n1 + n2, where n1 and n2 are integers) are coupled to a word line corresponding to the row of the memory cell, e.g., word line WL0. Such GD structures may be referred to as WL GD structures. A WL GD structure superimposed on the OD structure is equivalent to a unit of a second transistor, such as transistor WLS0. A unit of a transistor may be referred to as a finger.

[0101] In some embodiments, the ratio of the number of first transistor units (e.g., fingers) multiplied by the width of the first transistor unit (e.g., the width of an OD structure extending in the second direction) multiplied by the gate length of the first transistor unit (e.g., the width of a GD structure extending in the first direction) to the number of second transistor units multiplied by the width of the second transistor unit multiplied by the gate length of the second transistor unit is 1, greater than 1, 2, greater than 2, or any other number of such units. For example, in some embodiments, the width of the unit transistors is the same, the gate length of the unit transistors is the same, and m is equal to n1+n2, 2n1+2n2, or any other number of such GD structures.

[0102] Several GD structures (e.g., m, where m is an integer) are coupled to stacked gate lines corresponding to columns of memory cells, such as stacked gate lines CG0. Such GD structures may be referred to as CGL GD structures. A stacked CGL GD structure superimposed on an OD structure is equivalent to a unit of a first transistor, such as transistor CS00. Each GD structure may comprise any of Cu, Al, Co, Ru, W, polysilicon, or other various conductive materials.

[0103] Each unit cell of memory circuit 100 includes a fuse link. A fuse link is... Figure 1A The layout of the storage element includes, for example, a resistor R00. A fuse link is coupled at one end to a bit line, such as bit line BL0. The fuse link is coupled at the other end to the OD of a first transistor, such as transistor CS00.

[0104] Each unit cell of memory circuit 100 includes a pickup (PU). The pickup may be referred to as a p-well. The pickup provides a contact point to the substrate. Pickups may be required for compliance with design rules.

[0105] Figure 1C The diagram illustrates the circuit layout of the memory unit UC00 according to various embodiments. Figure 1C The purpose is to illustrate examples of conductive structures for various transistor units coupled to a memory cell UC00. The memory cell UC00 includes a plurality of first conductive structures (e.g., M0 structures) spaced apart from each other in a first lateral direction and along a second lateral direction. Each of the first conductive structures is disposed above a plurality of OD portions. For example, conductive structure VD0 M0 is disposed above a first number of OD portions in the first row, conductive structure VCO M0 is disposed above a second number of OD portions in the first row, and conductive structure ground M0 is disposed above a third number of OD portions in the first row. Each OD portion may refer to a segment of OD structure between two adjacent GD structures. Each of the plurality of OD portions may be coupled to an associated conductive structure via a via (such as an OD-M0 via).

[0106] In some embodiments, a first number of OD portions may define a VD node, a second number of OD portions may define a VC node, and a third number of OD portions may define a first reference node. Although the first conductive structure extends above the first row, it will be understood that additional conductive structures may extend above other rows. In some embodiments, each of the first conductive structures extends to an adjacent memory cell (e.g., memory cell UC01) and is disposed above the OD portion of the adjacent memory cell. Each of the first conductive structures may include any of Cu, Al, Co, Ru, W, or other various conductive materials.

[0107] The memory cell UC00 includes a plurality of second conductive structures (e.g., M1 structures) spaced apart from each other in a second lateral direction and along a first lateral direction. Each of the second conductive structures is disposed above a plurality of first metal structures. Furthermore, each of the second conductive structures is disposed above a plurality of OD portions. For example, conductive structure VD0 M1 is disposed above a fourth number of OD portions in the first column, conductive structure VCO M1 is disposed above a fifth number of OD portions in the second column, and conductive structure ground M1 is disposed above a sixth number of OD portions in the third column. Each of the plurality of OD portions can be coupled to an associated conductive structure via a combination of vias and conductive structures (such as OD-M0 vias, M0 structures, and M0-M1 vias).

[0108] Although the second conductive structure extends above three columns, it will be understood that additional metal structures may extend above other columns. In some embodiments, each of the second conductive structures extends to an adjacent memory cell (e.g., memory cell UC10) and is disposed above the OD portion of the adjacent memory cell. Each of the second conductive structures may include any of Cu, Al, Co, Ru, W, or various other conductive materials.

[0109] Figure 1D The diagram illustrates the circuit layout of memory unit UC00 and memory unit UC01 according to various embodiments. Figure 1D Similar to Figure 1C ,Apart from Figure 1D The diagram illustrates how conductive structures couple various transistor units across multiple memory cells. One application of coupling transistor units across multiple memory cells is when multiple memory cells share the same one or more common source transistor units.

[0110] In some embodiments, VC nodes are shared among multiple memory cells. For example, conductive structure VCO M0 is disposed above a second number of OD portions in the first row of memory cell UC00 and a second number of OD portions in the first row of memory cell UC01. In some embodiments, ground nodes are shared among multiple memory cells. For example, conductive structure ground M0 is disposed above a third number of OD portions in the first row of memory cell UC00 and a third number of OD portions in the first row of memory cell UC01. In some embodiments, VD nodes are not shared among multiple memory cells. For example, memory cell UC00 has a first VD node and memory cell UC01 has a second memory cell UC01. In some embodiments, conductive structure VD0 M0 is disposed above a first number of OD portions in the first row of memory cell UC00, and conductive structure VD1 M0 is disposed above a first number of OD portions in the first row of memory cell UC01.

[0111] Figure 1E The diagram illustrates the circuit layout of the memory unit UC00 according to various embodiments. Figure 1E The purpose is to illustrate the high-level layout arrangement. WLN represents the layout area of ​​a transistor unit including a second transistor (e.g., transistor WLS0), CGN represents the layout area of ​​a transistor unit including a first transistor (e.g., transistor CS00), fuse link represents the layout area including a storage element (e.g., resistor R00), and PU represents the layout area including a connection to the substrate.

[0112] In some embodiments, the memory cell UC00 is a 3x3 array of regions. In some embodiments, the first row includes a WLN region, a CGN region, and a WLN region; the second row adjacent to the first row includes a PU region, a fuse link region, and a PU region; and the third row adjacent to the second row includes a WLN region, a CGN region, and a WLN region. In some embodiments, the first column includes a WLN region, a PU region, and a WLN region; the second column adjacent to the first column includes a CGN region, a fuse link region, and a CGN region; and the third column adjacent to the second column includes a WLN region, a PU region, and a WLN region. Although Figure 1E The memory cell UC00 is illustrated as a 3x3 array of regions, and the memory cell UC00 can include any number of regions.

[0113] Figure 2A The figure shows a circuit diagram of a memory circuit 200 according to some embodiments of this case. The memory circuit 200 is similar to... Figure 1A The memory circuit 100, except that the memory circuit 200 is a 2x2N array of memory cells, wherein every N memory cells share a common source transistor, where N is equal to 3 or more. In some embodiments, the advantage of sharing a common source transistor among N memory cells is that, for a given number of memory cells, the memory cell size is smaller than that in the case where only two memory cells share a common source transistor. Although Figure 2A The memory circuit 100 is illustrated as a 2x2N array of memory cells. The memory circuit 100 may include any number of rows (and corresponding WL) and any number of columns (and corresponding BL), while still within the scope of this invention. In some embodiments, the common source transistors WLS[N-1:0] corresponding to the N memory cells in the first N columns are not shared with the common source transistors WLS[2N-1:N] corresponding to the N memory cells in the last N columns.

[0114] As in Figure 1A middle, Figure 2AEach of the memory cells includes a corresponding storage element, a first transistor, and a second transistor. For example, memory cell UC00 includes a storage element R[0], a first transistor CS[0], and a second transistor WLS0[0], and memory cell UC01 includes a storage element R[1], a first transistor CS[1], and a second transistor WLS0[0], etc.

[0115] Figure 2B The diagram illustrates the circuit layout of memory cell 240 according to various embodiments. Memory cell 240 is similar to... Figure 1E The memory cell UC00, except that each of the memory cells 240 (e.g., memory cells UC00, UC01, UC02, and UC03) shares the same common source transistor WLS. In some embodiments, such as Figure 2A The advantage of arranging the memory cells 240 as shown is that routing between the shared source transistors and the memory cells is easier to implement because all the shared source transistors are located in the same column. In some embodiments, memory cells UC00, UC01, UC02, and UC03 are memory cells in the first N columns.

[0116] In some embodiments, memory cells 240 are a 3x5 array of regions. In some embodiments, the first row includes the CGN of memory cell UC00 region, the CGN of memory cell UC01 region and a shared WLN region, the CGN of memory cell UC02 region and the CGN of memory cell UC03 region; the second row adjacent to the first row includes the fuse links of memory cell UC00 region, the fuse links of memory cell UC01 region, the PU region, the fuse links of memory cell UC02 region and the fuse links of memory cell UC03 region; and the third row adjacent to the second row includes the CGN of memory cell UC00 region, the CGN of memory cell UC01 region and a shared WLN region, the CGN of memory cell UC02 region and the CGN of memory cell UC03 region.

[0117] In some embodiments, the first column includes the CGN of the memory cell UC00 region, the fuse link of the memory cell UC00 region, and the CGN of the memory cell UC00 region; the second column adjacent to the first column includes the CGN of the memory cell UC01 region, the fuse link of the memory cell UC01 region, and the CGN of the memory cell UC01 region; the third column adjacent to the second column includes the WLN region, the PU region, and the WLN region; the fourth column adjacent to the third column includes the CGN of the memory cell UC02 region, the fuse link of the memory cell UC02 region, and the CGN of the memory cell UC02 region; and the fifth column adjacent to the fourth column includes the CGN of the memory cell UC03 region, the fuse link of the memory cell UC03 region, and the CGN of the memory cell UC03 region. Although Figure 2B The memory cell 240 is illustrated as a 3x5 array of regions, and the memory cell 240 may include any number of regions.

[0118] Figure 3A The figure shows a circuit diagram of a memory circuit 300 according to some embodiments of this case. The memory circuit 300 is similar to... Figure 2A The memory circuit 200 includes distributed shared source transistors. In some embodiments, the advantage of distributed shared source transistors WLS[N-1:0] is that the distance between the stacked transistors in each memory cell and the nearest shared source transistor is reduced. This can result in a reduction of parasitic resistance between the stacked transistors and the shared source transistors.

[0119] Figure 3B The diagram illustrates the circuit layout of memory cell 340 according to various embodiments. Memory cell 340 is similar to... Figure 2B The memory cell 240, in addition to the shared source transistor of the distributed memory cell 340. In some embodiments, the advantage of the distributed shared source transistor is that the distance between the stacked transistor in each memory cell and the nearest shared source transistor is reduced and the parasitic resistance due to routing is reduced.

[0120] In some embodiments, memory cells 340 are a 3x8 array of regions. In some embodiments, the first row includes a first portion of a distributed shared WLN region, a CGN of memory cell UC00 region, a CGN of memory cell UC01 region, a second portion of a distributed shared WLN region, a third portion of a distributed shared WLN region, a CGN of memory cell UC02 region, a CGN of memory cell UC03 region, and a fourth portion of a distributed shared WLN region; the second row adjacent to the first row includes a PU region, fuse links of memory cell UC00 region, fuse links of memory cell UC01 region, a PU region, a PU region, fuse links of memory cell UC02 region, fuse links of memory cell UC03 region, and a PU region; and the third row adjacent to the second row includes the same components as the first row.

[0121] In some embodiments, the first column includes a first portion of a shared WLN region, a PU region, and a second portion of a shared WLN region; the second column adjacent to the first column includes a CGN of a memory cell UC00 region, a fuse link of a memory cell UC00 region, and a third column adjacent to the second column includes a CGN of a memory cell UC01 region, a fuse link of a memory cell UC01 region, and a fourth column adjacent to the third column includes a second portion of a shared WLN region, a PU region, and a second portion of a shared WLN region; The fifth column adjacent to the fourth column includes the third part of the shared WLN region, the PU region, and the third part of the shared WLN region; the sixth column adjacent to the fifth column includes the CGN of the memory cell UC02 region, the fuse link of the memory cell UC02 region, and the CGN of the memory cell UC02 region; the seventh column adjacent to the sixth column includes the CGN of the memory cell UC03 region, the fuse link of the memory cell UC03 region, and the CGN of the memory cell UC03 region; and the eighth column adjacent to the seventh column includes the fourth part of the shared WLN region, the PU region, and the fourth part of the shared WLN region. Although Figure 3B The memory cell 340 is illustrated as a 3x8 array of regions, and the memory cell 340 may include any number of regions.

[0122] Figure 4 The figure shows a circuit diagram of a memory circuit 400 according to some embodiments of this case. The memory circuit 400 is similar to... Figure 3AThe memory circuit 300, except that the common source transistors WLS[N-1:0] corresponding to the N memory cells in the first N columns are coupled to the common source transistors WLS[2N-1:N] corresponding to the N memory cells in the last N columns. Therefore, each of the 2N cells shares 2N common source transistors. In some embodiments, the advantage of sharing 2N common source transistors among the 2N memory cells is that the distance between the stacked transistors and the average common source transistor in each memory cell is reduced. This can result in a reduction of parasitic resistance between the stacked transistors and the shared source transistors.

[0123] Figure 5A The figure shows a circuit diagram of a memory circuit 500 according to some embodiments of this case. The memory circuit 500 is similar to... Figure 4 The memory circuit 400 has a common source transistor WLS[0] located outside the array of memory cells. In some embodiments, the advantage of moving the common source transistor WLS[0] outside the array of memory cells is that routing between the common source transistor and the memory cells is easier to implement.

[0124] In some embodiments, the common-source transistor WLS[0] is coupled to the pull-up transistor pull-up0. Specifically, in some embodiments, the drain node of the common-source transistor WLS[0] is coupled to the drain node of the pull-up transistor pull-up0. In some embodiments, the common-source transistor is an NMOS transistor and the pull-up transistor pull-up0 is a PMOS transistor. In some embodiments, the pull-up transistor pull-up0 is coupled to the pull-up line PUL0. In some embodiments, the pull-up transistor pull-up0 receives a pull-up signal via its pull-up line PUL0.

[0125] Figure 5B The diagram illustrates the circuit layout of memory cell 540 according to various embodiments. Memory cell 540 is similar to... Figure 2B The memory cell 240 is separated from the memory cell 540 except for the common source transistor. In some embodiments, the advantage of separating the array of common source transistors from the memory cells is that routing between the common source transistors and the memory cells is easier to implement.

[0126] In some embodiments, memory cells 540 are a 3x4 array of regions. In some embodiments, the first row includes the CGN of memory cell UC00 region, the CGN of memory cell UC01 region, the CGN of memory cell UC02 region, and the CGN of memory cell UC03 region; the second row adjacent to the first row includes the fuse links of memory cell UC00 region, the fuse links of memory cell UC01 region, the fuse links of memory cell UC02 region, and the fuse links of memory cell UC03 region; and the third row adjacent to the second row includes the same as the first row.

[0127] In some embodiments, the first column includes the CGN of the memory cell UC00 region, the fuse link of the memory cell UC00 region, and the CGN of the memory cell UC00 region; the second column adjacent to the first column includes the CGN of the memory cell UC01 region, the fuse link of the memory cell UC01 region, and the CGN of the memory cell UC01 region; the third column adjacent to the second column includes the CGN of the memory cell UC02 region, the fuse link of the memory cell UC02 region, and the CGN of the memory cell UC02 region; the fourth column adjacent to the third column includes the CGN of the memory cell UC03 region, the fuse link of the memory cell UC03 region, and the CGN of the memory cell UC03 region. Although Figure 5B The memory cell 540 is illustrated as a 3x4 array of regions, and the memory cell 540 may include any number of regions.

[0128] Figure 6 The figure shows a circuit diagram of a memory circuit 600 according to some embodiments of this case. The memory circuit 600 is similar to... Figure 3A The memory circuit 300, in addition to the memory cell 600 including a switch SW0, can be used to share or reuse common source transistors WLS0 and WLS1 or to isolate common source transistors WLS0 and WLS1. In some embodiments, the advantage of sharing common source transistors is higher drive capability for each memory cell. In some embodiments, the advantage of isolating common source transistors is reduced leakage. The application of isolated common source transistors is in memory cells where the storage element is sufficiently sensitive to changes in programming signals (e.g., current or voltage) such that leakage from the shared common source transistors leads to the programming of the memory cell even if no programming memory cell is selected.

[0129] In some embodiments, switch SW0 is coupled to switch gate line SWL0. In some embodiments, switch SW0 can be enabled by receiving a switch enable signal of a first magnitude via its switch gate line SW0. The first magnitude may be 1.8V, although the switch enable signal may have any of a variety of first magnitudes, which are still within the scope of this invention. In some embodiments, switch SW0 can be disabled by receiving a switch enable signal of a second magnitude via its switch gate line. The second magnitude may be 0V, although the switch enable signal may have any of a variety of second magnitudes, which are still within the scope of this invention.

[0130] Figure 7 The figure shows a circuit diagram of a memory circuit 700 according to some embodiments of this case. The memory circuit 700 is similar to... Figure 3A The memory circuit 300, in addition to being used to share or reuse common-source transistors WLS0 and WLS1, or to isolate common-source transistors WLS0 and WLS1, is used because common-source transistor WLS0 is coupled to WL0 and common-source transistor WLS1 is coupled to the word lift line WL0boost. In some embodiments, the advantage of sharing common-source transistors is higher drive capability per memory cell. In some embodiments, the advantage of isolating common-source transistors is reduced leakage. In some embodiments, the advantage of memory circuit 700 compared to memory circuit 600 is that the memory cell area of ​​memory circuit 700 is smaller than that of memory circuit 600 because additional switches are required for memory circuit 600.

[0131] In some embodiments, the common-source transistor WLS0 can be isolated from the common-source transistor WLS1 by receiving a word line signal of a first value via its word line and a word line boost signal of a second value via its word boost line. The first value may be 0.9V and the second value may be 0V, although each of WL and the WL boost signal may have any of various values, which are still within the scope of this invention. In some embodiments, the common-source transistor WLS0 can be shared with the common-source transistor WLS1 by receiving a word line signal of a first value via its word line and a word line boost signal of a third value via its word boost line. The third value may be 0.9V, although the WL boost signal may have any of various values, which are still within the scope of this invention.

[0132] Figures 8 to 13 The figure shows a circuit diagram of a memory circuit implemented in a PMOS according to some embodiments of this case. Figure 8 The figure shows a circuit diagram of a memory circuit 800 according to some embodiments of this case. This memory circuit is Figure 2AThe memory circuit 200 is implemented using a PMOS transistor. For example, each of the first transistor CS[0] and the second transistor WLS0[0] is a PMOS transistor. In some embodiments, the advantage of using PMOS transistors for the memory circuit 800 is that PMOS technology is a highly controllable and low-cost process with good yield and high immunity.

[0133] Figure 9 The figure shows a circuit diagram of a memory circuit 900 according to some embodiments of this case. This memory circuit is Figure 3A The PMOS implementation of the memory circuit 300. Figure 10 The figure shows a circuit diagram of a memory circuit 1000 according to some embodiments of this case. This memory circuit is Figure 4 The PMOS implementation of the memory circuit 400. Figure 11 The figure shows a circuit diagram of a memory circuit 1100 according to some embodiments of this case. This memory circuit is Figure 5A The PMOS implementation of the memory circuit 500. Figure 12 The figure shows a circuit diagram of a memory circuit 1200 according to some embodiments of this case. This memory circuit is Figure 6 The PMOS implementation of the memory circuit 600. Figure 13 The diagram shows a circuit diagram of a memory circuit 1300 according to some embodiments of this case. This memory circuit is... Figure 7 The PMOS implementation of the memory circuit 700.

[0134] Figure 14 The illustration shows a flowchart of a method 1400 for operating one or more memory circuits 100-1300 according to some embodiments of this invention. It should be noted that method 1400 is merely an example and is not intended to limit the scope of this invention. Therefore, it will be understood that additional operations may be performed... Figure 14 The method 1400 is provided before, during, and after the method, and some other operations are only briefly described herein. In some embodiments, the method 1400 is performed by one or more memory circuits 100-1300.

[0135] In operation 1410, memory circuit (e.g., Figure 1A The memory circuit 100) is coupled to the first memory cell (e.g., Figure 1A The first bit line of the memory cell UC00 (for example, Figure 1A The first bit line signal is received by the bit line BL0. In operation 1420, the memory circuitry is coupled to the second memory cell (e.g., ...). Figure 1A The second bit line of the memory cell UC01 (for example, Figure 1AThe second bit line signal is received by the bit line BL1. In operation 1430, the memory circuit is coupled to a first transistor (e.g., ) shared by the first memory cell and the second memory cell. Figure 1A The word line of the transistor WLS0 (e.g., Figure 1A The word line WL0 receives the first word line signal.

[0136] In some embodiments, the memory circuitry is coupled to a first stacked gate line (e.g., ...) of the first memory cell. Figure 1A The memory circuit receives the first stacked gate signal via a second stacked gate line (CG0) coupled to the second memory cell. In some embodiments, the memory circuit receives the first stacked gate signal via a second stacked gate line (e.g., CG0) coupled to the second memory cell. Figure 1A The memory circuit receives the second stacked gate signal via a first pull-up gate line (CG1) coupled to the first memory cell and the second memory cell. In some embodiments, the memory circuit receives the second stacked gate signal via a first pull-up gate line (CG1) coupled to the first memory cell and the second memory cell. Figure 5A The pull-up line PUL0 receives the first pull-up gate signal.

[0137] In some embodiments, the memory circuitry is coupled via a switch (e.g., Figure 6 The switch gate line of the switch SW0) (e.g., Figure 6 The switching gate line SWL0 receives a first switching gate signal that couples a first transistor unit of a first transistor to a second transistor unit of a second transistor, wherein the first transistor unit includes a first transistor unit and the second transistor unit includes a second transistor unit. In some embodiments, the memory circuitry receives a first switching gate signal (e.g., SWL0) that couples to a second word line (e.g., SWL0) of a first transistor shared by the first memory unit and the second memory unit. Figure 7 The word lift-up line (WL0boost) receives the second word line signal, wherein the word line is coupled to the first transistor unit of the first transistor and the second word line is coupled to the second transistor unit of the first transistor.

[0138] In some embodiments of this case, a memory circuit is disclosed. In some embodiments, the memory circuit includes: a first storage element coupled to a first bit line; a first transistor coupled between the first storage element and a central node; a second storage element coupled to a second bit line; a second transistor coupled between the second storage element and the central node; and a third transistor coupled between the central node and a reference node.

[0139] In some embodiments, the memory circuitry includes: a third storage element coupled to a third bit line; and a third transistor coupled between the third storage element and a central node.

[0140] In some embodiments, each of the first transistor and the second transistor is an N-type metal-oxide-semiconductor (NMOS) transistor, and the reference node is a ground node. In some embodiments, the memory circuitry includes a pull-up transistor coupled between the center node and the supply node.

[0141] In some embodiments, each of the first and second transistors is a P-type metal-oxide-semiconductor (PMOS) transistor, and the reference node is a supply node. In some embodiments, the memory circuitry includes a pull-down transistor coupled between a center node and a ground node.

[0142] In some embodiments, each of the first storage element and the second storage element is a resistor. In some embodiments, each of the first storage element and the second storage element is a capacitor.

[0143] In some embodiments, a first transistor is coupled to a first stacked gate line, a second transistor is coupled to a second stacked gate line, and a third transistor is coupled to a word line. In some embodiments, the first and third transistors are the same size. In some embodiments, the first transistor is smaller than the third transistor.

[0144] In some embodiments of this application, a method for operating a memory device is disclosed. In some embodiments, the method includes: receiving a first bit line signal via a first bit line coupled to a first memory cell; receiving a second bit line signal via a second bit line coupled to a second memory cell; and receiving a first word line signal via a word line coupled to a first transistor shared by the first memory cell and the second memory cell.

[0145] In some embodiments, the method includes: receiving a first stacked gate signal via a first stacked gate line coupled to a first memory cell; and receiving a second stacked gate signal via a second stacked gate line coupled to a second memory cell. In some embodiments, the method includes receiving a first pull-up gate signal via a first pull-up gate line coupled to the first memory cell and the second memory cell.

[0146] In some embodiments, the method includes: receiving a first switching gate signal via a switching gate line that couples a first transistor unit of a first transistor to a second transistor unit of a second transistor, wherein a first memory cell includes a first transistor unit and a second memory cell includes a second transistor unit. In some embodiments, the method includes: receiving a second word line signal via a second word line coupled to a first transistor shared by the first memory cell and the second memory cell, wherein the word line is coupled to a first transistor unit of the first transistor and the second word line is coupled to a second transistor unit of the first transistor.

[0147] In some embodiments of this invention, a memory device is disclosed. In some embodiments, the memory device includes a first memory cell and a second memory cell. In some embodiments, each of the first memory cell and the second memory cell includes a plurality of active structures extending along a first lateral direction. In some embodiments, a first portion of the plurality of active structures defines a first signal node. In some embodiments, a second portion of the plurality of active structures defines a second signal node. In some embodiments, a third portion of the plurality of active structures defines a first reference node.

[0148] In some embodiments, each of the first memory cell and the second memory cell includes a plurality of gate-defined (GD) structures extending along a second lateral direction perpendicular to the first lateral direction. In some embodiments, the plurality of GD structures are disposed above a plurality of active structures. In some embodiments, a first number of the plurality of GD structures are coupled to word lines, and a second number of the plurality of GD structures are coupled to stacked gate lines.

[0149] In some embodiments, each of the first memory cell and the second memory cell includes a first conductive structure extending along a first lateral direction. In some embodiments, the first conductive structure is disposed above a second portion of a plurality of active structures. In some embodiments, the first conductive structure of the first memory cell is coupled to the first conductive structure of the second memory cell.

[0150] In some embodiments, each of the first memory cell and the second memory cell includes a fuse link extending in a first direction. In some embodiments, the fuse link is coupled to a bit line. In some embodiments, each of the first memory cell and the second memory cell includes a second conductive structure extending in a second direction. In some embodiments, the second conductive structure is disposed above the fuse link and a first portion of a plurality of active structures.

[0151] In some embodiments, the ratio of a first number of multiple GD structures to a second number of multiple GD structures is greater than 1. In some embodiments, the ratio of a first number of multiple GD structures to a second number of multiple GD structures is greater than 2.

[0152] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that this invention can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this invention.

Claims

1. A memory circuit, characterized in that, Include: A first storage element, the first storage element being coupled to a first bit line; A first transistor, wherein a first source / drain of the first transistor is coupled to the first storage element, and a second source / drain of the first transistor is coupled to a central node; A second storage element, the second storage element being coupled to a second bit line; A second transistor, wherein a first source / drain of the second transistor is coupled to the second storage element, and a second source / drain of the second transistor is coupled to the center node; as well as A third transistor is coupled between the central node and a reference node.

2. The memory circuit as described in claim 1, characterized in that, Further includes: A third storage element, the third storage element being coupled to a third bit line; and A third transistor is coupled between the third storage element and the central node.

3. The memory circuit as described in claim 1, characterized in that, Each of the first transistor and the second transistor is an N-type metal-oxide-semiconductor transistor, and the reference node is a ground node.

4. The memory circuit as described in claim 3, characterized in that, It further includes a pull-up transistor coupled between the center node and a supply node.

5. The memory circuit as described in claim 1, characterized in that, Each of the first transistor and the second transistor is a P-type metal-oxide-semiconductor transistor, and the reference node is a supply node.

6. The memory circuit as described in claim 5, characterized in that, It further includes a pull-down transistor coupled between the center node and a ground node.

7. The memory circuit as described in claim 1, characterized in that, Each of the first storage element and the second storage element is a resistor.

8. The memory circuit as described in claim 1, characterized in that, Each of the first storage element and the second storage element is a capacitor.

9. The memory circuit as described in claim 1, characterized in that, The first transistor is coupled to a first stacked gate line, the second transistor is coupled to a second stacked gate line, and the third transistor is coupled to a word line.

10. The memory circuit as described in claim 1, characterized in that, The first transistor and the third transistor are of the same size.

11. The memory circuit as described in claim 1, characterized in that, The first transistor is smaller than the third transistor.

12. A method for operating a memory device, characterized in that, Include: A first bit line signal is received via a bit line coupled to a first memory cell, wherein a first source / drain of a first transistor of the first memory cell is coupled to a central node; A second bit line signal is received via a second bit line coupled to a second memory cell, wherein a second source / drain of a second transistor of the second memory cell is coupled to the central node; as well as A first word line signal is received via a first word line coupled to a third transistor shared by the first memory cell and the second memory cell, the third transistor being coupled between the central node and a reference node.

13. The method as described in claim 12, characterized in that, Further includes: A first stacked gate signal is received via a first stacked gate line coupled to the first memory cell; and A second stacked gate signal is received via a second stacked gate line coupled to the second memory cell.

14. The method as described in claim 12, characterized in that, Further includes: A first pull-up gate signal is received via a first pull-up gate line coupled to the first memory cell and the second memory cell.

15. The method as described in claim 12, characterized in that, Further includes: A first switch gate signal is received via a switch gate line coupled to a switch, the first switch gate signal coupling a first transistor unit of the third transistor to a second transistor unit.

16. The method as described in claim 12, characterized in that, Further includes: A second word line signal is received via a second word line coupled to a third transistor shared by the first memory cell and the second memory cell, wherein the first word line is coupled to a first transistor unit of the third transistor and the second word line is coupled to a second transistor unit of the third transistor.

17. A memory device, characterized in that, The memory device includes a first memory unit and a second memory unit, wherein each of the first memory unit and the second memory unit includes: Multiple active structures extend along a first lateral direction, wherein a first portion of the active structures defines a first signal node, wherein a second portion of the active structures defines a second signal node, and wherein a third portion of the active structures defines a first reference node. A plurality of gate-defined structures extend along a second lateral direction perpendicular to the first lateral direction, wherein the gate-defined structures are disposed above the active structures, wherein a first number of the gate-defined structures are coupled to a word line and a second number of the gate-defined structures are coupled to a stacked gate line; and A first conductive structure extends along the first transverse direction, wherein the first conductive structure is disposed above the second portion of the active structures; The first conductive structure of the first memory cell is coupled to the first conductive structure of the second memory cell.

18. The memory device as claimed in claim 17, characterized in that, Each of the first memory unit and the second memory unit further includes: A fuse link extends in the first lateral direction, wherein the fuse link is coupled to a bit line; and A second conductive structure extends in a second direction, wherein the second conductive structure is disposed above the fuse link and the first portion of the active structures.

19. The memory device as claimed in claim 17, characterized in that, The ratio of the first number of gate-defined structures to the second number of gate-defined structures is greater than 1.

20. The memory device as claimed in claim 19, characterized in that, The ratio of the first number of gate-defined structures to the second number of gate-defined structures is greater than 2.

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