Selection of target reference structure and methods for fabricating semiconductor structures based on it

Abstract

In the method for selecting a target reference structure and the method for fabricating a semiconductor structure provided by the present invention, after obtaining the actual feature size of each reference structure, the actual feature size of the reference structure is associated with and compared with a preset feature size to obtain a difference. In this way, the actual feature size of the target reference structure obtained based on the difference will be less different from the preset feature size. Therefore, when adjusting the parameters in the subsequent fabrication of the semiconductor structure based on the target reference structure, the size of the product can be stabilized, the defect rate can be reduced, and the product performance can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for selecting a target reference structure and fabricating a semiconductor structure based thereon. Background Technology

[0002] As people's living standards improve, electronic products are being used more and more widely, and various semiconductor products are commonly used in these products. With the development of technology and the increase in people's needs, the performance requirements for semiconductor products are also getting higher and higher.

[0003] Therefore, in the fabrication of semiconductor structural products, it is necessary to ensure consistent product dimensions to improve product yield and performance. During the fabrication process, especially when performing exposure processes, the parameters of the exposure process are typically adjusted based on a comparison of the dimensions of feedback points, such as the vias for word lines and bit lines in flash memory, with preset dimensions. This ensures dimensional consistency across the entire batch of products.

[0004] Using a mature and stable feedback point as a benchmark for parameter adjustments generally ensures product size consistency. However, since different customers may have different product requirements, some customers may modify the structural dimensions of the feedback point. This will cause deformation of the feedback point's structural dimensions. Continuing to use this feedback point as a benchmark for parameter adjustments will result in significant product size deviations, leading to reduced product performance and yield losses. Summary of the Invention

[0005] The purpose of this invention is to provide a method for selecting a target reference structure and fabricating a semiconductor structure based on it, so as to solve the problems of low product performance and yield loss in the prior art.

[0006] To address the above problems, this invention discloses a method for selecting a target reference structure, comprising:

[0007] At least two semiconductor structures are provided, each of the semiconductor structures including at least two reference structures, the at least two reference structures being fabricated based on the same exposure process and having different preset features, each of the reference structures having a preset feature size;

[0008] Obtain the actual feature size of each of the reference structures, subtract the actual feature size from the preset feature size to obtain the difference value, and select the target reference structure based on the difference value.

[0009] Optionally, the method for selecting the target reference structure based on the difference includes:

[0010] Divide the difference corresponding to each of the reference structures by the preset feature size to obtain the percentage difference;

[0011] The average difference percentage is obtained by averaging the difference percentages corresponding to the reference structures located on different semiconductor structures but having the same preset characteristics.

[0012] Sort the average difference percentages corresponding to the reference structures located on the same semiconductor.

[0013] The benchmark structure corresponding to the smallest percentage of the average difference is selected as the target benchmark structure.

[0014] Optionally, after obtaining the percentage difference, the method further includes taking the absolute value of the percentage difference.

[0015] Optionally, before obtaining the percentage difference, the method further includes: removing the abnormal differences.

[0016] Optionally, the method for removing the abnormal differences includes: processing all the differences using an outlier detection algorithm, and recording and removing the differences that are outside the 5-sigma range as abnormal differences.

[0017] Optionally, the number of semiconductor structures is greater than or equal to 200.

[0018] Optionally, the preset features include: shape features.

[0019] Optionally, the reference structure includes: a connecting hole, a metal wire, and an alignment mark.

[0020] Optionally, the method for obtaining each of the actual feature dimensions includes: measuring the actual feature dimensions of the reference structure using an optical CDSEM device.

[0021] To address the above problems, the present invention also provides a method for preparing a semiconductor structure, the method comprising:

[0022] Provides multiple semiconductor structures to be fabricated with material layers formed thereon;

[0023] The semiconductor structure to be prepared is subjected to an exposure process sequentially, wherein, during the sequential exposure process of the semiconductor structure to be prepared, the parameters of the exposure process are adjusted based on the target reference structure selected according to the target reference structure selection method as described above.

[0024] In this invention, after obtaining the actual feature size of each reference structure, the actual feature size of the reference structure is associated with and compared with the preset feature size to obtain the difference. Thus, the actual feature size of the target reference structure obtained based on the difference will be less different from the preset feature size. Therefore, when adjusting the parameters in the subsequent semiconductor structure fabrication based on the target reference structure, the size of the product can be stabilized, the defect rate can be reduced, and the product performance can be improved. Attached Figure Description

[0025] Figure 1 This is a flowchart of a method for selecting a target reference structure according to an embodiment of the present invention;

[0026] Figure 2 This is another flowchart of the method for selecting the target reference structure in one embodiment of the present invention. Detailed Implementation

[0027] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the selection of the target reference structure and the method for fabricating the semiconductor structure proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0028] Figure 1 This is a flowchart of a method for selecting a target reference structure according to an embodiment of the present invention; Figure 2 This is another flowchart of the method for selecting the target reference structure in one embodiment of the present invention.

[0029] like Figure 1 and Figure 2 As shown in the figure, this embodiment provides a method for selecting a target reference structure, which includes the following steps.

[0030] In step one, at least two semiconductor structures are provided, each of which includes at least two reference structures. The at least two reference structures are fabricated based on the same exposure process and have different preset features. Each reference structure has a preset feature size.

[0031] The reference structure includes: a connecting hole, a metal line, and an alignment mark. The preset features include shape features. For example, the reference structure can be a structure with different shapes located on the same semiconductor structure and fabricated using the same exposure process. The reference structure could be, for example, a circular bit line contact hole and an elliptical word line contact hole located on the same semiconductor structure. Alternatively, the reference structure could be a cross-shaped alignment mark and a triangular alignment mark. The reference structure could also be a cross-shaped metal line or a linear metal line. In other words, the reference structure consists of distinctly different structures on a semiconductor device fabricated using the same exposure process.

[0032] In step S20, the actual feature size of each of the reference structures is obtained, the difference between the actual feature size and the preset feature size is calculated to obtain a difference value, and the target reference structure is selected based on the difference value. In this embodiment, the method for obtaining each of the actual feature sizes includes: measuring the actual feature size of the reference structure using an optical CDSEM device.

[0033] In this embodiment, after obtaining the actual feature size of each reference structure, the actual feature size of the reference structure is associated with and compared with the preset feature size to obtain the difference. Thus, the actual feature size of the target reference structure obtained based on the difference will be less different from the preset feature size. Therefore, when adjusting the parameters in the subsequent semiconductor structure fabrication based on the target reference structure, the size of the product can be stabilized, the defect rate can be reduced, and the product performance can be improved.

[0034] Specifically, refer to Figure 2 As shown, in this embodiment, the method for selecting the target reference structure based on the difference includes the following steps one to four.

[0035] In step one: the difference corresponding to each of the reference structures is divided by the preset feature size to obtain the difference percentage.

[0036] In this embodiment, for example, three semiconductor structures are provided: semiconductor structure A, semiconductor structure B, and semiconductor structure C. Each semiconductor structure has three reference structures, such as the interconnects etched by each semiconductor structure using the same exposure process: VCC, VDD, and shared CT. For example, VCC is circular, and its diameter is used as the feature size; VDD is elliptical, and its longest inner diameter (i.e., the distance between the two points with the longest distance) is used as the feature size; shared CT is square, and the side length of this square is defined as the feature size. The actual feature size corresponding to each reference structure on each semiconductor structure is measured using an optical CDSEM device and the difference is calculated with the preset feature size corresponding to each reference structure. The difference value corresponding to each reference structure is then divided by the preset feature size to obtain the percentage difference. For example, the percentage difference between the semiconductor structure and its corresponding reference structure is summarized in Table 1 below.

[0037] VCC VDD ShareCT Semiconductor structure A 0.5％ 2％ 1％ Semiconductor structure B 0.8％ 1％ 0.7％ Semiconductor structure C 0.2％ 0.6％ 1％

[0038] Table 1

[0039] In step two: the average percentage difference of the reference structures located on different semiconductor structures and having the same preset characteristics is averaged to obtain the average percentage difference.

[0040] Referring to Table 1 above, the average percentage difference across the three semiconductor structures, with VCC as the reference structure, is as follows: 0.5% for VCC, 1.2% for VDD, and 0.9% for shared CT.

[0041] In step three: the average difference percentages corresponding to the reference structures located on the same semiconductor are sorted.

[0042] In step four: the benchmark structure corresponding to the smallest percentage of the average difference is selected as the target benchmark structure.

[0043] Continuing with the three semiconductor structures mentioned above, it is obvious that 0.5% is less than 0.9% and less than 1.2%. That is, the average difference percentage of the structure with VCC as the reference is less than the average difference percentage of the structure with VDD as the reference, which is less than the average difference percentage of the structure with shared CT as the reference. Therefore, the VCC corresponding to the smallest average difference percentage is selected as the reference structure.

[0044] Furthermore, in this embodiment, after obtaining the percentage difference, the method further includes taking the absolute value of the percentage difference. This is to prevent negative percentage differences from affecting the final result.

[0045] Furthermore, before obtaining the percentage difference, the method further includes: removing abnormal differences. The method for removing abnormal differences includes: processing all differences using an outlier detection algorithm, and recording and removing differences outside the 5-sigma range as abnormal differences. In this embodiment, by removing abnormal differences, the influence of abnormal differences on the final calculation result is avoided.

[0046] Furthermore, in this embodiment, three semiconductor structures are used for illustration. In actual production, the more sample data, the more reliable the results. Research by technical personnel has found that when the number of semiconductor structures is greater than or equal to 200, the data reliability is higher and the conclusions are more accurate.

[0047] Furthermore, this embodiment also provides a method for fabricating a semiconductor structure, which includes the following first step and second step.

[0048] In the first step: multiple semiconductor structures to be fabricated are provided, each having a material layer formed on it.

[0049] In this embodiment, the semiconductor structure to be fabricated includes a substrate and a semiconductor material layer formed on the substrate. The substrate may include semiconductor materials, insulating materials, conductive materials, or any combination thereof, and may be a single-layer structure or a multilayer structure. Therefore, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. It may also include layered substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The material layer may be a metallic material layer or a dielectric material layer. In this embodiment, the material of the material layer is not specifically limited and is subject to actual conditions. Furthermore, the methods for forming the material layer include chemical vapor deposition and / or physical vapor deposition.

[0050] In the second step, the semiconductor structure to be prepared is subjected to an exposure process in sequence. During the process of performing the exposure process on the semiconductor structure to be prepared in sequence, the parameters of the exposure process are adjusted based on the target reference structure selected according to the target reference structure selection method described above.

[0051] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0052] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for selecting a target reference structure, characterized in that, include: At least two semiconductor structures are provided, each of the semiconductor structures including at least two reference structures, the at least two reference structures being fabricated based on the same exposure process and having different preset features, each of the reference structures having a preset feature size; Obtain the actual feature size of each of the reference structures, subtract the actual feature size from the preset feature size to obtain the difference value, and select the target reference structure based on the difference value; The method for selecting the target reference structure based on the difference includes: Divide the difference corresponding to each of the reference structures by the preset feature size to obtain the percentage difference; The average difference percentage is obtained by averaging the difference percentages corresponding to the reference structures located on different semiconductor structures but having the same preset characteristics. The average difference percentages corresponding to at least two of the reference structures located on the same semiconductor are sorted. The benchmark structure corresponding to the smallest percentage of the average difference is selected as the target benchmark structure.

2. The target reference structure selection method as described in claim 1, characterized in that, After obtaining the percentage difference, the method further includes taking the absolute value of the percentage difference.

3. The target reference structure selection method as described in claim 1, characterized in that, Before obtaining the percentage difference, the method further includes: removing the abnormal differences.

4. The target reference structure selection method as described in claim 3, characterized in that, The method for removing the abnormal differences includes: processing all the differences using an outlier detection algorithm, and recording the differences located outside the 5-sigma range as abnormal differences and removing them.

5. The target reference structure selection method as described in claim 1, characterized in that, The number of semiconductor structures is greater than or equal to 200.

6. The target reference structure selection method as described in claim 1, characterized in that, The preset features include: shape features.

7. The target reference structure selection method as described in claim 1, characterized in that, The reference structure includes: a connecting hole, a metal wire, and an alignment mark.

8. The target reference structure selection method as described in claim 1, characterized in that, The method for obtaining each of the actual feature dimensions includes: measuring the actual feature dimensions of the reference structure using an optical CDSEM device.

9. A method for fabricating a semiconductor structure, characterized in that: Provides multiple semiconductor structures to be fabricated with material layers formed thereon; The semiconductor structure to be prepared is subjected to an exposure process sequentially, wherein, during the sequential exposure process of the semiconductor structure to be prepared, the parameters of the exposure process are adjusted based on the target reference structure selected according to the target reference structure selection method according to any one of claims 1 to 8.

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