SOI substrate, SOI device and forming method thereof

Abstract

A SOI substrate, SOI device, and method for forming the same. The SOI substrate comprises: a bottom silicon layer; a buried oxide layer located on the bottom silicon layer; a composite core layer located in the buried oxide layer; the top surface of the composite core layer being flush with the top surface of the buried oxide layer; a top silicon layer located on the buried oxide layer and the composite core layer; the top silicon layer having an active region, wherein source / drain doped regions are subsequently formed in the active region; the composite core layer is located below the subsequently formed source / drain doped regions and is used to absorb and conduct charges from the subsequently formed neutral region. The above-described scheme can effectively suppress the floating body effect and improve the performance of the resulting SOI device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an SOI substrate, an SOI device and a method for forming the same. Background Art

[0002] Silicon-on-insulator (SOI) substrates incorporate a buried oxide layer between the top silicon layer and the substrate. SOI substrates offer numerous advantages over conventional bulk silicon substrates, including eliminating latch-up, reducing short-channel effects, and improving radiation resistance.

[0003] Therefore, using SOI substrate to manufacture field effect transistors (MOSFETs) is one of the commonly used technologies in semiconductor manufacturing. MOSFETs manufactured using SOI substrates can be called SOI MOSFETs.

[0004] However, the performance of existing SOI MOSFETs still needs to be improved. Summary of the Invention

[0005] The problem solved by the present invention is to provide an SOI substrate, an SOI device and a method for forming the same, so as to improve the floating body effect and enhance the performance of the formed SOI MOSFET.

[0006] To solve the above problems, the present invention provides an SOI substrate, comprising:

[0007] bottom silicon layer;

[0008] a buried oxide layer on the bottom silicon layer;

[0009] a composite central layer located in the buried oxide layer; a top surface of the composite central layer being flush with a top surface of the buried oxide layer;

[0010] A top silicon layer is located on the buried oxide layer and the composite central layer; the top silicon layer has an active area, in which a source-drain doped area is subsequently formed, and the composite central layer is located below the subsequently formed source-drain doped area, and the composite central layer is used to absorb and lead out charges in the subsequently formed neutral body area.

[0011] Optionally, the material of the composite core layer is RRC material or doped RRC material.

[0012] Optionally, the RRC material includes polysilicon, silicon germanium, silicon nitride, silicon carbide, or carbon-doped silicon.

[0013] Optionally, the doped ions in the doped RRC material include argon, carbon, fluorine, boron fluoride, indium, and nitrogen.

[0014] Optionally, the thickness of the composite core layer is 5 nm to 200 nm.

[0015] Optionally, the material of the bottom silicon layer includes single crystal silicon, single crystal silicon germanium, a III-V group element compound, or single crystal silicon carbide.

[0016] Optionally, the buried oxide layer material is silicon oxide.

[0017] Optionally, the material of the top silicon layer includes single crystal silicon, single crystal silicon germanium, a III-V group element compound, or single crystal silicon carbide.

[0018] Accordingly, an embodiment of the present invention further provides a method for forming an SOI substrate, which is used to form any of the above-mentioned SOI substrates, comprising:

[0019] providing a first substrate;

[0020] oxidizing the surface of the first substrate to form a buried oxide layer and a bottom silicon layer located below the buried oxide layer;

[0021] forming a composite core layer in the buried oxide layer; wherein a top surface of the composite core layer is flush with a top surface of the buried oxide layer;

[0022] A top silicon layer is formed covering the buried oxide layer and the composite central layer; the top silicon layer has an active area, in which a source-drain doped area is subsequently formed, and the composite central layer is located below the subsequently formed source-drain doped area, and the composite central layer is used to absorb and conduct charges in the subsequently formed neutral area.

[0023] Optionally, the step of forming the composite core layer includes:

[0024] forming a buried trench in the buried oxide layer;

[0025] forming a composite core material layer covering the buried oxide layer and filling the buried trench;

[0026] The composite core material layer is planarized so that a top surface of the remaining composite core material layer is flush with a top surface of the buried oxide layer, thereby forming the composite core layer.

[0027] Optionally, after planarizing the composite core material layer, the method further includes:

[0028] A first ion implantation process is performed on the composite core layer.

[0029] Optionally, the parameters of the first ion implantation process include: the implanted ions are at least one of argon ions, carbon ions, fluorine ions, boron fluoride ions, indium ions, and nitrogen ions, the implantation energy is, and the implantation dose is.

[0030] Optionally, the step of forming the top silicon layer comprises:

[0031] providing a second substrate;

[0032] bonding the second substrate to the buried oxide layer and the composite core layer;

[0033] After bonding, thinning the second substrate;

[0034] A planarization process is performed on the thinned second substrate to make the top surface of the thinned second substrate flat, thereby forming the top silicon layer.

[0035] Optionally, the process of thinning the top silicon layer is at least one of etching back and grinding.

[0036] Optionally, the step of forming the top silicon layer comprises:

[0037] providing a second substrate;

[0038] performing a second ion implantation process on a top portion of the second substrate to form an ion implantation layer located on the top portion of the second substrate;

[0039] After forming the ion implantation layer, bonding the second substrate to the substrate;

[0040] After bonding, performing an annealing process on the second substrate;

[0041] After performing the annealing process, stripping the ion implantation layer;

[0042] After the ion implantation layer is stripped off, a planarization process is performed on the remaining second substrate to make the top surface of the remaining second substrate flat, thereby forming the top silicon layer.

[0043] Optionally, the ions implanted in the second ion implantation process are hydrogen ions.

[0044] Accordingly, an embodiment of the present invention further provides an SOI device, comprising:

[0045] The SOI substrate as described in any one of the above items.

[0046] Optionally, the SOI device further includes:

[0047] a gate structure located on the top silicon layer; the gate structure being located on the active area;

[0048] source-drain doped regions within the active region on both sides of the gate structure;

[0049] A metal silicide is located on the top of the gate structure and the surface of the source and drain doped regions.

[0050] Accordingly, an embodiment of the present invention further provides a method for forming an SOI device, the method comprising:

[0051] The SOI substrate is formed by using any of the above methods for forming an SOI substrate.

[0052] Accordingly, the method for forming the SOI device further includes:

[0053] forming a gate structure on the active region in the top silicon layer;

[0054] forming source and drain doped regions in the active regions located on both sides of the gate structure;

[0055] Metal silicide is formed on the surface of the gate structure and the source-drain doped regions.

[0056] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0057] The solution of the embodiment of the present invention is to provide a recombination center layer in the buried oxide layer within the SIO substrate. The recombination center layer is located below the source-drain doped region subsequently formed in the top silicon layer of the SIO substrate. The recombination center layer can absorb and conduct the accumulated charge in the neutral body region subsequently formed in the top silicon layer, thereby effectively suppressing the floating body effect and improving the performance of the formed SOI device. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 FIG1 is a schematic diagram of an SOI device;

[0059] Figures 2 to 5 A schematic structural diagram of a method for forming an SOI substrate according to an embodiment of the present invention;

[0060] Figures 6 to 12 The figure shows a schematic diagram of an intermediate structure formed by each step of a method for forming an SOI device in an embodiment of the present invention. DETAILED DESCRIPTION

[0061] As can be seen from the background technology, the performance of existing SOI substrates still needs to be improved.

[0062] Now we analyze it in combination with an SOI device.

[0063] refer to Figure 1The SOI device includes an SOI substrate (not shown) and a gate structure 12 located on the SOI substrate.

[0064] The SOI substrate includes a bottom silicon layer 111 , a buried oxide layer (BOX) 112 located on the bottom silicon layer 111 , and a top silicon layer 113 located on the buried oxide layer 112 .

[0065] In the above-mentioned SOI device, when the thickness of the top silicon layer 113 is greater than the width of the maximum depletion layer, due to the isolation effect of the buried oxide layer 112 in the structure, after the device is turned on, a part of the top silicon layer 113 that has not been depleted will be in an electrically floating state, forming a floating structure.

[0066] This floating body structure can significantly affect device characteristics, known as the floating body effect. This floating body effect can cause problems such as kink effects, reduced drain breakdown voltage, and abnormal subthreshold slopes, thus impacting device performance.

[0067] To solve the above problems, an embodiment of the present invention provides an SOI substrate, which includes: a bottom silicon layer; a buried oxide layer located on the bottom silicon layer; a composite center layer located in the buried oxide layer; the top surface of the composite center layer is flush with the top surface of the buried oxide layer; a top silicon layer located on the buried oxide layer and the composite center layer; the top silicon layer has an active area, in which a source-drain doped area is subsequently formed, the composite center layer is located below the subsequently formed source-drain doped area, and the composite center layer is used to adsorb and conduct charges in the subsequently formed neutral body area.

[0068] The solution in the embodiment of the present invention is to set a composite center layer in the buried oxide layer in the SOI substrate. The composite center layer is located below the source and drain doped regions subsequently formed in the top silicon layer of the SOI substrate. The composite center layer can absorb and conduct the charges accumulated in the neutral body region subsequently formed in the top silicon layer, thereby effectively suppressing the floating body effect and improving the performance of the formed SOI device.

[0069] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0070] Figure 5 A schematic structural diagram of an SOI substrate in an embodiment of the present invention is shown.

[0071] See also Figure 5The SOI substrate includes: a bottom silicon layer 100; a buried oxide layer 110 located on the bottom silicon layer 100; a recombination center layer 115 located in the buried oxide layer 110; the top surface of the recombination center layer 115 is flush with the top surface of the buried oxide layer 110; a top silicon layer 120 located on the buried oxide layer 110 and the recombination center layer 115; the top silicon layer 120 has an active area (not marked), in which a source-drain doped area is subsequently formed, the recombination center layer 115 is located below the source-drain doped area formed subsequently, and the recombination center layer 115 is used to absorb and conduct charges accumulated in a neutral area formed subsequently.

[0072] In this embodiment, the material of the bottom silicon layer 100 is single crystal silicon. In other embodiments, the material of the bottom silicon layer 100 can also be single crystal germanium or single crystal germanium silicon, III-V group element compounds, single crystal silicon carbide and other materials.

[0073] In this embodiment, the buried oxide layer 110 is made of silicon oxide. In other embodiments, the buried oxide layer may also be other dielectric layers known to those skilled in the art.

[0074] The thickness of the buried oxide layer 110 can be set according to the performance of the formed SOI device. In this embodiment, the thickness of the buried oxide layer 110 is 200 nm to 5000 nm.

[0075] The recombination center layer 115 is used to absorb and conduct charges accumulated in the neutral body region subsequently formed in the top silicon layer to suppress the floating body effect.

[0076] In this embodiment, the material of the recombination center layer 115 is a rich recombination center (RRC) material. The RRC material is a material with a smaller grain size and a shorter recombination time constant, such as polysilicon, silicon germanium, silicon nitride, silicon carbide, carbon-doped silicon, etc. Due to the smaller grain size and shorter recombination time constant, the recombination center layer 115 can quickly capture the charges accumulated in the neutral body region formed in the SOI substrate to quickly reduce the floating body potential, thereby suppressing the floating body effect more quickly and effectively. In the implementation of the present invention, the recombination time constant of the RRC material is <10 -10 s.

[0077] In other embodiments, the composite core layer may be made of a doped RRC material, wherein the doping ions in the RRC material include at least one of argon, carbon, fluorine, boron fluoride, indium, and nitrogen.

[0078] The presence of doped ions in the doped RRC material can generate more defect recombination centers to further improve the capture efficiency of the accumulated charges in the subsequently formed neutral body region, thereby more effectively suppressing the floating body effect.

[0079] The thickness of the recombination core layer 115 can be set based on the SOI device being formed. Specifically, the thickness of the recombination core layer 115 can be determined based on the required absorption of accumulated charges in the neutral body region within the active region subsequently formed in the top silicon layer. In this embodiment, the thickness of the recombination core layer is 5 nm to 200 nm.

[0080] In this embodiment, the material of the top silicon layer 120 is single crystal silicon. In other embodiments, the material of the top silicon layer can also be single crystal germanium or single crystal germanium silicon, III-V group element compounds, single crystal silicon carbide and other materials.

[0081] In this example, the SOI substrate further includes an isolation structure.

[0082] The isolation structure is used to isolate the subsequently formed SOI device from other devices.

[0083] In this embodiment, the thickness of the isolation structure is greater than the thickness of the top silicon layer 120. In other embodiments, the thickness of the isolation structure may also be equal to the thickness of the top silicon layer.

[0084] In this embodiment, the isolation structure is a shallow trench isolation (STI) structure.

[0085] In this embodiment, the material of the isolation structure is silicon oxide.

[0086] Correspondingly, an embodiment of the present invention also provides a method for forming an SOI substrate.

[0087] Figures 2 to 5 It is a schematic diagram of the structure formed by each step in an embodiment of the method for forming an SOI substrate of the present invention.

[0088] See also Figure 2 , providing a first substrate 10.

[0089] The first substrate 10 is used for subsequently forming a bottom silicon layer and a buried oxide layer located on the bottom silicon layer.

[0090] In this embodiment, the material of the first substrate 10 is single crystal silicon. In other embodiments, the material of the first substrate 10 can also be single crystal germanium or single crystal germanium silicon, III-V group element compounds, single crystal silicon carbide and other materials.

[0091] See also Figure 3, the top surface of the first substrate 10 is oxidized to form a buried oxide layer 110 and a bottom silicon layer 100 located below the buried oxide layer 110 .

[0092] The buried oxide layer 110 is used to isolate the bottom silicon layer 100 from a subsequently formed top silicon layer.

[0093] In this embodiment, the buried oxide layer 110 is made of silicon oxide.

[0094] In this embodiment, the buried oxide layer 110 is formed by thermally oxidizing the top surface of the first substrate 10 at room temperature.

[0095] The thickness of the buried oxide layer 110 can be determined according to the type of the subsequently formed SOI device. For example, when the subsequently formed SOI device is an RFSOI MOSFET device, the thickness of the buried oxide layer is 200 nm to 5000 nm.

[0096] See also Figure 4 , a composite core layer 115 is formed in the buried oxide layer 110 .

[0097] The recombination center layer 115 is located below the source-drain doped source region subsequently formed in the top silicon layer. Specifically, the recombination center layer 115 is located below the source-drain doped region subsequently formed in the active region to absorb charges accumulated in the subsequently formed neutral body region and conduct them through the subsequently formed source region to suppress the floating body effect.

[0098] The recombination core layer 115 is located below the source and drain doping regions that will subsequently form the source region of the SOI device. This layer absorbs the charge accumulated in the neutral body formed during operation of the subsequently formed SOI device and conducts it through the source region. Therefore, the recombination core layer 115 can be provided only below the source and drain doping regions corresponding to the source region of the subsequently formed SOI device.

[0099] Those skilled in the art will appreciate that, for the convenience of subsequent process operations, that is, to avoid restrictions on whether the source-drain doped regions formed in the subsequent process form source regions or drain regions, a corresponding composite center layer may be provided under each of the two source-drain doped regions formed, so that in the subsequent process, any one of the source-drain doped regions may be selected as the source region, and the other source-drain doped region may be selected as the drain region.

[0100] The steps of forming the composite center layer 102 include: forming a buried trench in the buried oxide layer 110; forming a composite center material layer covering the buried oxide layer 110 and filling the buried trench; and flattening the composite center material layer so that the top surface of the remaining composite center material layer is flush with the top surface of the buried oxide layer to form the composite center layer 115.

[0101] In this embodiment, the buried trench is formed by dry etching. In other embodiments, the buried trench may be formed by wet etching, etc. Those skilled in the art may select the process according to actual needs, and this is not limited here.

[0102] In this embodiment, the process for planarizing the composite core material layer is a chemical mechanical polishing process. In other embodiments, the process for planarizing the composite core material layer may also be an etch-back process.

[0103] The material of the recombination center layer 115 is a rich recombination center (RRC) material. The RRC material is a material with a small grain size and a short recombination time constant, such as polycrystalline silicon, silicon germanium, silicon nitride, silicon carbide, or carbon-doped silicon. Due to its small grain size and short recombination time constant, the recombination center layer can quickly capture the charge accumulated in the subsequently formed neutral body region, rapidly reducing the potential of the neutral body region, thereby more quickly and effectively suppressing the floating body effect.

[0104] In this embodiment, after planarizing the composite core material layer, the method further includes performing a first ion implantation process on the composite core layer.

[0105] Performing the first ion implantation process on the recombination center layer can generate more defective recombination centers in the recombination center layer, thereby further improving the capture efficiency of the charges accumulated in the neutral body, thereby more effectively suppressing the floating body effect.

[0106] The first ion implantation process can be set according to actual needs. In this embodiment, the process parameters of the first ion implantation process include: the implanted ions include at least one of argon ions, carbon ions, fluorine ions, boron fluoride ions, indium ions, and nitrogen ions; the implantation energy is 5K to 500K, depending on the thickness of the composite core layer and the type of implanted ions used; the implantation dose is 10 13 / cm 2 ~10 15 / cm 2 .

[0107] The size of the recombination core layer 115 can be determined based on the charge absorption requirements of the neutral bodies subsequently formed in the SOI device. Specifically, the thickness of the recombination core layer 115 is determined by the thickness of the buried oxide layer 110, i.e., the thickness of the recombination core layer 115 is less than the thickness of the buried oxide layer 110. The width of the recombination core layer 115 is determined by the size of the body contact region of the source and drain doped regions subsequently formed in the SOI device. In this embodiment, the thickness of the recombination core layer 115 is 5 nm to 200 nm.

[0108] See also Figure 5 , forming a top silicon layer 120 covering the buried oxide layer 110 and the composite core layer 115 .

[0109] The top silicon layer 120 provides a process platform for subsequent formation of SOI devices.

[0110] In this embodiment, the material of the top silicon layer 120 is single crystal silicon. In other embodiments, the material of the top silicon layer can also be single crystal germanium or single crystal germanium silicon, III-V group element compounds, single crystal silicon carbide and other materials.

[0111] In this embodiment, the steps of forming the top silicon layer 120 include: providing a second substrate; bonding the second substrate to the buried oxide layer 110 and the composite center layer 115; after bonding, thinning the second substrate; performing a planarization process on the thinned second substrate to make the top surface of the thinned second substrate flat, thereby forming the top silicon layer 120.

[0112] In this embodiment, the second substrate is formed by an epitaxial growth process.

[0113] In this embodiment, before bonding the second substrate to the top surfaces of the buried oxide layer 110 and the recombination core layer 115, the top surfaces of the buried oxide layer 110 and the recombination core layer 115, as well as the bottom surface of the second substrate, are cleaned and activated. Subsequently, N+ plasma can be used to activate the surfaces to be bonded to increase dangling bonds and activate the surface, further enhancing the bonding strength.

[0114] In this embodiment, the process for thinning the second substrate is a grinding process. In other embodiments, the process for thinning the top silicon layer may also be an etch-back process.

[0115] In other embodiments, the steps of forming the top silicon layer 120 may include: providing a second substrate; performing a second ion implantation process on the top of the second substrate to form an ion implantation layer; after forming the ion implantation layer, bonding the second substrate to the buried oxide layer 110 and the composite center layer 115; after bonding, performing an annealing process on the second substrate to peel off the ion implantation layer from the top of the second substrate; after peeling off the ion implantation layer, performing a planarization process on the remaining second substrate to make the top surface of the remaining second substrate flush to form the top silicon layer 120.

[0116] In this embodiment, the ions implanted in the second ion implantation process are hydrogen ions.

[0117] The depth of the second ion implantation process is determined by the thickness of the second substrate and the thickness of the subsequently formed top silicon layer. The thickness of the second substrate and the thickness of the top silicon layer can be determined according to the specific conditions of the device and are not limited here.

[0118] In this embodiment, after the ion implantation layer is stripped, a high-temperature annealing operation may be performed on the bonding contact surface to enhance the bonding strength.

[0119] In this embodiment, the planarization process performed on the top silicon layer 120 is a chemical mechanical polishing process, so that the top surface of the top silicon layer 120 is flush after the ion implantation layer is stripped off.

[0120] Accordingly, an embodiment of the present invention further provides an SOI device. The SOI device includes the SOI substrate. The SOI substrate is described in the above section and will not be described in detail here.

[0121] An SOI device according to an embodiment of the present invention will be described in detail below.

[0122] See Figure 12 , an SOI device in an embodiment of the present invention includes:

[0123] An SOI substrate 10 includes: a bottom silicon layer 100; a buried oxide layer 110 located on the bottom silicon layer 100; a composite center layer 115 located in the buried oxide layer 110; a top surface of the composite center layer 115 is flush with the top surface of the buried oxide layer 110; a top silicon layer 120 located on the buried oxide layer 110 and the composite center layer 115; the top silicon layer 120 has an active area (not marked), in which a source-drain doped area is subsequently formed, the composite center layer 115 is located below the subsequently formed source-drain doped area, and the composite center layer 115 is used to absorb and conduct charges in a subsequently formed neutral body area; a gate structure (not marked) located on the active area in the top silicon layer 120; source-drain doped areas 150 located in the active area on both sides of the gate structure; and a metal silicide 150 located on the top of the gate structure and on the surface of the source-drain doped areas 150.

[0124] In this embodiment, the gate structure includes a gate dielectric layer 131 ′ and a gate 132 located on the gate dielectric layer 131 ′.

[0125] In this embodiment, the gate dielectric layer 131' is made of silicon oxide, and the gate 132 is made of polysilicon. In other embodiments, the gate structure may also be a metal gate structure.

[0126] In this embodiment, the doping ions in the source / drain doping regions 150 are determined by the SOI device being formed. Specifically, when the SOI device being formed is an NMOS device, the doping ions in the source / drain doping regions 150 are N-type ions; when the SOI device being formed is a PMOS device, the doping ions in the source / drain doping regions 150 are P-type ions.

[0127] In this embodiment, the SOI device further includes an isolation structure 125 located in the top substrate layer 120 .

[0128] The isolation structure 125 is used to isolate the subsequently formed SOI device from other devices.

[0129] In this embodiment, the thickness of the isolation structure 125 is greater than the thickness of the top silicon layer 120. In other embodiments, the thickness of the isolation structure may also be equal to the thickness of the top silicon layer.

[0130] In this embodiment, the isolation structure 125 is a shallow trench isolation structure.

[0131] In this embodiment, the isolation structure 125 is made of silicon oxide.

[0132] In this embodiment, the SOI device further includes a first spacer layer 141 located on the sidewall of the gate structure.

[0133] The first spacer layer 141 and the gate structure are used together as a mask for a subsequent lightly doped implantation process, and can protect the sidewalls of the gate structure during the lightly doped implantation process.

[0134] In this embodiment, the material of the first spacer layer 141 is silicon oxide. In other embodiments, the material of the first spacer layer can also be silicon nitride or the like.

[0135] In this embodiment, the SOI device further includes lightly doped regions (not labeled) located on both sides of the gate structure.

[0136] The lightly doped region is used to prevent the short channel effect.

[0137] The type of dopant ions implanted into the lightly doped region is determined by the electrical properties of the semiconductor device to be formed. Specifically, when the semiconductor device to be formed is an NMOS device, the implanted impurity ions are one or a combination of phosphorus, arsenic, antimony, and bismuth; when the semiconductor device to be formed is a PMOS device, the implanted impurity ions are boron.

[0138] In this embodiment, the SOI device further includes halo regions (not shown) located on both sides of the gate structure.

[0139] In this embodiment, the SOI device further includes spacer layers 140 located on both sides of the gate structure.

[0140] The spacer layer 140 is used as a mask together with the gate structure when the source and drain doping regions are subsequently formed, and can protect the sidewalls of the gate structure during the source and drain implantation process.

[0141] In this embodiment, the spacer layer 140 includes a first spacer layer 141 and a second spacer layer 142 located on the sidewalls of the first spacer layer 141. In other words, the spacer layer 140 is formed by forming the second spacer layer 142 on the sidewalls of the first spacer layer 141.

[0142] In this embodiment, the material of the second spacer layer 142 is the same as the material of the first spacer layer 141, that is, silicon oxide. In other embodiments, the material of the second spacer layer can also be silicon nitride or the like.

[0143] Accordingly, an embodiment of the present invention further provides a method for forming an SOI device.

[0144] Figures 6 to 12 The figure shows a schematic diagram of an intermediate structure formed by each step of a method for forming an SOI device in an embodiment of the present invention.

[0145] Please continue to see Figure 6 , providing an SOI substrate (not shown).

[0146] The SOI substrate provides a process platform for the subsequently formed device structure.

[0147] The SOI substrate includes: a bottom silicon layer 100; a buried oxide layer 110 located on the bottom silicon layer 100; a composite center layer 115 located in the buried oxide layer 110; the top surface of the composite center layer 115 is flush with the top surface of the buried oxide layer 110; a top silicon layer 120 located on the buried oxide layer 110 and the composite center layer 115; the top silicon layer 120 has an active area (not marked), in which a source-drain doped area is subsequently formed, the composite center layer 115 is located below the source-drain doped area, and the composite center layer is used to absorb and conduct the charges accumulated in the neutral body area formed when the SOI device is in an operating state.

[0148] The SOI substrate is described in detail in the previous section and will not be described again here.

[0149] Please continue to see Figure 6 In this embodiment, after the SOI substrate is formed, an isolation structure 125 is formed in the SOI substrate.

[0150] In this embodiment, the thickness of the isolation structure 125 is greater than the thickness of the top silicon layer. In other embodiments, the thickness of the isolation structure 125 may also be equal to the thickness of the top silicon layer.

[0151] In this embodiment, the isolation structure 125 is a shallow trench isolation (STI) structure.

[0152] In this embodiment, the isolation structure 125 is made of silicon oxide.

[0153] The steps of forming the isolation structure 125 include: forming a patterned hard mask layer on the SOI substrate 10; etching the SOI substrate 10 using the patterned hard mask layer as a mask to form an isolation trench; forming an isolation material layer covering the patterned hard mask layer and filling the isolation trench; the top surface of the isolation material layer is flush with the top surface of the patterned hard mask layer; and performing a planarization process on the patterned hard mask layer and the isolation material layer until the top surface of the top silicon layer is exposed to form the isolation structure 125.

[0154] It should be pointed out that when the thickness of the isolation structure 125 is greater than the thickness of the top silicon layer 120, the bottom of the isolation trench formed exposes the material of the buried oxide layer; when the thickness of the isolation structure 125 is equal to the thickness of the top silicon layer 120, the bottom of the isolation trench formed exposes the top surface of the buried oxide layer.

[0155] In this embodiment, before forming a patterned hard mask layer on the SOI substrate 10, it also includes: forming a buffer layer (not shown) on the SOI substrate 10; and performing the planarization process on the patterned hard mask layer and the isolation material layer, and also performing the planarization process on the buffer layer.

[0156] The buffer layer is used to play a buffering role between the SIO substrate 10 and the patterned hard mask layer, and can enhance the adhesion between the SIO substrate 10 and the patterned hard mask layer, thereby avoiding the problem of misalignment when the hard mask layer is directly formed on the SIO substrate 10.

[0157] In this embodiment, the material of the buffer layer is silicon oxide. In other embodiments, the material of the buffer layer may also be silicon nitride or the like.

[0158] In this embodiment, the material of the patterned hard mask layer is silicon nitride (SiN).

[0159] In this embodiment, the planarization process performed on the patterned hard mask layer and the isolation material layer is a chemical mechanical polishing process.

[0160] See also Figure 7 , a gate structure is formed on the active area in the top silicon layer 120.

[0161] In this embodiment, the gate structure includes a gate dielectric layer 131' and a gate 132 (eg, Figure 12 shown).

[0162] In this embodiment, the gate dielectric layer 131' is made of silicon oxide, and the gate 132 is made of polysilicon. In other embodiments, the gate structure may also be a metal gate structure.

[0163] The steps of forming the gate structure include: forming a gate dielectric material layer 131 on the top silicon layer; forming an interlayer dielectric layer (not shown) on the gate dielectric material layer 131; etching the interlayer dielectric layer to form a gate trench (not shown); forming a gate 132 filling the gate trench; after forming the gate 132, removing the interlayer dielectric layer; then, etching the gate dielectric material layer under the gate to form a gate dielectric layer 131' located under the gate 132, and forming the gate structure.

[0164] The gate dielectric layer may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0165] The interlayer dielectric layer may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0166] In this embodiment, the material of the interlayer dielectric layer is silicon oxide.

[0167] The gate trench is formed by a dry etching process or a wet etching process.

[0168] The step of forming the gate includes: forming a gate material layer (not shown) covering the interlayer dielectric layer and filling the gate trench; and planarizing the gate material layer until the top surface of the top silicon layer is exposed to form the gate.

[0169] In this embodiment, the process for planarizing the gate material layer is a chemical mechanical polishing process.

[0170] In this embodiment, after forming the gate, the gate dielectric material layer 131 is not etched to form the gate dielectric layer 131'. Instead, after forming the source and drain doped regions on both sides of the gate 132, the gate dielectric material layer 131 is etched to form the gate dielectric layer 131' below the gate 132. In this way, in subsequent manufacturing processes, the gate dielectric material layer 131 can protect the underlying structures, thereby further improving device performance.

[0171] See also Figure 8 In this embodiment, after forming the gate 132 , the step further includes forming a first spacer layer 141 on the top silicon layer to cover the sidewall of the gate 132 .

[0172] The top silicon layer below the first spacer 141 is used to subsequently form a lightly doped region. Therefore, the thickness of the first spacer 141 affects the distance between the subsequently formed lightly doped region and the channel region, as well as the width of the lightly doped region. In this embodiment, the thickness of the first spacer is 5 nm to 20 nm.

[0173] The first spacer layer 141 is formed by chemical vapor deposition, physical vapor deposition, atomic layer vapor deposition, or the like.

[0174] In this embodiment, the material of the first spacer layer 141 is silicon oxide.

[0175] See also Figure 9 In this embodiment, after forming the first sidewall layer 141, the process also includes performing a lightly doped drain implantation process 135 on the top silicon layer 120 using the gate 132 and the first sidewall layer 141 as a mask to form lightly doped regions (not shown) in the active regions on both sides of the gate structure.

[0176] The type of ions implanted during the lightly doped drain implantation (LDD) process is determined based on the electrical properties of the semiconductor device to be formed. Specifically, when the semiconductor device to be formed is an NMOS device, the impurity ions implanted during the LDD process are one or a combination of phosphorus, arsenic, antimony, and bismuth; when the semiconductor device to be formed is a PMOS device, the impurity ions implanted are at least one of boron and indium.

[0177] For example, when the semiconductor device formed is a PMOS transistor, the ions implanted in the lightly doped ion implantation process are at least one of boron ions and indium ions, and the ion doping concentration range can be 1E14atom / cm 2 ~1E16atom / cm 2 The ion injection energy range can be 100eV to 5keV. By controlling the doping concentration and ion injection energy, the parasitic resistance in the lightly doped region is reduced, and doping segregation occurs in the lightly doped region during the subsequent annealing process, extending the lightly doped region to the edges of the channel region. Even if the impurity ions injected by the lightly doped drain injection process are located close to the edge of the channel region, an impurity concentration gradient is provided for the source and drain doped regions, reducing the electric field between the junction and the channel, separating the maximum electric field position in the junction from the maximum current path in the channel, and thus preventing the generation of hot carriers.

[0178] In this embodiment, after performing the lightly doped drain injection, the step of performing a halo injection on the top silicon layer using the gate structure and the first sidewall layer 141 as a mask is also included to form a halo area (not marked) in the active area on both sides of the gate structure.

[0179] See also Figure 10 After the lightly doped region is formed, a second spacer layer 142 is formed to cover the sidewall of the first spacer layer 141 . The first spacer layer 141 and the second spacer layer 142 constitute a spacer layer 140 .

[0180] The first spacer layer 141 and the second spacer layer 142 constitute a spacer layer 140 . The spacer layer 140 and the gate 132 are used as masks for a subsequent source / drain implantation process.

[0181] The second spacer layer 142 is formed by chemical vapor deposition, physical vapor deposition, atomic layer vapor deposition, or the like.

[0182] In this embodiment, the material of the second spacer layer 142 is silicon oxide.

[0183] See also Figure 11 A source-drain implantation process is performed on the active area using the gate 132 and the spacer layer 140 as masks to form source-drain doped regions 150 in the active area on both sides of the gate structure.

[0184] The source-drain doped region 150 is used to subsequently form a source region or a drain region of an SOI device.

[0185] The dopant ions implanted during the source / drain implantation process are determined by the type of semiconductor device being formed. Specifically, when the semiconductor device being formed is an N-type device, the ions implanted during the source / drain implantation process are N-type ions; when the semiconductor device being formed is a P-type device, the ions implanted during the source / drain implantation process are P-type ions.

[0186] The process parameters of the source-drain implantation process are determined according to actual process requirements and performance requirements of the formed semiconductor device.

[0187] In some specific embodiments, the parameters of the source-drain implantation process include: the implanted ions are one or more of P ions, As ions, and Sb ions, the implantation energy is 10 KeV to 20 KeV, and the implantation dose is 7E12 atoms per square centimeter to 1.2E13 atoms per square centimeter.

[0188] See also Figure 12 , performing a metal silicide process on the top surfaces of the gate 132 and the source / drain doped region 150 , forming a metal silicide 160 on the top of the gate 132 and in the source / drain doped region 150 .

[0189] The steps of forming the metal silicide 160 include: forming a metal layer (not marked) on the top surface of the gate 132 and the source-drain doped region 150; after forming the metal layer, performing an annealing treatment to allow the metal layer to react with the material on the surface of the gate structure and the source-drain doped region 150 to form the metal silicide layer 160.

[0190] The material of the metal layer is Ti, Ni or Co.

[0191] In the solution of the embodiment of the present invention, a recombination center layer is provided in the buried oxide layer within the SIO substrate. The recombination center layer is located below the source-drain doped region subsequently formed in the top silicon layer of the SIO substrate. The recombination center layer can absorb and conduct the accumulated charge in the subsequently formed neutral body region, thereby effectively suppressing the floating body effect and improving the performance of the formed SOI device.

[0192] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. An SOI substrate, characterized in that: include: bottom silicon layer; a buried oxide layer on the bottom silicon layer; a composite core layer located in the buried oxide layer; The top surface of the composite center layer is flush with the top surface of the buried oxide layer, and the thickness of the composite center layer is less than the thickness of the buried oxide layer; A top silicon layer is located on the buried oxide layer and the composite central layer; the top silicon layer has an active area, in which a source-drain doped area is subsequently formed, and the composite central layer is located below the subsequently formed source-drain doped area, and the composite central layer is used to absorb charges in the subsequently formed neutral body area and conduct them through the source area.

2. The SOI substrate according to claim 1, characterized in that The material of the composite core layer is RRC material or doped RRC material.

3. The SOI substrate according to claim 2, characterized in that The RRC material includes polysilicon, silicon germanium, silicon nitride, silicon carbide, and carbon-doped silicon.

4. The SOI substrate according to claim 2, wherein: The doped ions in the doped RRC material include argon, carbon, fluorine, boron fluoride, indium, and nitrogen.

5. The SOI substrate according to claim 1, wherein: The thickness of the composite core layer is 5nm to 50nm.

6. The SOI substrate according to claim 1, characterized in that The material of the bottom silicon layer includes single crystal silicon, single crystal silicon germanium, III-V group element compounds, and single crystal silicon carbide.

7. The SOI substrate according to claim 1, wherein: The buried oxide layer material is silicon oxide.

8. The SOI substrate according to claim 1, wherein: The material of the top silicon layer includes single crystal silicon, single crystal silicon germanium, III-V group element compounds, and single crystal silicon carbide.

9. A method for forming an SOI substrate, characterized in that: include: providing a first substrate; oxidizing the surface of the first substrate to form a buried oxide layer and a bottom silicon layer located below the buried oxide layer; forming a composite central layer in the buried oxide layer; wherein a top surface of the composite central layer is flush with a top surface of the buried oxide layer, and a thickness of the composite central layer is less than a thickness of the buried oxide layer; A top silicon layer is formed covering the buried oxide layer and the composite center layer; the top silicon layer has an active area, in which a source-drain doped area is subsequently formed, and the composite center layer is located below the subsequently formed source-drain doped area, and the composite center layer is used to absorb charges in the subsequently formed neutral body area and conduct them through the source area.

10. The method for forming an SOI substrate according to claim 9, wherein: The steps of forming the composite core layer include: forming a buried trench in the buried oxide layer; forming a composite core material layer covering the buried oxide layer and filling the buried trench; The composite core material layer is planarized so that a top surface of the remaining composite core material layer is flush with a top surface of the buried oxide layer, thereby forming the composite core layer.

11. The method for forming an SOI substrate according to claim 10, wherein: After planarizing the composite core material layer, the method further includes: A first ion implantation process is performed on the composite core layer.

12. The method for forming an SOI substrate according to claim 11, wherein: The parameters of the first ion implantation process include: the implanted ions are at least one of argon ions, carbon ions, fluorine ions, boron fluoride ions, indium ions, and nitrogen ions; the implantation energy is 5K to 500K; the implantation dose is 10 13 / cm 2 ~10 15 / cm 2 .

13. The method for forming an SOI substrate according to claim 9, wherein: The steps for forming the top silicon layer include: providing a second substrate; bonding the second substrate to the buried oxide layer and the composite core layer; After bonding, thinning the second substrate; A planarization process is performed on the thinned second substrate to make the top surface of the thinned second substrate flat, thereby forming the top silicon layer.

14. The method for forming an SOI substrate according to claim 13, wherein: The process of thinning the top silicon layer is at least one of etching back and grinding.

15. The method for forming an SOI substrate according to claim 9, wherein: The steps of forming the top silicon layer include: providing a second substrate; performing a second ion implantation process on a top portion of the second substrate to form an ion implantation layer located on the top portion of the second substrate; After forming the ion implantation layer, bonding the second substrate to the substrate; After bonding, performing an annealing process on the second substrate; After performing the annealing process, stripping the ion implantation layer; After the ion implantation layer is stripped off, a planarization process is performed on the remaining second substrate to make the top surface of the remaining second substrate flat, thereby forming the top silicon layer.

16. The method for forming an SOI substrate according to claim 15, wherein: The ions implanted in the second ion implantation process are hydrogen ions.

17. An SOI device, characterized in that: include: The SOI substrate according to any one of claims 1 to 8.

18. The SOI device according to claim 17, wherein: Also includes: a gate structure located on the top silicon layer; the gate structure being located on the active area; source-drain doped regions within the active region on both sides of the gate structure; A metal silicide is located on the top of the gate structure and the surface of the source and drain doped regions.

19. A method for forming an SOI device, characterized in that: include: An SOI substrate is formed by using the method for forming an SOI substrate according to any one of claims 9 to 16.

20. The method for forming an SOI device according to claim 19, wherein: Also includes: forming a gate structure on the active region in the top silicon layer; forming source and drain doped regions in the active regions located on both sides of the gate structure; Metal silicide is formed on the top of the gate structure and the surface of the source and drain doped regions.

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