A planar power device, a manufacturing method and a chip

Abstract

This application belongs to the field of semiconductor technology and provides a planar power device, its fabrication method, and a chip. The planar power device includes: a semiconductor substrate, an N-type well region, a P-type well region, a gate oxide layer, a gate metal layer, a source region, a P-type base region, an isolation region, and a drain region. By setting the N-type well region to an "L"-shaped structure and the P-type well region to a "U"-shaped structure, the source region and the P-type base region are both located within the groove of the P-type well region, while the isolation region and the drain region are located on the horizontal portion of the N-type well region. This reduces the area occupied by the planar power device, making it more miniaturized and achieving higher area utilization without compromising its performance. This effectively solves the problem of the large size of existing planar power devices.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a planar power device, its fabrication method, and a chip. Background Technology

[0002] With the increasing integration of integrated circuits, laterally diffused metal-oxide semiconductors (LDMOS) are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially widely used in high-voltage power amplifier applications, such as LED drivers, switching converters, audio amplifiers, and power management products.

[0003] In practical applications, due to the limitations of the LDMOS device structure, when a large current and a large voltage are required, it is generally achieved by extending the channel distance between the drain region and the source region. However, the increase in channel length will bring unacceptable channel resistance and further increase the device area.

[0004] Therefore, existing LDMOS devices typically require a large chip area, making it an urgent technical problem to reduce the area of ​​LDMOS devices. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a planar power device, a fabrication method, and a chip, which can solve the problem of the large size of existing planar power devices.

[0006] This application provides a planar power device, the planar power device comprising:

[0007] Semiconductor substrate;

[0008] The N-type well region and the P-type well region are in contact with each other and located on the semiconductor substrate. The N-type well region has an "L" shape and the P-type well region has a "U" shape.

[0009] A gate oxide layer is located on the vertical portion of the N-type well region and on the recess wall of the P-type well region;

[0010] A gate metal layer is located on the gate oxide layer;

[0011] The source region and the P-type base region are both disposed within the groove of the P-type well region, and the source region is in contact with the gate oxide layer, and the P-type base region is in contact with the source region.

[0012] An isolation region and a drain region are disposed on the horizontal portion of the N-type well region, and the isolation region is disposed between the drain region and the gate oxide layer.

[0013] In one embodiment, both the source region and the drain region are doped with N-type ions, and the doping concentration of the source region and the drain region is at least 10 times that of the N-type well region.

[0014] In one embodiment, the sum of the lengths of the P-type base region and the source region is equal to the length of the isolation region.

[0015] In one embodiment, the length of the P-type base region is less than the length of the source region.

[0016] In one embodiment, the depths of the P-type base region and the source region are the same, and the depths of both the P-type base region and the source region are less than the depth of the P-type well region.

[0017] In one embodiment, the length of the P-type base region is 1 / 3 of the length of the source region.

[0018] In one embodiment, the depths of the P-type base region and the source region are both half the depth of the P-type well region.

[0019] In one embodiment, the length of the source region is equal to the length of the gate metal layer.

[0020] This application also provides a method for fabricating a planar power device, including:

[0021] An N-type well region and a P-type well region are sequentially formed on a semiconductor substrate; wherein the N-type well region and the P-type well region are in contact with each other and located on the semiconductor substrate, and the N-type well region has an "L" shaped structure and the P-type well region has a "U" shaped structure.

[0022] A source region and a P-type base region are formed on the P-type well region; wherein the source region and the P-type base region are both disposed in the groove of the P-type well region, and the P-type base region is in contact with the source region;

[0023] An isolation region and a drain region are formed on the N-type well region; wherein the isolation region and the drain region are disposed on the horizontal portion of the N-type well region, and the isolation region and the drain region are in contact;

[0024] An oxide layer is formed on the N-type well region, the P-type well region, the source region, and the isolation region, and the gate oxide layer is selectively etched to form a gate oxide layer on the vertical portion of the N-type well region and the groove wall of the P-type well region.

[0025] A gate metal layer is formed on the gate oxide layer.

[0026] This application also provides a chip, characterized in that it includes a plurality of planar power devices as described above or a plurality of planar power devices prepared by the preparation method described above.

[0027] The beneficial effects of this application embodiment compared with the prior art are as follows: by setting the N-type well region to an "L" shape and the P-type well region to a "U" shape, the source region and the P-type base region are both located in the groove of the P-type well region, and the isolation region and the drain region are located on the horizontal part of the N-type well region, thereby reducing the occupied area of ​​the planar power device. Without reducing the performance of the planar power device, the planar power device is made more miniaturized and has a higher area utilization rate, effectively solving the problem of the large size of existing planar power devices. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the vertical cross-sectional structure of a planar power device provided in one embodiment of this application;

[0029] Figure 2 This is a top view of a planar power device provided in one embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the fabrication steps of a planar power device according to an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of the formation of an N-type well region and a P-type well region according to an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the formation of the source region and the P-type base region according to an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the formation of the drain region and isolation region provided in one embodiment of this application;

[0034] Figure 7 This is a schematic diagram of the formation of a gate oxide layer provided in one embodiment of this application;

[0035] Figure 8 This is a schematic diagram of the formation of a gate oxide layer provided in one embodiment of this application;

[0036] Figure 9 This is a schematic diagram of a chip structure provided in one embodiment of this application. Detailed Implementation

[0037] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0038] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0039] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0041] With the increasing integration of integrated circuits, laterally diffused metal-oxide semiconductors (LDMOS) are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially widely used in high-voltage power amplifier applications, such as LED drivers, switching converters, audio amplifiers, and power management products.

[0042] In practical applications, due to the limitations of the LDMOS device structure, when a large current and a large voltage are required, it is generally achieved by extending the channel distance between the drain region and the source region. However, the increase in channel length will bring unacceptable channel resistance and further increase the device area.

[0043] Therefore, existing LDMOS devices typically require a large chip area, making it an urgent technical problem to reduce the area of ​​LDMOS devices.

[0044] This shows that existing planar power devices have the problem of large size.

[0045] To address the aforementioned technical problems, embodiments of this application provide a planar power device, referencing... Figure 1 , Figure 2 As shown, where Figure 2 for Figure 1 A top view of the planar power device. The planar power device includes: a semiconductor substrate 10, an N-type well region 20, a P-type well region 30, a gate oxide layer 40, a gate metal layer 50, a source region 60, a P-type base region 70, an isolation region 80, and a drain region 90.

[0046] Specifically, the N-type well region 20 and the P-type well region 30 are in contact with each other and located on the semiconductor substrate 10, with the N-type well region 20 having an "L"-shaped structure and the P-type well region 30 having a "U"-shaped structure; the gate oxide layer 40 is located on the vertical portion of the N-type well region 20 and on the groove wall of the P-type well region 30; the gate metal layer 50 is located on the gate oxide layer 40; the source region 60 and the P-type base region 70 are both disposed in the groove of the P-type well region 30, with the source region 60 in contact with the gate oxide layer 40 and the P-type base region 70 in contact with the source region 60; the isolation region 80 and the drain region 90 are disposed on the horizontal portion of the N-type well region 20, with the isolation region 80 disposed between the drain region 90 and the gate oxide layer 40.

[0047] In this implementation, the required withstand voltage for planar power devices varies depending on the application scenario. Existing planar power devices, when requiring high withstand voltage, typically improve their withstand voltage capability by increasing the distance between the source region 60 and the drain region 90. However, this significantly increases the size of the planar power device, resulting in material waste and a substantial increase in its area.

[0048] In this embodiment, the N-type well region 20 has an "L"-shaped structure, and the P-type well region 30 has a "U"-shaped structure. Both the source region 60 and the P-type base region 70 are located within the groove of the P-type well region 30. The recessed structure in the "U"-shaped structure is called a groove. Specifically, the first end of the P-type base region 70 contacts the first end of the source region 60. (Refer to...) Figure 1 As shown, it can be understood that the P-type base region 70 is located above the first end of the P-type well region 30, and the source region 60 is located above the second end of the P-type well region 30, with the P-type base region 70 in contact with the source region 60. By setting the first end of the P-type base region 70 to contact the first end of the source region 60, the P-type base region 70 and the source region 60 are linearly arranged, forming a column, and the vertical distances between the P-type base region 70, the source region 60, and the isolation region 80 are equal. This operation can greatly reduce the area of ​​the planar power device, which is different from the traditional planar device where the P-type base region 70 and the source region 60 each occupy a separate column, resulting in a larger area for the planar device.

[0049] In this embodiment, both the source region 60 and the P-type base region 70 are disposed within the groove of the P-type well region 30. It can be understood that the source region 60 and the P-type base region 70 are arranged in a row, both located within the groove. This significantly reduces the area of ​​the planar power device, unlike traditional planar devices where the P-type base region 70 and the source region 60 each occupy a separate row, resulting in a larger planar device area and wasted materials.

[0050] In this embodiment, the N-type well region 20 has an "L"-shaped structure. The isolation region 80 and the drain region 90 are disposed on the horizontal portion of the N-type well region 20, with the isolation region 80 located between the drain region 90 and the gate oxide layer 40. Specifically, the shallower part of the "L"-shaped structure is called the horizontal portion, and the deeper part is called the vertical portion. The isolation region 80 and the drain region 90 are disposed on the horizontal portion of the N-type well region 20. It can be understood that the isolation region 80 and the drain region 90 have the same thickness, and the sum of the thicknesses of the isolation region 80 and the horizontal portion is the same as the depth of the vertical portion. This allows the gate oxide layer 40 to be horizontally disposed on the vertical portion of the N-type well region 20, the recess wall of the P-type well region 30, the source region 60, and the drain region 90. This ensures that the gate oxide layer 40 simultaneously contacts the vertical portion of the N-type well region 20, the recess wall of the P-type well region 30, the source region 60, and the drain region 90, thereby achieving stable operation of the planar power device.

[0051] In one embodiment, both the source region 60 and the drain region 90 are doped with N-type ions, and the doping concentration of the source region 60 and the drain region 90 is at least 10 times the doping concentration of the N-type well region 20. Both the source region 60 and the drain region 90 are heavily doped. In this embodiment, the P-type base region 70 is doped with P-type ions, and is lightly doped. Both the source region 60 and the drain region 90 are doped with N-type ions, and are heavily doped. It can be understood that the doping concentration of the heavily doped ions is greater than 1*102. 19 cm -3 By setting both the source region 60 and the drain region 90 to be heavily doped, the performance of planar power devices can be reduced without compromising their performance, thus making planar power devices more miniaturized, with higher area utilization, and without reducing their performance.

[0052] In one embodiment, reference Figure 2 As shown, the sum of the length L1 of the P-type base region 70 and the length L2 of the source region 60 is equal to the length L3 of the isolation region 80.

[0053] Specifically, the P-type well region 30 has a U-shaped structure, and the length of the groove is equal to the length L3 of the isolation region 80. The P-type base region 70 and the source region 60 are disposed within the groove, and their lengths are equal to the length of the groove. In other words, the P-type base region 70 and the source region 60 completely fill the groove, forming a rectangle with the P-type base region 70, the source region 60, and the P-type well region 30. The thickness of the P-type base region 70 and the source region 60 after filling the groove is the same as the thickness of the vertical portion. In this embodiment, by setting the sum of the lengths of the P-type base region 70 and the source region 60 to be equal to the length of the isolation region 80, the area of ​​the planar power device can be reduced, improving the area utilization rate of the power device and providing a planar power device with efficient area utilization.

[0054] In one embodiment, reference Figure 2 As shown, the length L1 of the P-type base region 70 is less than the length L2 of the source region 60. Specifically, the P-type base region 70 is used to apply voltage. The source region 60 and the P-type base region 70 on the P-type well region 30 typically use the same voltage. Since the P-type base region 70 requires only a small area to maintain the voltage of the P-type well region 30, setting the length L1 of the P-type base region 70 to be less than the length L2 of the source region 60 allows the P-type base region 70 to apply voltage, ensuring the P-type well region 30 maintains the required voltage. Furthermore, it significantly reduces the area occupied by the planar power device. This improves the area utilization rate of the power device and provides a planar power device with efficient area utilization.

[0055] In one embodiment, reference Figure 1 As shown, the depth H1 of the P-type base region 70 and the source region 60 is the same, and the depth H1 of both the P-type base region 70 and the source region 60 is less than the depth H2 of the P-type well region 30. Specifically, the depth of the P-type base region 70 and the source region 60 is equal to the depth of the groove. This means that the P-type base region 70 and the source region 60 exactly fill the groove. By setting the depth of the P-type base region 70 and the source region 60 to be the same, the P-type well region 30 can maintain the required voltage after the P-type base region 70 is connected to a voltage source. On the other hand, this greatly reduces the area occupied by the planar power device. This improves the area utilization rate of the power device and provides a planar power device with efficient area utilization.

[0056] In one embodiment, reference Figure 2As shown, the length L1 of the P-type base region 70 is 1 / 3 of the length L2 of the source region 60. Specifically, the P-type base region 70 is used to connect a voltage. The source region 60 and the P-type base region 70 on the P-type well region 30 usually use the same voltage. However, the P-type base region 70 only requires a small area to maintain the voltage of the P-type well region 30. Therefore, setting the length of the P-type base region 70 to 1 / 3 of the length of the source region 60 allows the P-type base region 70 to connect a voltage, enabling the P-type well region 30 to maintain the required voltage. On the other hand, it greatly reduces the area occupied by the planar power device, improves the area utilization rate of the power device, and provides a planar power device with efficient area utilization.

[0057] In one embodiment, reference Figure 1 As shown, the depth H1 of both the P-type base region 70 and the source region 60 is half the depth H2 of the P-type well region 30. It can be understood that when voltage is applied through the P-type base region 70, an electric field is generated through the P-type well region 30. By setting the depths of both the P-type base region 70 and the source region 60 to be half the depth of the P-type well region 30, the depth of the source region 60 is made consistent with the depth of the isolation region 80. This operation maintains a higher breakdown voltage, improves the breakdown voltage capability of the planar power device, and enhances the breakdown voltage capability without increasing the area. This allows the planar power device to improve its breakdown voltage capability while reducing its area.

[0058] In one embodiment, the length of the source region 60 is equal to the length of the gate metal layer 50. Specifically, the length of the gate metal layer 50 is equal to the length of the gate oxide layer 40. It is understood that the lengths of the source region 60, the gate metal layer 50, and the gate oxide layer 40 are all equal. In this embodiment, when the planar power device starts operating, when the voltage is applied through the P-type base region 70, it passes sequentially through the source region 60, the gate oxide layer 40, and the drain region 90. It is known that the gate oxide layer 40 and the gate metal layer 50 do not need to contact the P-type base region 70 for operation. Therefore, setting the length of the source region 60 to be equal to the length of the gate metal layer 50 ensures that the gate metal layer 50 or the gate oxide layer 40 does not contact the P-type base region 70, saving materials and reducing the area occupied by the planar power device, thus improving the area utilization rate of the power device and providing a planar power device with efficient area utilization.

[0059] In one embodiment, the P-type well region 30 has a U-shaped structure, which can be a U-shaped structure. This allows the area of ​​the P-type base region 70 and the source region 60 in the U-shaped structure that is far from the gate metal layer 50 to be smaller than the area of ​​the area that is close to the gate metal layer 50. That is, the source region 60 is divided into two parts according to its distance from the gate metal layer 50. The part of the source region 60 that is far from the gate metal layer 50 and close to the semiconductor substrate 10 is defined as the first part, and the part of the source region 60 that is close to the gate metal layer 50 and far from the semiconductor substrate 10 is defined as the second part. By setting the area of ​​the first part to be smaller than the area of ​​the second part, the first part of the source region 60 can have a higher breakdown voltage, and the second part of the source region 60 can have a lower on-resistance. This operation can optimize the design balance between breakdown voltage and on-resistance and improve the overall performance of the planar power device.

[0060] In one embodiment, the P-type well region 30 has a U-shaped structure, which can be a stepped structure. Specifically, the width of the groove in the P-type well region 30 gradually decreases with depth. It can be understood that the area of ​​the part away from the gate metal layer 50 is smaller than the area of ​​the part close to the gate metal layer 50. That is, the source region 60 is divided into two parts according to its distance from the gate metal layer 50. The part of the source region 60 away from the gate metal layer 50 and close to the semiconductor substrate 10 is defined as the first part, and the part of the source region 60 close to the gate metal layer 50 and away from the semiconductor substrate 10 is defined as the second part. By setting the area of ​​the first part to be smaller than the area of ​​the second part, the first part of the source region 60 can increase the withstand voltage, and the second part of the source region 60 can reduce the on-resistance. This operation can optimize the design balance between withstand voltage and on-resistance and improve the overall performance of the planar power device.

[0061] In one embodiment, both the source region 60 and the drain region 90 are doped with N-type ions, and both are heavily doped. The doping concentration in the source region 60 is not uniform; specifically, the doping concentration in the source region 60 closer to the P-type base region 70 is greater than that further away from the P-type base region 70. This is because breakdown effects are prone to occur at the device's edge. By setting the doping concentration in the source region 60 closer to the P-type base region 70 to be greater than that further away from the P-type base region 70, the voltage distribution of the device can be made more uniform, extending the lifetime of the planar power device.

[0062] This application also provides a method for fabricating a planar power device, referring to... Figure 3 As shown, it includes steps S10-S50.

[0063] Step S10: Reference Figure 4As shown, an N-type well region 20 and a P-type well region 30 are sequentially formed on a semiconductor substrate 10; wherein, the N-type well region 20 and the P-type well region 30 are in contact with each other and located on the semiconductor substrate 10, and the N-type well region 20 has an "L" shaped structure and the P-type well region 30 has a "U" shaped structure.

[0064] Step S20: Reference Figure 5 As shown, a source region 60 and a P-type base region 70 are formed on the P-type well region 30; wherein, the source region 60 and the P-type base region 70 are both disposed in the groove of the P-type well region 30, and the P-type base region 70 is in contact with the source region 60.

[0065] Step S30: Reference Figure 6 As shown, an isolation region 80 and a drain region 90 are formed on the N-type well region 20; wherein the isolation region 80 and the drain region 90 are disposed on the horizontal portion of the N-type well region 20, and the isolation region 80 and the drain region 90 are in contact.

[0066] Step S40: Reference Figure 7 As shown, oxide layers are formed on the N-type well region 20, the P-type well region 30, the source region 60 and the isolation region 80, and the gate oxide layer 40 is selectively etched to form the gate oxide layer 40 on the vertical portion of the N-type well region 20 and the groove wall of the P-type well region 30.

[0067] Step S50: Reference Figure 8 As shown, a gate metal layer 50 is formed on the gate oxide layer 40.

[0068] In this embodiment, the N-type well region 20 has an "L"-shaped structure, and the P-type well region 30 has a "U"-shaped structure. Both the source region 60 and the P-type base region 70 are located within the groove of the P-type well region 30. The recessed structure in the "U"-shaped structure is called a groove. Specifically, the first end of the P-type base region 70 contacts the first end of the source region 60. (Refer to...) Figure 1 As shown, it can be understood that the P-type base region 70 is located above the first end of the P-type well region 30, and the source region 60 is located above the second end of the P-type well region 30, with the P-type base region 70 in contact with the source region 60. By setting the first end of the P-type base region 70 to contact the first end of the source region 60, the P-type base region 70 and the source region 60 are linearly arranged, forming a column, and the vertical distances between the P-type base region 70, the source region 60, and the isolation region 80 are equal. This operation can greatly reduce the area of ​​the planar power device, which is different from the traditional planar device where the P-type base region 70 and the source region 60 each occupy a separate column, resulting in a larger area for the planar device.

[0069] In this embodiment, both the source region 60 and the P-type base region 70 are disposed within the groove of the P-type well region 30. It can be understood that the source region 60 and the P-type base region 70 are arranged in a row, both located within the groove. This significantly reduces the area of ​​the planar power device, unlike traditional planar devices where the P-type base region 70 and the source region 60 each occupy a separate row, resulting in a larger planar device area and wasted materials.

[0070] In this embodiment, the N-type well region 20 has an "L"-shaped structure. The isolation region 80 and the drain region 90 are disposed on the horizontal portion of the N-type well region 20, with the isolation region 80 located between the drain region 90 and the gate oxide layer 40. Specifically, the shallower part of the "L"-shaped structure is called the horizontal portion, and the deeper part is called the vertical portion. The isolation region 80 and the drain region 90 are disposed on the horizontal portion of the N-type well region 20. It can be understood that the isolation region 80 and the drain region 90 have the same thickness, and the sum of the thicknesses of the isolation region 80 and the horizontal portion is the same as the depth of the vertical portion. This allows the gate oxide layer 40 to be horizontally disposed on the vertical portion of the N-type well region 20, the recess wall of the P-type well region 30, the source region 60, and the drain region 90. This ensures that the gate oxide layer 40 simultaneously contacts the vertical portion of the N-type well region 20, the recess wall of the P-type well region 30, the source region 60, and the drain region 90, thereby achieving stable operation of the planar power device.

[0071] In one embodiment, both the drain region 90 and the source region 60 can be fabricated using multilayer metal materials, which is beneficial for forming ohmic contacts.

[0072] This application also provides a chip, including multiple planar power devices as described above or multiple planar power devices fabricated by the fabrication method described above.

[0073] In this embodiment, reference Figure 9 As shown, when multiple planar power devices work together, the adjacent source regions 60 of adjacent planar power devices are arranged diagonally. It can be understood that the adjacent P-type base regions 70 are also arranged diagonally. This is because when planar power devices are working, the source region 60 closer to the P-type base region 70 has a larger voltage, while the source region 60 farther from the P-type base region 70 has a smaller voltage. Arranging the adjacent source regions 60 of adjacent planar power devices diagonally can make the electric field distribution of the chip more uniform when it is working, and can reduce the leakage current from the drain region 90 to the P-type base region 70, thus extending the life of the chip.

[0074] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0075] The units described as separate components may or may not be physically separate. The components that display data may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0076] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A planar power device, characterized by The planar power device includes: Semiconductor substrate; The N-type well region and the P-type well region are in contact with each other and located on the semiconductor substrate. The N-type well region has an "L" shaped structure and the P-type well region has a "U" shaped structure. A gate oxide layer is located on the upper surface of the semiconductor substrate above the vertical portion of the N-type well region and the recess wall of the P-type well region; A gate metal layer is located on the gate oxide layer; The source region and the P-type base region are both disposed within the groove of the P-type well region. The P-type base region and the source region are disposed adjacent to each other along the length of the groove, and the source region is in contact with the gate oxide layer, while the P-type base region is in contact with the source region. An isolation region and a drain region are disposed on the horizontal portion of the N-type well region, and the isolation region is disposed between the drain region and the gate oxide layer; Wherein, along the groove direction of the P-type well region, the sum of the lengths of the P-type base region and the source region is equal to the length of the isolation region.

2. The planar power device of claim 1, wherein, Both the source region and the drain region are doped with N-type ions, and the doping concentration of the source region and the drain region is at least 10 times that of the N-type well region.

3. The planar power device of claim 1, wherein, Along the groove direction of the P-type well region, the length of the P-type base region is less than the length of the source region.

4. The planar power device of claim 1, wherein, The P-type base region and the source region have the same depth, and the depths of both the P-type base region and the source region are less than the depth of the P-type well region.

5. The planar power device as described in claim 3, characterized in that, Along the groove direction of the P-type well region, the length of the P-type base region is 1 / 3 of the length of the source region.

6. The planar power device as described in claim 4, characterized in that, The depths of the P-type base region and the source region are both half the depth of the P-type well region.

7. The planar power device as described in claim 1, characterized in that, The length of the source region is equal to the length of the gate metal layer.

8. A method for fabricating a planar power device, characterized in that, include: An N-type well region and a P-type well region are sequentially formed on a semiconductor substrate; wherein the N-type well region and the P-type well region are in contact with each other and located on the semiconductor substrate, and the N-type well region has an "L" shaped structure and the P-type well region has a "U" shaped structure; A source region and a P-type base region are formed on the P-type well region; wherein, the source region and the P-type base region are both disposed in the groove of the P-type well region, the P-type base region and the source region are disposed adjacent to each other along the length direction of the groove, and the P-type base region is in contact with the source region; An isolation region and a drain region are formed on the N-type well region; wherein the isolation region and the drain region are disposed on the horizontal portion of the N-type well region, and the isolation region and the drain region are in contact; An oxide layer is formed on the N-type well region, the P-type well region, the source region, and the isolation region, and the gate oxide layer is selectively etched to form a gate oxide layer on the upper surface of the semiconductor substrate above the vertical portion of the N-type well region and the groove wall of the P-type well region; wherein, along the groove direction of the P-type well region, the sum of the lengths of the P-type base region and the source region is equal to the length of the isolation region; A gate metal layer is formed on the gate oxide layer.

9. A chip, characterized in that, It includes multiple planar power devices as described in any one of claims 1-7 or multiple planar power devices prepared by the preparation method described in claim 8.

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