Power converter device and power conversion method

Abstract

A power converter apparatus includes a converter circuit, a detection circuitry, an energy distribution logic circuit, and a ramp generator circuit. The converter circuit selectively switches a plurality of charging paths and a plurality of discharging paths of an inductor according to a plurality of switching signals to generate a plurality of output voltages. The detection circuitry generates a plurality of error signals according to the output voltages and a plurality of reference voltages, and compares the error signals with a plurality of ramp signals to generate a plurality of decision signals, respectively. The energy distribution logic circuit generates the switching signals and a plurality of control signals according to the decision signals. The ramp generator circuit generates the ramp signals according to the control signals, wherein a start time of each of the ramp signals is different from one another.

Description

TECHNICAL FIELD

[0001] The present application relates to power converter apparatuses, and more particularly, to power converter apparatuses using single inductor multiple outputs and power conversion methods thereof. BACKGROUND

[0002] In related art employing an interleaving energy-conservation mode, a converter circuit generates a sense voltage by summing up a plurality of error signals generated from different output voltages to regulate the output voltages. In these techniques, since the sense voltage is generated by superimposing a plurality of error signals, the level of the sense voltage can be too high to be suitable for low voltage applications. In addition, since the sense voltage encompasses information from a plurality of error signals of different output voltages, the cross-regulation of the converter circuit can be affected. SUMMARY

[0003] In some embodiments, a power converter apparatus includes a converter circuit, a detection circuit system, an energy distribution logic circuit, and a ramp generator circuit. The converter circuit is configured to selectively switch a plurality of charging paths and a plurality of discharging paths of an inductor according to a plurality of switching signals to generate a plurality of output voltages. The detection circuit system is configured to generate a plurality of error signals according to the output voltages and a plurality of reference voltages, and compare the error signals with a plurality of ramp signals to generate a plurality of decision signals. The energy distribution logic circuit is configured to generate the switching signals and a plurality of control signals according to the decision signals. The ramp generator circuit is configured to generate the ramp signals according to the control signals, wherein a start time of a first ramp signal of the ramp signals is different from a start time of a second ramp signal of the ramp signals.

[0004] In some embodiments, a power conversion method includes the following operations: selectively switching a plurality of charging paths and a plurality of discharging paths of an inductor according to a plurality of switching signals to generate a plurality of output voltages; generating a plurality of error signals according to the output voltages and a plurality of reference voltages, and comparing the error signals with a plurality of ramp signals to generate a plurality of decision signals; generating the switching signals and a plurality of control signals according to the decision signals; and generating the ramp signals according to the control signals, wherein a start time of each of the ramp signals is different from each other.

[0005] The features, implementations, and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1FIG. 1 shows a schematic diagram of a power converter apparatus according to some embodiments of the present application;

[0007] Figure 2A FIG. 2 shows a schematic diagram of a detection circuit according to some embodiments of the present application; Figure 1

[0008] Figure 2B FIG. 3 shows a schematic diagram of a ramp generator circuit according to some embodiments of the present application; Figure 1

[0009] Figure 3A FIG. 4 shows a waveform diagram of related signals in FIG. 3 according to some embodiments of the present application; Figure 1

[0010] Figure 3B FIG. 5 shows a waveform diagram of related signals in FIG. 4 according to some embodiments of the present application; and Figure 1

[0011] Figure 4 FIG. 6 shows a flowchart of a power conversion method according to some embodiments of the present application. DETAILED DESCRIPTION

[0012] All words used herein are to be interpreted according to their normal meaning. Definitions of the above words in common usage dictionaries, including any examples of usage of the words discussed herein, are to be construed as examples only and are not to limit the scope and meaning of the present application. Similarly, the present application is not to be limited to the various embodiments shown in the specification.

[0013] As used herein, "coupled" or "connected" can mean either a direct electrical or physical contact between two or more components or an indirect electrical or physical contact between two or more components through another component. As used herein, the term "circuitry" can mean a single system formed from at least one circuit, and the term "circuit" can mean a device that processes signals by way of at least one transistor and / or at least one passive component connected in a certain manner.

[0014] As used herein, the term "and / or" includes any combination of one or more of the associated listed items. As used herein, the terms first, second, and third, etc. are used to describe and distinguish various components. Thus, the terms first component, second component, and third component can be used interchangeably with the terms second component, first component, and third component, respectively, without departing from the spirit of the present application. For ease of understanding, similar components in the various drawings will be designated by identical reference numerals.

[0015] Figure 1 ​​​​A schematic diagram of a power converter apparatus 100 is drawn according to some embodiments of the present application. The power converter apparatus 100 comprises a converter circuit 110, a detection circuitry 120, an energy distribution logic circuit 130, a ramp generator circuit 140 and a mode switching circuit 150.

[0016] The converter circuit 110 can be a single-inductor multi-output (SIMO) DC-DC converter circuit. In this example, the converter circuit 110 is a single-inductor dual-output (SINDO) DC-DC converter circuit, which can generate two output voltages V IN and V OA according to an input signal Vin OB , but the present application is not limited thereto. In other embodiments, the converter circuit 110 can generate 2 or more output voltages.

[0017] In some embodiments, the converter circuit 110 can selectively switch a plurality of charging and discharging paths of the inductor L according to a plurality of switching signals S1-S4 to generate the output voltages V OA and V OB . In detail, the converter circuit 110 comprises a plurality of switches SW1-SW4 and an inductor L. The plurality of switches SW1-SW4 can be implemented by, but not limited to, power transistors. A first terminal of the switch SW1 is configured to receive the input signal Vin IN , a second terminal of the switch SW1 is coupled to a first terminal of the switch SW2 and a first terminal of the inductor L, and a control terminal of the switch SW1 is configured to receive the switching signal S1. A second terminal of the switch SW2 is coupled to ground, and a control terminal of the switch SW2 is configured to receive the switching signal S2. A first terminal of the switch SW3 is coupled to a second terminal of the inductor L, a second terminal of the switch SW3 is configured to generate the output voltage V OA , and a control terminal of the switch SW3 is configured to receive the switching signal S3. A first terminal of the switch SW4 is coupled to the second terminal of the inductor L, a second terminal of the switch SW4 is configured to generate the output voltage V OB , and a control terminal of the switch SW4 is configured to receive the switching signal S4.

[0018] When the switches SW1 and SW3 are turned on and the switches SW2 and SW4 are turned off, the turned-on switches SW1 and SW3 can form a first charging path of the inductor L. In this condition, the inductor L can be charged by the input signal Vin IN . During the energy storage of the inductor L, the inductor L simultaneously transfers energy to a node for generating the output voltage V OA , and thus the current i LIt has a positive slope. When switches SW2 and SW3 are conducting and switches SW1 and SW4 are not conducting, the conducting switches SW2 and SW3 can form the first discharge path of inductor L. Under this condition, inductor L cannot discharge based on the input signal V. IN It stores energy and then discharges the stored energy to generate the output voltage V. OA The node, therefore the current i in inductor L L It has a negative slope.

[0019] When switches SW1 and SW4 are on and switches SW2 and SW3 are off, the on-state switches SW1 and SW4 can form a second charging path for inductor L. Under this condition, inductor L can be charged by the input signal V. IN Charging. During the period of storing energy in inductor L, inductor L can simultaneously transfer energy to generate the output voltage V. OB At a node, therefore the current i in inductor L is... L It has a positive slope. When switches SW2 and SW4 are conducting and switches SW1 and SW3 are not conducting, the conducting switches SW2 and SW4 can form a second discharge path for inductor L. Under this condition, inductor L cannot discharge based on the input signal V. IN It stores energy and then discharges the stored energy to generate the output voltage V. OB The node, therefore the current i in inductor L L It has a negative slope.

[0020] The detection circuit system 120 is used to generate multiple error signals based on multiple output voltages and multiple reference voltages, and compares the multiple error signals with multiple ramp signals to generate multiple decision signals. For example, the detection circuit system 120 can generate multiple decision signals based on multiple output voltages V. OA With V OB and multiple reference voltages V REFA With V REFB Generate multiple error signals (e.g., for) Figure 2A Error signal S EA With S EB The detection circuit system 120 can compare a first error signal (e.g., a...) among multiple error signals. Figure 2A Error signal S EA ) and ramp signal S ra To generate decision signal S DA And compare the second error signal among multiple error signals (e.g., for example) Figure 2A Error signal S EB ) and ramp signal S rb To generate decision signal S DB .

[0021] In some embodiments, the detection circuit system 120 directly detects multiple output voltages V. OA With V OB Alternatively, depending on the practical application, in some other embodiments, the power converter device 100 may also include a voltage divider circuit (not shown) that can divide the output voltage V OA With output voltage V OB A voltage divider is used to generate a first feedback signal (not shown) and a second feedback signal (not shown). Thus, the detection circuit system 120 can determine the feedback signal based on the first feedback signal, the second feedback signal, and multiple reference voltages V. REFA With V REFB Multiple error signals are generated.

[0022] The energy distribution logic circuit 130 can determine the energy distribution based on the decision signal S. DA With decision signal S DB Generate multiple control signals S c1 ~S c4 Multiple switching signals S1 to S4 are used to switch multiple charging and discharging paths of inductor L according to the current load demand. In some embodiments, the energy distribution logic circuit 130 may be a digital logic circuit, which can perform actions such as... Figure 3A or Figure 3B The related operations shown are used to generate multiple control signals S c1 ~S c4 With multiple switching signals S1 to S4.

[0023] The ramp generator circuit 140 generates multiple ramp signals based on multiple control signals. For example, the ramp generator circuit 140 generates multiple ramp signals based on multiple control signals S. c1 ~S c4 Generate ramp signal S rc With ramp signal S rd The mode switching circuit 150 can switch according to the mode signal S. M Selectively output ramp signal S rc For the ramp signal S ra With ramp signal S rb One of them, and outputs the ramp signal S. rd For the ramp signal S ra With ramp signal S rb The other one. In some embodiments, the mode switching circuit 150 may be a switching circuit formed by a plurality of switches, which can switch according to the mode signal S. M Selectively output ramp signal S rc With ramp signal S rd For the ramp signal S ra With ramp signal S rb .

[0024] For example, when the mode signal SM When the signal has a first logic value (e.g., logic 0), the mode switching circuit 150 can switch the ramp signal S... rc The output is a ramp signal S ra and the ramp signal S rd The output is a ramp signal S rb Under these conditions, one corresponding to a plurality of error signals (e.g., for example, ...) Figure 2A Error signal S EA This can be used to determine the transition point from the first charging path to the second charging path (e.g., for example, ...). Figure 3A The transition point N1) and the transition point from the second discharge path to the first discharge path (e.g., the ... Figure 3A The transition point N2). Or, when the mode signal S M When the second logic value is present (e.g., logic 1), the mode switching circuit 150 can switch the ramp signal S... rd The output is a ramp signal S ra and the ramp signal S rc The output is a ramp signal S rb Under these conditions, another of the multiple error signals (e.g., for example) Figure 2A Error signal S EB This can be used to determine the transition point from the second charging path to the first charging path (e.g., for example, ...). Figure 3B The transition point N3) and the transition point from the first discharge path to the second discharge path (e.g., the transition point N3) Figure 3B The transition point N4). Details regarding this operation will be provided later. Figure 3A and Figure 3B Please provide an explanation.

[0025] In some embodiments, the start time of each of the plurality of ramp signals generated by the ramp generator circuit 140 is different from that of each other. For example, as follows Figure 3A or Figure 3B As shown, the ramp signal S ra The start time is different from the ramp signal S rb The start time. In other words, the detection circuit system 120 detects multiple error signals (e.g., error signal S) at different times. EA With error signal S EB ) respectively with multiple ramp signals (e.g., ramp signal S) ra With ramp signal S rb) are compared. In some related arts, a single-inductor dual-output converter circuit sums multiple error signals to generate a sense voltage, and controls the charging and discharging path of the inductor according to the sense voltage. In these arts, since the sense voltage is generated by summing two error signals, the level of the sense voltage is higher than the level of a single error signal, and thus the level of the ramp signal used for comparison is also higher. As such, the sense voltage and / or the ramp signal can be close to saturation in a low voltage environment, and thus are not suitable for low voltage applications. In addition, since the sense voltage is generated based on multiple error signals related to multiple output voltages, the multiple output voltages can affect each other, and thus the cross-regulation of the converter circuit is high.

[0026] In contrast to the above arts, as previously described, the detection circuitry 120 compares the multiple error signals S EA and S EB to the multiple ramp signals S ra and S rb at different times. In other words, the detection circuitry 120 can generate the decision signals S EA and S EB without summing the error signals S DA and S DB . As such, the levels of the multiple ramp signals S ra and S rb can be reduced, and thus the power converter device 100 can be suitable for low voltage and low power requirements. In addition, since the error signals S EA are not summed, the output voltages V OA and V OB can be controlled separately. As such, the cross-regulation of the converter circuit 110 can be improved.

[0027] The above description is based on two output voltages V OA and V OB , but the present disclosure is not limited thereto. In other examples, if the converter circuit 110 is configured to generate multiple output voltages V OA , V OB , …, V ON (not shown), the detection circuitry 120 can generate multiple error signals S EA , S EB , …, S EN based on the multiple output voltages V EA , V EB , …, V EN and multiple reference voltages V ra , V rb , …, V rn (not shown).EN (Not shown). The detection circuit system 120 can detect multiple error signals S. EA S EB S EN (Not shown) are respectively associated with multiple ramp signals S ra S rb S rn (Not shown) Comparisons are made to generate multiple decision signals S. DA S DB S DN (Not shown). In other words, various configurations of the converter circuit 110, the detection circuit system 120, the energy distribution logic circuit 130, and the ramp generator circuit 140 that can be used to generate two or more output voltages are all within the scope of this application.

[0028] Figure 2A Drawing based on some embodiments of this case Figure 1 A schematic diagram of the detection circuit system 120. The detection circuit system 120 includes an error amplifier circuit 201, an error amplifier circuit 202, a comparator circuit 203, and a comparator circuit 204.

[0029] Error amplifier circuit 201 is used to adjust the output voltage V based on the error amplifier circuit 201. OA With reference voltage V REFA Generate error signal S EA The error amplifier circuit 202 is used to adjust the output voltage V. OB With reference voltage V REFB Generate error signal S EB The comparator circuit 203 is used to compare the error signal S. EA With ramp signal S ra To generate decision signal S DA For example, when the error signal S EA Less than or equal to the ramp signal S ra At that time, comparator circuit 203 generates a decision signal S with a logic value of 0. DA Or, when the error signal S EA Greater than the ramp signal S ra At that time, comparator circuit 203 generates a decision signal S with a logic value of 1. DA Similarly, comparator circuit 204 is used to compare the error signal S. EB With ramp signal S rb To generate decision signal S DB For example, when the error signal S EB Less than or equal to the ramp signal S rb At that time, comparator circuit 204 generates a decision signal S with a logic value of 0. DB When the error signal SEB Greater than the ramp signal S rb At that time, comparator circuit 204 generates a decision signal S with a logic value of 1. DB .

[0030] Figure 2B Drawing based on some embodiments of this case Figure 1 A schematic diagram of the ramp generator circuit 140 is shown. The ramp generator circuit 140 includes multiple current source circuits 211-214, multiple switches SW5-SW8, and multiple capacitors C1-C2. Switches SW5 and SW6 operate according to control signal S. c1 With control signal S c2 Control capacitor C1 to generate ramp signal S rc Switches SW7 and SW8 are controlled by signal S. c3 With control signal S c4 Control capacitor C2 to generate ramp signal S rd .

[0031] In detail, the first terminal of the current source circuit 211 receives voltage VDD, and the second terminal of the current source circuit 211 is coupled to the first terminal of switch SW5. The second terminal of switch SW5 is coupled to the first terminal of switch SW6, and the control terminal of switch SW5 receives control signal S. c1 The second terminal of switch SW6 is coupled to the first terminal of current source circuit 212, and the control terminal of switch SW6 receives control signal S. c2 The second terminal of current source circuit 212 is coupled to ground. The first terminal of capacitor C1 is coupled to the second terminal of switch SW5 and the first terminal of switch SW6 to generate a ramp signal S. rc Furthermore, the second terminal of capacitor C1 is coupled to ground. When switch SW5 responds to control signal S... c1 When turned on, the current source circuit 211 can charge capacitor C1 to generate a ramp signal S with a positive slope. rc Alternatively, when switch SW6 responds to control signal S c2 When the circuit is turned on, capacitor C1 can discharge through current source circuit 212 to generate a ramp signal S with a negative slope. rc .

[0032] Similarly, the first terminal of the current source circuit 213 receives voltage VDD, and the second terminal of the current source circuit 213 is coupled to the first terminal of switch SW7. The second terminal of switch SW7 is coupled to the first terminal of switch SW8, and the control terminal of switch SW7 receives control signal S. c3 The second terminal of switch SW8 is coupled to the first terminal of current source circuit 214, and the control terminal of switch SW8 receives control signal S. c4The second terminal of current source circuit 214 is coupled to ground. The first terminal of capacitor C2 is coupled to the second terminal of switch SW7 and the first terminal of switch SW8 to generate a ramp signal S. rd Furthermore, the second terminal of capacitor C2 is coupled to ground. When switch SW7 responds to control signal S... c3 When turned on, the current source circuit 213 can charge capacitor C2 to generate a ramp signal S with a positive slope. rd Alternatively, when switch SW8 responds to control signal S c4 When the circuit is turned on, capacitor C2 can discharge through current source circuit 214 to generate a ramp signal S with a negative slope. rd .

[0033] In some embodiments, current source circuit 211 and current source circuit 213 have substantially the same current value, current source circuit 212 and current source circuit 214 have substantially the same current value, and capacitor C1 and capacitor C2 have substantially the same capacitance value. This ensures that the ramp signal S... ra With ramp signal S rb It can have substantially the same positive slope (as in the following) Figure 3A (As shown). The above-described configuration of current source circuit 211, current source circuit 213, capacitor C1, and capacitor C2 is for illustrative purposes only and is not limited to this embodiment.

[0034] Figure 3A Drawing based on some embodiments of this case Figure 1 The waveforms of the relevant signals are shown in the diagram. In this example, the mode signal S... M It has a first logic value (e.g., logic 0). As previously stated, under this condition, the mode switching circuit 150 can convert the ramp signal S... rc The output is a ramp signal S ra and the ramp signal S rd The output is a ramp signal S rb Error signal S EA It can be used to determine the transition point N1 from the first charging path to the second charging path and the transition point N2 from the second discharging path to the first discharging path.

[0035] For example, during a period between time T0 and time T1, comparator circuit 203 confirms the error signal S. EA Greater than the ramp signal S ra Under these conditions, the decision signal S DA It has a logic value of 1. Respond to this decision signal S DAThe energy distribution logic circuit 130 outputs multiple switching signals S1 and S3 with a first preset level (e.g., high level) and multiple switching signals S2 and S4 with a second preset level (e.g., low level). In this way, switches SW1 and SW4 are turned on to form the first charging path of inductor L, while switches SW2 and SW4 are not turned on.

[0036] At time T1, comparator circuit 203 confirms the error signal S. EA Equal to the ramp signal S ra It outputs a decision signal S with a logic value of 0. DA . Respond to this decision signal S DA The energy distribution logic circuit 130 generates multiple switching signals S1 and S4 with a first preset level and multiple switching signals S2 and S3 with a second preset level. As a result, switches SW1 and SW4 are turned on to form a second charging path for inductor L, while switches SW2 and SW3 are turned off. On the other hand, in response to this decision signal S... DA The energy distribution logic circuit 130 further generates multiple corresponding control signals S. c3 With S c4 Thus, when the error signal S EA Equal to the ramp signal S ra At that time, the ramp generator circuit 140 can generate a ramp signal S. rb In detail, it responds to multiple control signals S c3 With S c4 With switch SW7 turned on and switch SW8 turned off, the current source circuit 213 can begin charging capacitor C2 to generate a ramp signal S. rd The mode switching circuit 150 can output a ramp signal S. rd For the ramp signal S rb .like Figure 3A As shown, unlike the ramp signal S ra The start time (e.g., time T0), the ramp signal S rb The start time is time T1 and can be determined by the ramp signal S. ra and error signal S EA The comparison results determine this. Furthermore, the ramp signal S... ra The positive slope is the same as the slope signal S. rb The positive slope. For example, the slope signal S. ra The slope during the period between time T0 and time T2 is m (m is a positive number), and the ramp signal S rb The slope during the period between time T1 and time T2 is also m.

[0037] At time T2, comparator circuit 204 confirms the error signal S. EBEqual to the ramp signal S rb It outputs a decision signal S with a logic value of 0. DB . Respond to this decision signal S DB The energy distribution logic circuit 130 generates multiple switching signals S2 and S4 with a first preset level and multiple switching signals S1 and S3 with a second preset level. As a result, switches SW2 and SW4 are turned on to form a second discharge path for inductor L, while switches SW1 and SW3 are turned off.

[0038] On the other hand, in response to this decision signal S DB The energy distribution logic circuit 130 further generates multiple corresponding control signals S. c1 ~S c4 Thus, when the error signal S EB Equal to the ramp signal S rb At that time, the ramp generator circuit 140 can reduce the ramp signal S. ra With ramp signal S rb The level. Specifically, in response to multiple control signals S c1 ~S c4 Switches SW6 and SW8 are conducting, while switches SW5 and SW7 are not conducting. Thus, capacitor C1 can discharge via current source circuit 212, initiating the reduction of the ramp signal S. rc (Its output is the ramp signal S) ra The level of the ramp signal S. Similarly, capacitor C2 can discharge via current source circuit 214 to begin reducing the ramp signal S. rd (Its output is the ramp signal S) rb The level of ).

[0039] During the period between time T3 and time T4, comparator circuit 203 confirms the error signal S. EA Greater than the ramp signal S ra It outputs a decision signal S with a logic value of 1. DA . Respond to this decision signal S DA The energy distribution logic circuit 130 generates multiple switching signals S2 and S3 with a first preset level and multiple switching signals S1 and S4 with a second preset level. As a result, switches SW2 and SW3 are turned on to form the first discharge path of inductor L, while switches SW1 and SW4 are not turned on.

[0040] In some embodiments, the start time of each of the plurality of ramp signals is not different from each other. In some embodiments, the end time of each of the plurality of ramp signals is different from each other. For example, as... Figure 3A As shown, the ramp signal S ra The start time (e.g., time T0) is different from the ramp signal S. rbThe start time (e.g., time T1), and the ramp signal S ra The end time (e.g., time T4) is different from the ramp signal S. rb The end time (e.g., time T2). In other words, the detection circuit system 120 detects the ramp signal S at different times. ra With ramp signal S rb Generate multiple corresponding decision signals S DA With S DB Thus, without summing the error signal S EA With error signal S EB Under these conditions, the power converter device 100 can stably regulate the output voltage V. OA With output voltage V OB .

[0041] Figure 3B Drawing based on some embodiments of this case Figure 1 The waveforms of the relevant signals are shown in the diagram. In this example, the mode signal S... M It has a second logic value (e.g., logic value 1). As previously stated, under this condition, the mode switching circuit 150 can convert the ramp signal S... rd The output is a ramp signal S ra and the ramp signal S rc The output is a ramp signal S rb And the error signal S EB It can be used to determine the transition point N3 when switching from the second charging path to the first charging path and the transition point N4 when switching from the first discharging path to the second discharging path.

[0042] For example, during the period between time T0 and time T1, comparator circuit 204 confirms the error signal S. EB Greater than pulse signal S rb Under these conditions, the decision signal S DB All have a logical value of 1. Respond to this decision signal S DB The energy distribution logic circuit 130 outputs multiple switching signals S1 and S4 with a first preset level and multiple switching signals S2 and S3 with a second preset level. As a result, switches SW1 and SW4 are turned on to form a second charging path for inductor L, while switches SW2 and SW3 are turned off.

[0043] At time T1, comparator circuit 204 confirms the error signal S. EB Equal to the ramp signal S rb It outputs a decision signal S with a logic value of 0. DB . Respond to this decision signal S DBThe energy distribution logic circuit 130 generates multiple switching signals S1 and S3 with a first preset level and multiple switching signals S2 and S4 with a second preset level. As a result, switches SW1 and SW3 are turned on to form a first charging path for inductor L, while switches SW2 and SW4 are turned off. On the other hand, in response to this decision signal S... DB The energy distribution logic circuit 130 further generates multiple corresponding control signals S. c3 With S c4 Thus, when the error signal S EB Equal to the ramp signal S rb At that time, the ramp generator circuit 140 can generate a ramp signal S. ra In detail, it responds to multiple control signals S c3 With S c4 With switch SW7 turned on and switch SW8 turned off, the current source circuit 213 can begin charging capacitor C2 to generate a ramp signal S. rd The mode switching circuit 150 can output a ramp signal S. rd For the ramp signal S ra .like Figure 3B As shown, unlike the ramp signal S rb The start time (e.g., time T0), the ramp signal S ra The start time is time T1 and can be determined by the ramp signal S. rb and error signal S EB The comparison results determine this. Similarly, the ramp signal S rb The slope during the period between time T0 and time T2 is m (m is a positive number), and the ramp signal S ra The slope during the period between time T1 and time T2 is also m.

[0044] At time T2, comparator circuit 203 confirms the error signal S. EA Equal to the ramp signal S ra It outputs a decision signal S with a logic value of 0. DA . Respond to this decision signal S DA The energy distribution logic circuit 130 generates multiple switching signals S2 and S3 with a first preset level and multiple switching signals S1 and S4 with a second preset level. As a result, switches SW2 and SW3 are turned on to form the first discharge path of inductor L, while switches SW1 and SW4 are not turned on.

[0045] On the other hand, in response to this decision signal S DA The energy distribution logic circuit 130 further generates multiple corresponding control signals S. c1 ~S c4 Thus, when the error signal S EAEqual to the ramp signal S ra At that time, the ramp generator circuit 140 can reduce the ramp signal S. ra With ramp signal S rb The level. Specifically, in response to multiple control signals S c1 ~S c4 Switches SW6 and SW8 are conducting, while switches SW5 and SW7 are not conducting. Thus, capacitor C1 can discharge via current source circuit 212, initiating the reduction of the ramp signal S. rc (Its output is the ramp signal S) rb The level of the ramp signal S. Similarly, capacitor C2 can discharge via current source circuit 214 to begin reducing the ramp signal S. rd (Its output is the ramp signal S) ra The level of ).

[0046] During the period between time T3 and time T4, comparator circuit 204 confirms the error signal S. EB Greater than the ramp signal S rb It outputs a decision signal S with a logic value of 1. DB . Respond to this decision signal S DB The energy distribution logic circuit 130 generates multiple switching signals S2 and S4 with a first preset level and multiple switching signals S1 and S3 with a second preset level. As a result, switches SW2 and SW4 are turned on to form a second discharge path for inductor L, while switches SW1 and SW3 are turned off.

[0047] In this example, the ramp signal S rb The start time (e.g., time T0) is different from the ramp signal S. ra The start time (e.g., time T1), and the ramp signal S rb The end time (e.g., time T4) is different from the ramp signal S. ra The end time (e.g., time T2). Similar to... Figure 3A The detection circuit system 120 detects the slope signal S at different times. ra With ramp signal S rb Generate multiple corresponding decision signals S DA With S DB .

[0048] Figure 4 A flowchart of a power conversion method 400 is provided according to some embodiments of this invention. In some embodiments, the power conversion method 400 may be (but is not limited to) [the following methods]. Figure 1 The power converter device 100 is executed.

[0049] At operation S410, the plurality of charging paths and the plurality of discharging paths of the inductor are switched according to a plurality of switching signals to generate a plurality of output voltages. At operation S420, a plurality of error signals are generated according to the plurality of output voltages and a plurality of reference voltages, and the plurality of error signals are respectively compared with a plurality of ramp signals to generate a plurality of decision signals. At operation S430, the plurality of switching signals and a plurality of control signals are generated according to the plurality of decision signals. At operation S440, the plurality of ramp signals are generated according to the plurality of control signals, wherein a start time of each of the plurality of ramp signals is different from each other.

[0050] The above operations can refer to the foregoing embodiments, and thus will not be repeated. The operations of the power conversion method 400 are merely examples, and are not limited to the order in the examples. Without departing from the operation manner and scope of the embodiments, various operations in the power conversion method 400 can be appropriately added, replaced, omitted, or performed in different order (for example, simultaneously or partially simultaneously).

[0051] In summary, the power converter device and the power conversion method in some embodiments can detect different output voltages at different times. In this way, the plurality of output voltages can be adjusted without summing the plurality of error signals, so as to be suitable for a low-voltage environment and improve the interactive regulation rate of the converter circuit.

[0052] Although the embodiments are described above, the embodiments are not intended to limit the present application. Those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, and such changes can all fall within the scope of the patent protection sought by the present application. In other words, the scope of the patent protection of the present application shall be subject to the claims of the present application.

[0053]

Symbol Description

[0054] 100: power converter device

[0055] 110: converter circuit

[0056] 120: detection circuit system

[0057] 130: energy distribution logic circuit

[0058] 140: ramp generator circuit

[0059] 150: mode switching circuit

[0060] 201, 202: error amplifier circuit

[0061] 203, 204: comparator circuit

[0062] 211-214: current source circuit

[0063] 400: Power conversion method

[0064] C1-C2: Capacitance

[0065] i L : Current

[0066] L: Inductance

[0067] N1-N4: Switching point

[0068] S1-S4: Switching signal

[0069] S410, S420, S430, S440: Operation

[0070] S c1 -S c4 : Control signal

[0071] S DA , S DB : Decision signal

[0072] S EA , S EB : Error signal

[0073] S M : Mode signal

[0074] S ra -S rd : Ramp signal

[0075] SW1-SW8: Switch

[0076] T0-T4: Time

[0077] VDD: Voltage

[0078] V IN : Input signal

[0079] V OA , V OB : Output voltage

[0080] V REFA , V REFB : Reference voltage

Claims

1. A power converter apparatus, comprising: a converter circuit to selectively switch a plurality of charging paths and a plurality of discharging paths of an inductor according to a plurality of switching signals to generate a plurality of output voltages; a detection circuitry to generate a plurality of error signals according to the output voltages and a plurality of reference voltages, and to compare the error signals with a plurality of ramp signals to generate a plurality of decision signals; an energy distribution logic circuit to generate the switching signals and a plurality of control signals according to the decision signals; and a ramp generator circuit to generate the ramp signals according to the control signals, wherein a start time of each of the ramp signals is different from one another, wherein the ramp generator circuit is to decrease a level of the ramp signals when a corresponding one of the ramp signals is equal to a corresponding one of the error signals.

2. The power converter apparatus of claim 1, wherein the detection circuitry is to generate the decision signals without summing the error signals.

3. The power converter apparatus of claim 1, wherein the ramp signals include a first ramp signal and a second ramp signal, the start time of the second ramp signal is determined based on a comparison result of a corresponding one of the error signals and the first ramp signal.

4. The power converter apparatus of claim 1, wherein a positive slope of a first one of the ramp signals is identical to a positive slope of a second one of the ramp signals.

5. The power converter apparatus of claim 1, wherein an end time of each of the ramp signals is different from one another.

6. The power converter apparatus of claim 1, wherein the detection circuitry includes: a first error amplifier circuit to generate a first one of the error signals according to a first one of the output voltages and a first one of the reference voltages; a second error amplifier circuit to generate a second one of the error signals according to a second one of the output voltages and a second one of the reference voltages; a first comparator circuit to compare the first error signal with a first one of the ramp signals to generate a first one of the decision signals; and a second comparator circuit to compare the second error signal with a second one of the ramp signals to generate a second one of the decision signals.

7. The power converter apparatus of claim 1, further comprising: a mode switching circuit to transmit a third ramp signal as one of a first one of the ramp signals and a second one of the ramp signals, and to transmit a fourth ramp signal as another one of the first one of the ramp signals and the second one of the ramp signals according to a mode signal, wherein the ramp generator circuit is to generate the third ramp signal and the fourth ramp signal according to the control signals to be output as the first one of the ramp signals and the second one of the ramp signals via the mode switching circuit.

8. The power converter apparatus of claim 1, wherein the ramp generator circuit includes: a first capacitor; ​ a plurality of first switches for controlling the first capacitor according to a plurality of first signals of the control signals to generate a first ramp signal of the ramp signals; a second capacitor; and a plurality of second switches for controlling the second capacitor according to a plurality of second signals of the control signals to generate a second ramp signal of the ramp signals.

9. A power conversion method, comprising: switching a plurality of charging paths and a plurality of discharging paths of an inductor according to a plurality of switching signals to generate a plurality of output voltages; generating a plurality of error signals according to the output voltages and a plurality of reference voltages, and comparing the error signals with a plurality of ramp signals respectively to generate a plurality of decision signals; generating the switching signals and a plurality of control signals according to the decision signals; and generating the ramp signals according to the control signals, wherein a start time of each of the ramp signals is different from each other, wherein a level of the ramp signals is decreased when a corresponding ramp signal of the ramp signals is equal to a corresponding error signal of the error signals.

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