Logic control circuits for DC-DC converters, and DC-DC converters

Abstract

Embodiments of this disclosure provide a logic control circuit for a DC-DC converter and a DC-DC converter. The DC-DC converter includes a bootstrap capacitor, a power transistor, and a freewheeling transistor. A first terminal of the bootstrap capacitor is coupled to a first terminal of the power transistor. A second terminal of the bootstrap capacitor is coupled to a bootstrap node. The logic control circuit includes a trigger circuit, a forced turn-off time control circuit, and a reset circuit. The trigger circuit is configured to generate a trigger signal based on a PWM signal from the DC-DC converter and a negative inductor current indication signal. The forced turn-off time control circuit is configured to generate a freewheeling transistor forced turn-off signal based on the trigger signal. During the period when the freewheeling transistor forced turn-off signal is at an active level, the freewheeling transistor is forcibly turned off. The reset circuit is configured to generate a reset signal based on the voltage difference between the bootstrap node and the first terminal of the power transistor, a reference voltage, and the freewheeling transistor forced turn-off signal. The reset signal is provided to the trigger circuit to reset the trigger signal to an inactive level.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to logic control circuitry for a DC-DC converter, and to a DC-DC converter. Background Technology

[0002] DC-DC converters are commonly used in various electronic devices to convert DC voltages. DC-DC converters include buck converters (BUCK) and boost converters (BOOST). A buck converter converts a higher DC voltage to a lower DC voltage. A boost converter converts a lower DC voltage to a higher DC voltage. In a buck converter, the drain of the power transistor (upper MOSFET) is coupled to the input voltage. The gate of the power transistor is supplied with a power transistor turn-on control signal. The power transistor is turned on while the power transistor turn-on control signal is active. In BUCK applications with a wide input / output range, if the input voltage is too high, causing the gate-source voltage of the power transistor to fall below the threshold voltage, the power transistor may be falsely turned off. To prevent the power transistor from turning off due to excessive input voltage, a bootstrap capacitor is typically used to maintain the power transistor's conduction. The first terminal of the bootstrap capacitor is coupled to the source of the power transistor. The second terminal of the bootstrap capacitor is coupled to the bootstrap node. While the power transistor turn-on control signal is active, the voltage at the power transistor's gate is equal to the voltage at the bootstrap node. By maintaining the voltage difference across the bootstrap capacitor, it can be ensured that the power transistor can conduct normally while the power transistor turn-on control signal is at an effective level, and will not be turned off due to excessively high input voltage. Summary of the Invention

[0003] The embodiments described herein provide a logic control circuit for a DC-DC converter, and a DC-DC converter.

[0004] According to a first aspect of this disclosure, a logic control circuit for a DC-DC converter is provided. The DC-DC converter includes a bootstrap capacitor, a power transistor, and a freewheeling transistor. A first terminal of the bootstrap capacitor is coupled to a first terminal of the power transistor. A second terminal of the bootstrap capacitor is coupled to a bootstrap node. The logic control circuit includes a trigger circuit, a forced turn-off time control circuit, and a reset circuit. The trigger circuit is configured to generate a trigger signal based on a PWM signal from the DC-DC converter and a negative inductor current indication signal. The forced turn-off time control circuit is configured to generate a freewheeling transistor forced turn-off signal based on the trigger signal. During the period when the freewheeling transistor forced turn-off signal is at an active level, the freewheeling transistor is forcibly turned off. The reset circuit is configured to generate a reset signal based on the voltage difference between the bootstrap node and the first terminal of the power transistor, a reference voltage from a reference voltage terminal, and the freewheeling transistor forced turn-off signal. The reset signal is provided to the trigger circuit to reset the trigger signal to an inactive level.

[0005] In some embodiments of this disclosure, the time period during which the freewheeling diode forced turn-off signal is at an active level is shorter than the time period during which the PWM signal is at an inactive level.

[0006] In some embodiments of this disclosure, the length of the time during which the freewheeling diode forced turn-off signal is at an effective level is preset.

[0007] In some embodiments of this disclosure, the trigger circuit includes a first inverter and a D flip-flop. The input of the first inverter is provided with a PWM signal. The output of the first inverter is coupled to the data input of the D flip-flop. The clock signal input of the D flip-flop is provided with a negative inductor current indication signal. The output of the D flip-flop is coupled to the input of a forced turn-off time control circuit. A trigger signal is output from the output of the D flip-flop. The reset terminal of the D flip-flop is coupled to the output of a reset circuit.

[0008] In some embodiments of this disclosure, the forced shutdown time control circuit includes a first monostable multivibrator. The input of the first monostable multivibrator is coupled to the output of the trigger circuit. The output of the first monostable multivibrator is coupled to the input of the reset circuit.

[0009] In some embodiments of this disclosure, the effective level of the freewheeling diode forced shutdown signal is a high level.

[0010] In some embodiments of this disclosure, the reset circuit includes: a second inverter, a second monostable multivibrator, a third inverter, a voltage comparator, a subtractor, and a first AND gate. The input of the second inverter is coupled to the output of a forced turn-off time control circuit. The output of the second inverter is coupled to the input of the second monostable multivibrator. The output of the second monostable multivibrator is coupled to the input of the third inverter. The output of the third inverter is coupled to the first input of the first AND gate. The first input of the subtractor is coupled to a bootstrap node. The second input of the subtractor is coupled to the first terminal of a power transistor. The output of the subtractor is coupled to the first input of the voltage comparator. The second input of the voltage comparator is coupled to a reference voltage terminal. The output of the voltage comparator is coupled to the second input of the first AND gate. The output of the first AND gate is coupled to the output of the reset circuit. The second monostable multivibrator is a rising-edge triggered monostable multivibrator. The effective level of the output signal of the second monostable multivibrator is high.

[0011] In some embodiments of this disclosure, the reset circuit includes: a second monostable multivibrator, a third inverter, a voltage comparator, a subtractor, and a first AND gate. The input of the second monostable multivibrator is coupled to the output of a forced turn-off time control circuit. The output of the second monostable multivibrator is coupled to the input of the third inverter. The output of the third inverter is coupled to the first input of the first AND gate. The first input of the subtractor is coupled to a bootstrap node. The second input of the subtractor is coupled to the first terminal of a power transistor. The output of the subtractor is coupled to the first input of the voltage comparator. The second input of the voltage comparator is coupled to a reference voltage terminal. The output of the voltage comparator is coupled to the second input of the first AND gate. The output of the first AND gate is coupled to the output of the reset circuit. The second monostable multivibrator is a falling-edge triggered monostable multivibrator. The effective level of the output signal of the second monostable multivibrator is high.

[0012] In some embodiments of this disclosure, the reset circuit includes: a second monostable multivibrator, a voltage comparator, a subtractor, and a first AND gate. The input of the second monostable multivibrator is coupled to the output of a forced turn-off time control circuit. The output of the second monostable multivibrator is coupled to the first input of the first AND gate. The first input of the subtractor is coupled to a bootstrap node. The second input of the subtractor is coupled to the first terminal of a power transistor. The output of the subtractor is coupled to the first input of the voltage comparator. The second input of the voltage comparator is coupled to a reference voltage terminal. The output of the voltage comparator is coupled to the second input of the first AND gate. The output of the first AND gate is coupled to the output of the reset circuit. The second monostable multivibrator is a falling-edge triggered monostable multivibrator, and the effective level of the output signal of the second monostable multivibrator is low.

[0013] According to a second aspect of this disclosure, a logic control circuit for a DC-DC converter is provided. The DC-DC converter includes a bootstrap capacitor, a power transistor, and a freewheeling transistor. A first terminal of the bootstrap capacitor is coupled to a first terminal of the power transistor. A second terminal of the bootstrap capacitor is coupled to a bootstrap node. The logic control circuit includes: a first inverter, a D flip-flop, a first monostable multivibrator, a second inverter, a second monostable multivibrator, a third inverter, a voltage comparator, a subtractor, and a first AND gate. The input of the first inverter is provided with a PWM signal for the DC-DC converter. The output of the first inverter is coupled to the data input of the D flip-flop. The clock signal input of the D flip-flop is provided with a negative inductor current indication signal for the DC-DC converter. The output of the D flip-flop is coupled to the input of the first monostable multivibrator. The reset terminal of the D flip-flop is coupled to the output of the first AND gate. The output of the first monostable multivibrator is coupled to the input of the second inverter. The output of the second inverter is coupled to the input of the second monostable multivibrator. The output of the second monostable multivibrator is coupled to the input of the third inverter. The output of the third inverter is coupled to the first input of the first AND gate. The first input of the subtractor is coupled to the bootstrap node. The second input of the subtractor is coupled to the first terminal of the power transistor. The output of the subtractor is coupled to the first input of the voltage comparator. The second input of the voltage comparator is coupled to the reference voltage terminal. The output of the voltage comparator is coupled to the second input of the first AND gate. The effective level of the output signal of the first monostable multivibrator is high. During the period when the output signal of the first monostable multivibrator is at an effective level, the freewheeling diode is forcibly turned off. The second monostable multivibrator is a rising-edge triggered monostable multivibrator. The effective level of the output signal of the second monostable multivibrator is high.

[0014] According to a third aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes: a bootstrap capacitor, a power transistor, a freewheeling diode, and logic control circuitry according to a first or second aspect of this disclosure. A first terminal of the bootstrap capacitor is coupled to a first terminal of the power transistor. A second terminal of the bootstrap capacitor is coupled to a bootstrap node.

[0015] In some embodiments of this disclosure, the DC-DC converter is a buck converter. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0017] Figure 1 This is an exemplary circuit diagram of a part of a DC-DC converter;

[0018] Figure 2 An exemplary circuit diagram is a part of a DC-DC converter according to an embodiment of the present disclosure;

[0019] Figure 3 This is a schematic block diagram of a logic control circuit according to an embodiment of the present disclosure;

[0020] Figure 4 This is an exemplary circuit diagram of a logic control circuit according to an embodiment of the present disclosure;

[0021] Figure 5 This is another exemplary circuit diagram of a logic control circuit according to embodiments of the present disclosure; and

[0022] Figure 6 This is yet another exemplary circuit diagram of a logic control circuit according to an embodiment of the present disclosure.

[0023] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0026] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0027] Figure 1 Partial structure of a buck DC-DC converter 100 (BUCK circuit) including a bootstrap capacitor C1 is shown. The bootstrap capacitor C1 is connected to the BST point (bootstrap node) and the SW point (the first terminal of the power transistor HS (upper transistor)). A pulse width modulation (PWM) signal is inverted via an inverter NG to generate a pulse width modulation inverted signal PWM_B (hereinafter simply referred to as the PWM_B signal). The PWM_B signal and the freewheeling diode turn-on control signal LG are input together to a first NOR gate NOR1 to generate a power transistor turn-on signal HGP. The power transistor turn-on signal HGP is inverted via an inverter composed of transistors M1 and M2 and another inverter composed of transistors M3 and M4 to generate a power transistor turn-on control signal HG. The power transistor turn-on control signal HG controls the on and off states of the power transistor HS. The PWM signal and the power transistor turn-on control signal HG are input together to a second NOR gate NOR2 to generate a freewheeling diode turn-on signal LGP. The freewheeling diode turn-on signal LGP is used by an inverter composed of transistors M5 and M6, and another inverter composed of transistors M7 and M8 to generate the freewheeling diode turn-on control signal LG. The freewheeling diode turn-on control signal LG can control the turn-on and turn-off of the freewheeling diode LS (lower diode).

[0028] When the freewheeling transistor LS is turned on, the bootstrap switch MB is also turned on. The voltage at point SW is close to 0V, and the LDO (not shown) built into the BUCK circuit can output the supply voltage VDD (e.g., 5V) to charge the bootstrap capacitor C1 (e.g., 100nF) until the voltage at point BST minus the voltage at point SW equals the supply voltage VDD, after which charging stops.

[0029] To ensure the power transistor HS can conduct normally, the PWM signal can be pulled low when the voltage at point BST minus the voltage at point SW is less than a first threshold (e.g., 2.6V). Figure 1 (The corresponding control circuit is not shown in the diagram) to turn off the power transistor HS. While ensuring that the power transistor HS is turned off, the freewheeling transistor LS is turned on, and the bootstrap capacitor C1 is charged with the power supply voltage VDD until the voltage at point BST minus the voltage at point SW is greater than the second threshold (e.g., 2.8V). The second threshold is higher than the first threshold.

[0030] The inventors of this application discovered that, with the preset output voltage Vout of the DC-DC converter 100 being 5V, the output capacitor Cout may have a pre-bias voltage of 4.9V before the DC-DC converter 100 is enabled. Point SW is connected to the output voltage terminal Vout via inductor L, therefore the initial voltage of point SW is 4.9V. Point BST is charged by the power supply voltage VDD (5V), therefore the voltage of point BST can only be raised to a maximum of 5V. Thus, the voltage difference between point BST and point SW can only reach a maximum of 0.1V. When the DC-DC converter 100 is enabled, the freewheeling transistor LS is typically turned on first to charge the bootstrap capacitor C1. When the freewheeling transistor LS is turned on for the first time, point SW is pulled to 0V, and the voltage difference between point BST and point SW begins to rise from 0.1V to 5V. Due to the limited charging capacity, it takes at least 2μs for the voltage difference between point BST and point SW to rise from 0.1V to the second threshold (e.g., 2.8V). During this period, the inductor current flowing through inductor L decreases from 0A at a fixed slope. If the inductance value of inductor L is relatively small, the inductor current will drop to negative tens of amperes, thereby damaging the DC-DC converter 100.

[0031] To avoid the inductor current dropping to negative tens of amperes in the initial stage after the DC-DC converter is enabled, embodiments of this disclosure propose a DC-DC converter. Figure 2 An exemplary circuit diagram showing a portion of a DC-DC converter 200 according to an embodiment of the present disclosure is shown. Figure 2 Examples in Figure 1 Based on the example, a logic control circuit 210 is added. The logic control circuit 210 can intermittently turn on the freewheeling transistor LS during the initial phase after the DC-DC converter 200 is enabled, while intermittently charging the bootstrap capacitor C1 using the supply voltage VDD, to prevent the inductor current from becoming too negative. For example, the freewheeling transistor LS is turned off when the inductor current drops to a preset value (e.g., -4A), so that the inductor current drops to at least that preset value and does not become too negative. Figure 2 In the example, the logic control circuit 210 may be provided with a PWM signal, a negative inductor current indication signal NOCL, and the voltage difference (V) between the bootstrap node BST and the first terminal of the power transistor HS. BST -V SW The logic control circuit 210 can determine the reference voltage Vref based on the PWM signal, the negative inductor current indication signal NOCL, and the voltage difference (V) between the bootstrap node BST and the first terminal of the power transistor HS. BST -V SWThe DC-DC converter 200 generates a forced turn-off signal DR for the freewheeling diode using a reference voltage Vref. The forced turn-off signal DR and the PWM signal are input to an OR gate OR. When the forced turn-off signal DR is active (high level), the OR gate outputs a high level, causing the freewheeling diode on signal LGP output by the second NOR gate NOR2 to be low. Therefore, the freewheeling diode on control signal LG is low, thus forcibly turning off the freewheeling diode LS. When the forced turn-off signal DR is inactive (low level), the output of the OR gate OR follows the PWM signal; therefore, the DC-DC converter 200 can operate normally.

[0032] Figure 3 A schematic block diagram of a logic control circuit 310 according to an embodiment of the present disclosure is shown. The logic control circuit 310 may include a trigger circuit 311, a forced shutdown time control circuit 312, and a reset circuit 313.

[0033] Trigger circuit 311 may be coupled to reset circuit 313 and forced turn-off time control circuit 312. Trigger circuit 311 may be provided with a PWM signal from the DC-DC converter and a negative inductor current indication signal NOCL. The PWM signal is used to control the power transistor HS and freewheeling transistor LS to conduct alternately. The negative inductor current indication signal NOCL is used to indicate whether the inductor current flowing through inductor L is lower than a preset negative current value. In some embodiments of this disclosure, when the inductor current drops to, for example, -4A, the negative inductor current indication signal NOCL flips from an invalid level (low level) to an active level (high level). Trigger circuit 311 may be configured to generate trigger signal TR based on the PWM signal from the DC-DC converter and the negative inductor current indication signal NOCL. In some embodiments of this disclosure, the trigger signal TR flips to an active level (high level) when the PWM signal is at an invalid level (low level) and the negative inductor current indication signal NOCL flips to an active level (high level). When the trigger circuit 311 receives a reset signal at an active level (low level) from the reset circuit 313, the trigger signal TR can be reset to an inactive level (low level).

[0034] The input of the forced turn-off time control circuit 312 can be coupled to the output of the trigger circuit 311. The output of the forced turn-off time control circuit 312 can be coupled to the input of the reset circuit 313. When the trigger signal TR flips to an active level, it indicates that the freewheeling transistor LS needs to be forcibly turned off for a period of time. The forced turn-off time control circuit 312 can be used to control the length of this period. The forced turn-off time control circuit 312 can be configured to generate a freewheeling transistor forced turn-off signal DR based on the trigger signal TR. During the period when the freewheeling transistor forced turn-off signal DR is active, the freewheeling transistor LS is forcibly turned off. In some embodiments of this disclosure, the period when the freewheeling transistor forced turn-off signal DR is active is shorter than the period when the PWM signal is inactive. This allows the freewheeling transistor LS to be intermittently turned on and off during the period when the PWM signal is inactive. In some embodiments of this disclosure, the length of the period when the freewheeling transistor forced turn-off signal DR is active is preset. In some embodiments of this disclosure, the length of the period when the freewheeling transistor forced turn-off signal DR is active is 500 ns.

[0035] The input of reset circuit 313 can be coupled to the output of forced turn-off time control circuit 312. The output of reset circuit 313 can be coupled to trigger circuit 311. Reset circuit 313 can be coupled to reference voltage terminal Vref. Reset circuit 313 can also provide the voltage difference (Vf) between bootstrap node BST and the first terminal of power transistor HS. BST -V SW The reset circuit 313 can be configured to respond to the voltage difference (V) between the bootstrap node BST and the first terminal of the power transistor HS. BST -V SW The reference voltage Vref from the reference voltage terminal Vref, and the freewheeling diode forced turn-off signal DR are used to generate the reset signal RESET. The reset signal RESET is provided to the trigger circuit 311 to reset the trigger signal TR to an invalid level. In some embodiments of this disclosure, the voltage difference (Vref) between the bootstrap node BST and the first terminal of the power transistor HS is used to generate the reset signal RESET. BST -V SW When the voltage is below the reference voltage Vref and the freewheeling diode forced turn-off signal DR flips from an invalid level to an active level, the reset signal RESET flips from an invalid level to an active level. The reset signal RESET can remain active for a preset time period, after which it automatically flips to an invalid level. The voltage difference (V) between the bootstrap node BST and the first terminal of the power transistor HS... BST -V SW When the voltage is higher than or equal to the reference voltage Vref, the reset signal RESET remains active. In some embodiments of this disclosure, the active level of the reset signal RESET is low.

[0036] The voltage difference (V) between the bootstrap node BST and the first terminal of the power transistor HS BST -V SW When the voltage is higher than or equal to the reference voltage Vref, the reset signal RESET remains active. Therefore, the trigger signal TR remains inactive, so that the freewheeling diode forced turn-off signal DR remains inactive. This ensures that the logic control circuit 310 does not affect the normal operation of the DC-DC converter.

[0037] The voltage difference (V) between the bootstrap node BST and the first terminal of the power transistor HS BST -V SW When the voltage is below the reference voltage Vref, the PWM signal is at an invalid level (low level), and the power transistor HS is off. Whenever the negative inductor current indicator signal NOCL flips to an active level (high level), the trigger signal TR flips to an active level (high level). When the trigger signal TR flips to an active level, the freewheeling diode forced turn-off signal DR flips to an active level (high level), thus forcibly turning off the freewheeling diode LS. The freewheeling diode forced turn-off signal DR flipping to an active level causes the reset signal to flip to an active level (low level), thereby resetting the trigger signal TR to an invalid level (low level). Thus, the freewheeling diode forced turn-off signal DR flips to an invalid level (low level), turning on the freewheeling diode LS. This process repeats, allowing the freewheeling diode LS to be intermittently turned on and off during the initial stage after the DC-DC converter is enabled.

[0038] Figure 4 An exemplary circuit diagram of a logic control circuit 410 according to an embodiment of the present disclosure is shown. The trigger circuit 411 may include a first inverter NG1 and a D flip-flop DT. The input of the first inverter NG1 is provided with a PWM signal. The output of the first inverter NG1 is coupled to the data input D of the D flip-flop DT. The clock signal input CLK of the D flip-flop DT is provided with a negative inductor current indication signal NOCL. The output Q of the D flip-flop DT is coupled to the input of a forced turn-off time control circuit 412. A trigger signal TR is output from the output Q of the D flip-flop DT. The reset terminal RN of the D flip-flop DT is coupled to the output of a reset circuit 413. Figure 4 In the example, the data input D of the D flip-flop DT is set to active high. The clock signal input CLK of the D flip-flop DT is set to active on the rising edge. The reset input RN of the D flip-flop DT is set to active low. In an alternative embodiment, if the data input D of the D flip-flop DT is set to active low, the trigger circuit 411 may not include the first inverter NG1, and the data input D of the D flip-flop DT is directly provided with a PWM signal.

[0039] The forced shutdown time control circuit 412 may include: a first monostable multivibrator. The input of the first monostable multivibrator is coupled to the output of the trigger circuit 411. The output of the first monostable multivibrator is coupled to the input of the reset circuit 413. Figure 4 In the example, the output Q of the D flip-flop DT is a non-inverting output, and the first monostable multivibrator is triggered at the rising edge of the trigger signal TR. Alternatively, when the output of the D flip-flop DT is an inverting output, the first monostable multivibrator is triggered at the falling edge of the trigger signal TR. In some embodiments of this disclosure, the effective level of the freewheeling diode forced turn-off signal DR is a high level.

[0040] The reset circuit 413 may include: a second inverter NG2, a second monostable multivibrator 4131, a third inverter NG3, a voltage comparator COMP, a subtractor SUB, and a first AND gate AND1. The input of the second inverter NG2 is coupled to the output of the forced turn-off time control circuit 412. The output of the second inverter NG2 is coupled to the input of the second monostable multivibrator 4131. The output of the second monostable multivibrator 4131 is coupled to the input of the third inverter NG3. The output of the third inverter NG3 is coupled to the first input of the first AND gate AND1. The first input of the subtractor SUB is coupled to the bootstrap node BST. The second input of the subtractor SUB is coupled to the first terminal (SW point) of the power transistor HS. The output of the subtractor SUB is coupled to the first input of the voltage comparator COMP. The second input of the voltage comparator COMP is coupled to the reference voltage Vref. The output of the voltage comparator COMP is coupled to the second input of the first AND gate AND1. The output of the first AND gate AND1 is coupled to the output of the reset circuit 413. The second monostable multivibrator 4131 is a rising-edge triggered monostable multivibrator. The effective level of the output signal of the second monostable multivibrator 4131 is high. In some embodiments of this disclosure, the duration of the effective level of the output signal of the second monostable multivibrator 4131 is 10 ns.

[0041] Figure 5 Another exemplary circuit diagram of a logic control circuit 510 according to an embodiment of the present disclosure is shown. Figure 5 Examples and Figure 4 The difference in the examples lies in the internal structure of the reset circuit 513. Figure 5In the example, the reset circuit 513 may include: a second monostable multivibrator 5131, a third inverter NG3, a voltage comparator COMP, a subtractor SUB, and a first AND gate AND1. The input of the second monostable multivibrator 5131 is coupled to the output of the forced turn-off time control circuit 412. The output of the second monostable multivibrator 5131 is coupled to the input of the third inverter NG3. The output of the third inverter NG3 is coupled to the first input of the first AND gate AND1. The first input of the subtractor SUB is coupled to the bootstrap node BST. The second input of the subtractor SUB is coupled to the first terminal (SW point) of the power transistor HS. The output of the subtractor SUB is coupled to the first input of the voltage comparator COMP. The second input of the voltage comparator COMP is coupled to the reference voltage Vref. The output of the voltage comparator COMP is coupled to the second input of the first AND gate AND1. The output of the first AND gate AND1 is coupled to the output of the reset circuit 513. The second monostable multivibrator 5131 is a falling-edge triggered monostable multivibrator. The effective level of the output signal of the second monostable multivibrator 5131 is high.

[0042] Figure 6 Another exemplary circuit diagram of a logic control circuit 610 according to an embodiment of the present disclosure is shown. Figure 6 Examples and Figure 4 The difference in the example lies in the internal structure of the reset circuit 613. Figure 6 In the example, the reset circuit 613 includes: a second monostable multivibrator 6131, a voltage comparator COMP, a subtractor SUB, and a first AND gate AND1. The input of the second monostable multivibrator 6131 is coupled to the output of the forced turn-off time control circuit 412. The output of the second monostable multivibrator 6131 is coupled to the first input of the first AND gate AND1. The first input of the subtractor SUB is coupled to the bootstrap node BST. The second input of the subtractor SUB is coupled to the first terminal (SW point) of the power transistor HS. The output of the subtractor SUB is coupled to the first input of the voltage comparator COMP. The second input of the voltage comparator COMP is coupled to the reference voltage Vref. The output of the voltage comparator COMP is coupled to the second input of the first AND gate AND1. The output of the first AND gate AND1 is coupled to the output of the reset circuit 613. The second monostable multivibrator 6131 is a falling-edge triggered monostable multivibrator, and the effective level of the output signal of the second monostable multivibrator 6131 is low.

[0043] exist Figures 4 to 6 In the example, the first input of the voltage comparator COMP is the inverting input. The second input of the voltage comparator COMP is the non-inverting input.

[0044] The following is based on Figure 4The operation of the logic control circuit 410 according to an embodiment of the present disclosure will be illustrated by taking the structure as an example.

[0045] A voltage comparator COMP can be used to compare the voltage difference (V) between point BST and point SW. BST -V SW The voltage comparator COMP is a hysteresis voltage comparator, and its magnitude is related to the reference voltage Vref. BST -V SW The signal BST_HB output by the voltage comparator COMP is high when the voltage is less than a first value (i.e., a first threshold, e.g., 2.6V) of the reference voltage Vref. BST -V SW The signal BST_HB output by the voltage comparator COMP is at a low level when the second value (i.e., the second threshold, for example, 2.8V) of the reference voltage Vref is greater than or equal to the first threshold.

[0046] When signal BST_HB is low, the PWM signal is unaffected, and power transistor HS can conduct normally. The first AND gate AND1 outputs a low level, therefore, the D flip-flop DT is reset. The trigger signal TR output by D flip-flop DT is low. The freewheeling diode forced turn-off signal DR output by the first monostable multivibrator is low. The freewheeling diode LS can conduct and cut off normally. Under these conditions, the DC-DC converter can operate normally.

[0047] When the signal BST_HB is high, the PWM signal is pulled low, causing the power transistor HS to turn off and the freewheeling transistor LS to turn on. During the conduction of the freewheeling transistor LS, the inductor current is monitored. When the negative inductor current indicator signal NOCL flips high, the trigger signal TR output from the D flip-flop DT flips high, and the freewheeling transistor forced turn-off signal DR output from the first monostable multivibrator flips high, thus turning off the freewheeling transistor LS and stopping the switching operation of the DC-DC converter. After, for example, 500ns, the freewheeling transistor forced turn-off signal DR flips low, the freewheeling transistor LS turns on again, the output signal DRB of the second inverter NG2 flips high, and the output signal RST of the second monostable multivibrator 4131 flips high. The output signal RSTB of the third inverter NG3 flips low. The reset signal RESET output from the first AND gate AND1 flips low. The D flip-flop DT is reset, and the trigger signal TR flips low. After, for example, 10 ns, the output signal RST of the second monostable multivibrator 4131 toggles low, and the output signal RSTB of the third inverter NG3 toggles high. The reset signal RESET from the first AND gate AND1 toggles high. The D flip-flop DT is enabled again. The above process is repeated when the rising edge of the negative inductor current indication signal NOCL arrives, intermittently turning on the freewheeling transistor LS, while intermittently charging the bootstrap capacitor C1 with the power supply voltage VDD to prevent the inductor current from becoming too negative.

[0048] In summary, the logic control circuit according to the embodiments of this disclosure intermittently turns the freewheeling diode on and off in the initial stage after the DC-DC converter is enabled, while intermittently charging the bootstrap capacitor with the power supply voltage, which can prevent the inductor current from being too negative and thus avoid damage to the DC-DC converter.

[0049] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0050] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0051] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A logic control circuit for a DC-DC converter, the DC-DC converter including a bootstrap capacitor, a power transistor, and a freewheeling transistor, a first terminal of the bootstrap capacitor being coupled to a first terminal of the power transistor, and a second terminal of the bootstrap capacitor being coupled to a bootstrap node, the logic control circuit comprising: Trigger circuit, forced shutdown time control circuit, and reset circuit. The trigger circuit is configured to generate a trigger signal based on the PWM signal of the DC-DC converter and the negative inductor current indication signal; The forced shutdown time control circuit is configured to generate a freewheeling diode forced shutdown signal according to the trigger signal, wherein the freewheeling diode is forcibly shut off during the time period when the freewheeling diode forced shutdown signal is at an effective level. The reset circuit is configured to generate a reset signal based on the voltage difference between the bootstrap node and the first terminal of the power transistor, a reference voltage from the reference voltage terminal, and the forced turn-off signal of the freewheeling transistor. The reset signal is provided to the trigger circuit to reset the trigger signal to an invalid level. The input of the reset circuit is coupled to the output of the forced turn-off time control circuit, the output of the reset circuit is coupled to the trigger circuit, the reset circuit is coupled to the reference voltage terminal, and the reset circuit is also provided with the voltage difference between the bootstrap node and the first terminal of the power transistor.

2. The logic control circuit according to claim 1, wherein, The time period during which the freewheeling diode forced turn-off signal is at an active level is shorter than the time period during which the PWM signal is at an inactive level.

3. The logic control circuit according to claim 1, wherein, The trigger circuit includes: a first inverter and a D flip-flop. The input terminal of the first inverter is provided with the PWM signal, and the output terminal of the first inverter is coupled to the data input terminal of the D flip-flop. The clock signal input terminal of the D flip-flop is provided with the negative inductor current indication signal, the output terminal of the D flip-flop is coupled to the input terminal of the forced turn-off time control circuit, the trigger signal is output from the output terminal of the D flip-flop, and the reset terminal of the D flip-flop is coupled to the output terminal of the reset circuit.

4. The logic control circuit according to claim 1, wherein, The forced shutdown time control circuit includes: a first monostable trigger. The input terminal of the first monostable multivibrator is coupled to the output terminal of the trigger circuit, and the output terminal of the first monostable multivibrator is coupled to the input terminal of the reset circuit.

5. The logic control circuit according to any one of claims 1 to 4, wherein, The effective level of the forced shutdown signal for the freewheeling diode is a high level.

6. The logic control circuit according to any one of claims 1 to 4, wherein, The reset circuit includes: a second inverter, a second monostable multivibrator, a third inverter, a voltage comparator, a subtractor, and a first AND gate. The input terminal of the second inverter is coupled to the output terminal of the forced turn-off time control circuit, and the output terminal of the second inverter is coupled to the input terminal of the second monostable multivibrator. The output of the second monostable multivibrator is coupled to the input of the third inverter; The output of the third inverter is coupled to the first input of the first AND gate; The first input terminal of the subtractor is coupled to the bootstrap node, the second input terminal of the subtractor is coupled to the first terminal of the power transistor, and the output terminal of the subtractor is coupled to the first input terminal of the voltage comparator. The second input terminal of the voltage comparator is coupled to the reference voltage terminal, and the output terminal of the voltage comparator is coupled to the second input terminal of the first AND gate; The output of the first AND gate is coupled to the output of the reset circuit; The second monostable multivibrator is a rising-edge triggered monostable multivibrator, and the effective level of the output signal of the second monostable multivibrator is a high level.

7. The logic control circuit according to any one of claims 1 to 4, wherein, The reset circuit includes: a second monostable multivibrator, a third inverter, a voltage comparator, a subtractor, and a first AND gate. The input terminal of the second monostable multivibrator is coupled to the output terminal of the forced turn-off time control circuit, and the output terminal of the second monostable multivibrator is coupled to the input terminal of the third inverter. The output of the third inverter is coupled to the first input of the first AND gate; The first input terminal of the subtractor is coupled to the bootstrap node, the second input terminal of the subtractor is coupled to the first terminal of the power transistor, and the output terminal of the subtractor is coupled to the first input terminal of the voltage comparator. The second input terminal of the voltage comparator is coupled to the reference voltage terminal, and the output terminal of the voltage comparator is coupled to the second input terminal of the first AND gate; The output of the first AND gate is coupled to the output of the reset circuit; The second monostable multivibrator is a falling-edge triggered monostable multivibrator, and the effective level of the output signal of the second monostable multivibrator is a high level.

8. The logic control circuit according to any one of claims 1 to 4, wherein, The reset circuit includes: a second monostable multivibrator, a voltage comparator, a subtractor, and a first AND gate. Wherein, the input terminal of the second monostable multivibrator is coupled to the output terminal of the forced turn-off time control circuit, and the output terminal of the second monostable multivibrator is coupled to the first input terminal of the first AND gate; The first input terminal of the subtractor is coupled to the bootstrap node, the second input terminal of the subtractor is coupled to the first terminal of the power transistor, and the output terminal of the subtractor is coupled to the first input terminal of the voltage comparator. The second input terminal of the voltage comparator is coupled to the reference voltage terminal, and the output terminal of the voltage comparator is coupled to the second input terminal of the first AND gate; The output of the first AND gate is coupled to the output of the reset circuit; The second monostable multivibrator is a falling-edge triggered monostable multivibrator, and the effective level of the output signal of the second monostable multivibrator is low.

9. A logic control circuit for a DC-DC converter, the DC-DC converter including a bootstrap capacitor, a power transistor, and a freewheeling transistor, a first terminal of the bootstrap capacitor being coupled to a first terminal of the power transistor, and a second terminal of the bootstrap capacitor being coupled to a bootstrap node, the logic control circuit comprising: The circuit consists of a first inverter, a D flip-flop, a first monostable multivibrator, a second inverter, a second monostable multivibrator, a third inverter, a voltage comparator, a subtractor, and a first AND gate. The input terminal of the first inverter is provided with the PWM signal of the DC-DC converter, and the output terminal of the first inverter is coupled to the data input terminal of the D flip-flop. The clock signal input of the D flip-flop is provided with the negative inductor current indication signal of the DC-DC converter, the output of the D flip-flop is coupled to the input of the first monostable multivibrator, and the reset terminal of the D flip-flop is coupled to the output of the first AND gate. The output of the first monostable multivibrator is coupled to the input of the second inverter, and the output of the second inverter is coupled to the input of the second monostable multivibrator. The output of the second monostable multivibrator is coupled to the input of the third inverter; The output of the third inverter is coupled to the first input of the first AND gate; The first input terminal of the subtractor is coupled to the bootstrap node, the second input terminal of the subtractor is coupled to the first terminal of the power transistor, and the output terminal of the subtractor is coupled to the first input terminal of the voltage comparator. The second input terminal of the voltage comparator is coupled to the reference voltage terminal, and the output terminal of the voltage comparator is coupled to the second input terminal of the first AND gate; Wherein, the effective level of the output signal of the first monostable multivibrator is high level, and the freewheeling diode is forcibly turned off during the time period when the output signal of the first monostable multivibrator is at the effective level; The second monostable multivibrator is a rising-edge triggered monostable multivibrator, and the effective level of the output signal of the second monostable multivibrator is a high level.

10. A DC-DC converter, comprising: A bootstrap capacitor, a power transistor, a freewheeling transistor, and a logic control circuit according to any one of claims 1 to 9. The first end of the bootstrap capacitor is coupled to the first electrode of the power transistor, and the second end of the bootstrap capacitor is coupled to the bootstrap node.

Images