A three-phase pfc rectifier circuit and control method compatible with boost and buck control

Abstract

A compatible boost and step-down control three-phase PFC rectifier circuit and control method, the circuit includes input filter circuit, power switch circuit, output filter circuit and control circuit, through the implementation of the application, the bridge arm reverse connection MOS replaces the conventional rectifier bridge arm single MOS, the filter inductance is added to the input and output end of the rectifier, so that the circuit has lower starting current and reliable short circuit current suppression capacity; combined with the new control method, the problem that the three-phase PFC rectifier can only be boost control or step-down control in the prior art is solved, so that the rectifier can realize a wider input voltage range, realize high power power factor quality of the power supply; when the bridge arm MOS is turned off, the input and output are isolated, there is no current path, when the upper and lower bridge arms of the same phase are directly connected, the rectifier will not be damaged, has lower starting current and reliable short circuit current suppression capacity.

Description

Technical Field

[0001] This invention relates to a three-phase PFC rectifier circuit and control method compatible with both boost and buck control. Background Technology

[0002] In daily life, numerous nonlinear loads are used, and the resulting harmonics can severely impact power grid quality. Therefore, high-performance three-phase rectifiers are particularly important. Furthermore, the AC output voltage of railway power supplies and generators used in electric aircraft typically varies by 3 to 5 times or even more, creating an urgent need for power converter technology that can adapt to a wide voltage range while also suppressing grid harmonics.

[0003] With the rapid development of semiconductor technology, rectifier technology has also made significant progress. In the field of three-phase rectifiers, three-phase uncontrolled rectifiers and three-phase phase-controlled rectifiers have low grid-side power factors, injecting a large amount of harmonics into the power grid. Three-phase single-switch and three-phase double-switch PFC rectifiers are limited by the fact that three-phase uncontrolled rectifiers can only achieve a certain degree of power factor correction, resulting in a low grid-side power factor. Three-phase three-switch, three-phase six-switch, and three-phase diode-clamped Boost PFC rectifiers can achieve unity power factor on the grid side, but the output voltage can only be greater than the peak value of the input line voltage. Three-phase six-switch Buck PFC rectifiers can achieve unity power factor on the grid side, but the output voltage can only be less than the peak value of the input line voltage. The above circuit topologies can only achieve high power factor regulated output within a narrow range and cannot adapt to applications with a range of 3 to 5 times or even wider variations. Therefore, in some applications with a wide input voltage range and high power factor requirements, existing topologies cannot meet the requirements. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a three-phase PFC rectifier circuit and control method compatible with both boost and buck control.

[0005] The present invention is achieved through the following technical solutions.

[0006] This invention provides a three-phase PFC rectifier circuit compatible with both boost and buck control, comprising an input filter circuit, a power switch circuit, an output filter circuit, and a control circuit.

[0007] The input filter circuit is connected to the power switch circuit, the power switch circuit is connected to the output filter circuit, and the output terminal of the control circuit is connected to the power switch circuit.

[0008] The input filter circuit includes inductors La, Lb, and Lc, capacitors Ca, Cb, and Cc; the power switching circuit includes power MOSFETs Qa1, Qa2, Qa3, Qa4, Qb1, Qb2, Qb3, Qb4, Qc1, Qc2, Qc3, and Qc4; the output filter circuit includes inductor Ldc and capacitor Co.

[0009] One end of the inductor La is connected to the A-phase voltage, and the other end is connected to one end of the capacitor Ca; one end of the inductor Lb is connected to the B-phase voltage, and the other end is connected to one end of the capacitor Cb; one end of the inductor Lc is connected to the C-phase voltage, and the other end is connected to one end of the capacitor Cc; the other ends of the capacitor Ca, the other ends of the capacitor Cb, and the other ends of the capacitor Cc are connected together.

[0010] One end of the inductor Ldc is connected to one end of the capacitor Co, and the other end of the inductor Ldc and the other end of the capacitor Co are respectively connected to the control circuit.

[0011] The drain of power MOSFET Qa1 is connected to the other end of inductor Ldc; the source of power MOSFET Qa1 is connected to the source of power MOSFET Qa2; the drain of power MOSFET Qa2 is connected to the other end of inductor La; and the gate of power MOSFET Qa1 is connected to the gate of power MOSFET Qa2. The drain of power MOSFET Qa3 is connected to the other end of inductor La; the source of power MOSFET Qa3 is connected to the source of power MOSFET Qa4; the drain of power MOSFET Qa4 is connected to the other end of capacitor Co; and the gate of power MOSFET Qa3 is connected to the gate of power MOSFET Qa4. Similarly, the drain of power MOSFET Qb1 is connected to the other end of inductor Ldc; the source of power MOSFET Qb1 is connected to the source of power MOSFET Qb2; the drain of power MOSFET Qb2 is connected to the other end of inductor Lb; and the gate of power MOSFET Qb1 is connected to the gate of power MOSFET Qb2. The drain of power MOSFET Qb3 is connected to the other end of inductor Lb, the source of power MOSFET Qb3 is connected to the source of power MOSFET Qb4, the drain of power MOSFET Qb4 is connected to the other end of capacitor Co, and the gate of power MOSFET Qb3 is connected to the gate of power MOSFET Qb4; the drain of power MOSFET Qc1 is connected to the other end of inductor Ldc, the source of power MOSFET Qc1 is connected to the source of power MOSFET Qc2, the drain of power MOSFET Qc2 is connected to the other end of inductor Lc, and the gate of power MOSFET Qc1 is connected to the gate of power MOSFET Qc2; the drain of power MOSFET Qc3 is connected to the other end of inductor Lc, the source of power MOSFET Qc3 is connected to the source of power MOSFET Qc4, the drain of power MOSFET Qc4 is connected to the other end of capacitor Co, and the gate of power MOSFET Qc3 is connected to the gate of power MOSFET Qc4.

[0012] Furthermore, it also includes an auxiliary power supply, which is connected to the control circuit.

[0013] Furthermore, the other end of the inductor Ldc is connected to an auxiliary power supply.

[0014] Furthermore, the other end of the capacitor Co is connected to an auxiliary power supply.

[0015] Furthermore, it also includes a resistor RL, which is connected in parallel with a capacitor Co.

[0016] Furthermore, the control circuit has a three-phase input voltage signal and a three-phase input current signal at its input terminal, and a power switch circuit at its output terminal.

[0017] A control method for a three-phase PFC rectifier circuit compatible with both boost and buck control, characterized by the following steps:

[0018] Step 1: Determine the numerical relationship between the three-phase input voltage and the DC output voltage setting value Vref of the three-phase PFC rectifier;

[0019] Step 2: Based on the numerical relationships obtained in Step 1, switch between boost control, buck control, and synchronous rectification control operating modes, specifically as follows:

[0020] When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in buck mode;

[0021] When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in boost mode;

[0022] When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in synchronous rectification mode;

[0023] Where Vref is the DC output voltage setting value, Um is the peak line voltage of the rectifier's three-phase input voltage, and ΔU% represents the fluctuation range of the grid voltage.

[0024] Furthermore, the three-phase input voltages have the same amplitude, but their phases differ by 120° sequentially.

[0025] The beneficial effects of this invention are as follows: By implementing this invention, a MOSFET with reverse-connected bridge arms replaces the single MOSFET in a conventional rectifier. Filter inductors are added to both the input and output terminals of the rectifier, giving the circuit lower startup current and reliable short-circuit current suppression capability. Combined with a new control method, it solves the problem that existing three-phase PFC rectifiers can only be controlled by boost or buck converters, enabling the rectifier to achieve a wider input voltage range and high power factor quality. When the bridge arm MOSFET is turned off, the input and output are isolated, eliminating current paths. Even when the upper and lower bridge arms of the same phase are directly connected, the rectifier will not be damaged, resulting in lower startup current and reliable short-circuit current suppression capability. Compared to traditional three-phase Boost PFC or Buck PFC rectifiers, this invention has significant advantages such as simple structure, wide input voltage range, high power factor, simple control, fewer components, and low cost. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the power switch circuit topology of the present invention;

[0027] Figure 2 This is the circuit schematic diagram of the present invention;

[0028] Figure 3 This is a block diagram of the control principle of the present invention;

[0029] Figure 4 This is the equivalent circuit diagram of the circuit topology of the present invention in boost mode in a stationary coordinate system;

[0030] Figure 5 This is the equivalent circuit diagram of the circuit topology of the present invention in the step-down mode in the stationary coordinate system;

[0031] Figure 6 This is the output control logic diagram of the circuit topology of this invention in boost mode in a stationary coordinate system;

[0032] Figure 7 This is the output control logic diagram of the circuit topology of the present invention in the step-down mode in the stationary coordinate system. Detailed Implementation

[0033] The technical solution of the present invention is further described below, but the scope of protection is not limited to what is described.

[0034] like Figures 1-2As shown, this invention provides a three-phase PFC rectifier circuit compatible with both boost and buck control, including an input filter circuit, a power switch circuit, an output filter circuit, and a control circuit. The input filter circuit is connected to the power switch circuit, the power switch circuit is connected to the output filter circuit, and the output terminal of the control circuit is connected to the power switch circuit. The input filter circuit includes inductors La, Lb, and Lc, and capacitor Ca. The circuit includes capacitors Cb and Cc; the power switching circuit includes power MOSFETs Qa1, Qa2, Qa3, Qa4, Qb1, Qb2, Qb3, Qb4, Qc1, Qc2, Qc3, and Qc4; the output filter circuit includes inductor Ldc and capacitor Co; one end of inductor La is connected to the A-phase voltage, and the other end is connected to one end of capacitor Ca; one end of inductor Lb is connected to the B-phase voltage, and the other end is connected to one end of capacitor Cb; one end of inductor Lc is connected to the C-phase voltage, and the other end is connected to one end of capacitor Cc; the other ends of capacitor Ca, capacitor Cb, and capacitor Cc are connected together. One end of inductor Ldc is connected to one end of capacitor Co, and the other ends of inductor Ldc and capacitor Co are respectively connected to the control circuit; the drain of power MOSFET Qa1 is connected to the other end of inductor Ldc, the source of power MOSFET Qa1 is connected to the source of power MOSFET Qa2, the drain of power MOSFET Qa2 is connected to the other end of inductor La, and the gate of power MOSFET Qa1 is connected to the gate of power MOSFET Qa2; the drain of power MOSFET Qa3 is connected to the other end of inductor La, the source of power MOSFET Qa3 is connected to the source of power MOSFET Qa4, the drain of power MOSFET Qa4 is connected to the other end of capacitor Co, and the gate of power MOSFET Qa3 is connected to the gate of power MOSFET Qa4; the drain of power MOSFET Qb1 is connected to the other end of inductor Ldc, and power M... The source of MOSFET Qb1 is connected to the source of power MOSFET Qb2, the drain of power MOSFET Qb2 is connected to the other end of inductor Lb, and the gate of power MOSFET Qb1 is connected to the gate of power MOSFET Qb2. The drain of power MOSFET Qb3 is connected to the other end of inductor Lb, the source of power MOSFET Qb3 is connected to the source of power MOSFET Qb4, the drain of power MOSFET Qb4 is connected to the other end of capacitor Co, and the gate of power MOSFET Qb3 is connected to the gate of power MOSFET Qb4. The drain of power MOSFET Qc1 is connected to the other end of inductor Ldc, the source of power MOSFET Qc1 is connected to the source of power MOSFET Qc2, the drain of power MOSFET Qc2 is connected to the other end of inductor Lc, and the gate of power MOSFET Qc1 is connected to the gate of power MOSFET Qc2.The drain of power MOSFET Qc3 is connected to the other end of inductor Lc; the source of power MOSFET Qc3 is connected to the source of power MOSFET Qc4; the drain of power MOSFET Qc4 is connected to the other end of capacitor Co; and the gate of power MOSFET Qc3 is connected to the gate of power MOSFET Qc4.

[0035] It also includes an auxiliary power supply, which is connected to the control circuit; the other ends of inductor Ldc and capacitor Co are both connected to the auxiliary power supply. It also includes a resistor RL, which is connected in parallel with capacitor Co. The control circuit input terminals receive three-phase input voltage and three-phase input current signals, and the output terminal is connected to a power switching circuit.

[0036] The technical solution adopted in this invention is a three-phase PFC rectifier circuit topology compatible with both boost and buck control. It includes a three-phase AC power supply, an input filter circuit connected to the three-phase AC power supply, an output terminal of the input filter circuit connected to a three-phase rectifier network, an output filter circuit connected to the output terminal of the three-phase rectifier, and a load connected between the positive and negative terminals of the output filter circuit. Its working principle is as follows:

[0037] Figure 1 The power switching circuit of the three-phase rectifier includes six sets of reverse-connected MOSFETs. The drain of power MOSFET Qx1 is connected to the input terminal of the DC-side filter circuit, the source of power MOSFET Qx1 is connected to the source of power MOSFET Qx2, the drain of power MOSFET Qx2 is connected to the output terminal of the AC-side filter circuit, and the gate of power MOSFET Qx1 is connected to the gate of power MOSFET Qx2. The drain of power MOSFET Qx3 is connected to the output terminal of the AC-side filter circuit, the source of power MOSFET Qx3 is connected to the source of power MOSFET Qx4, the drain of power MOSFET Qx4 is connected to the negative terminal of the DC side, and the gate of power MOSFET Qx3 is connected to the gate of power MOSFET Qx4, where x represents a, b, and c. Power MOSFETs Qx1 and Qx2 are switched on and off simultaneously, and the gates of power MOSFETs Qx3 and Qx4 are switched on and off simultaneously. When the gate of the power MOSFET is not driven, power MOSFETs Qx1 and Qx3 can prevent current from flowing from the DC output terminal to the AC input terminal.

[0038] When the three-phase rectifier operates in boost mode, the switching signals of the upper and lower arms of each phase satisfy a complementary logic relationship. To prevent overcurrent problems caused by arm shoot-through, a dead time is set for the drive signals of the switching transistors on the same arm. The drive signal of the three-phase rectifier is obtained by comparing a sinusoidal modulated wave with a triangular carrier wave. At any given time, only the upper arm or the lower arm of each phase is turned on.

[0039] When operating in buck mode, to prevent discontinuous DC inductor current, the three-phase rectifier requires one bridge arm to be directly connected at any given time, that is, to form an inductor current freewheeling circuit through the three bridge arms.

[0040] Figure 2 The circuit topology of this invention is given, where VA, VB, and VC are grid-side phase voltages; ia, ib, and ic are grid-side phase currents; isa, isb, and isc are AC-side currents; inductors La, Lb, and Lc, and capacitors Ca, Cb, and Cc constitute a grid-side LC filter, i.e., an input filter circuit, which filters out high-frequency harmonics on the AC side, making the grid phase current sinusoidal, and acts as an energy storage inductor when the rectifier is boosting; components Qx1 and Qx2 on each half-bridge arm are connected in reverse series, enhancing the reverse blocking capability of the switching transistors; the DC-side inductor Ldc and capacitor Co work together to ensure stable output voltage and current. Vdc is the DC-side output voltage; iLdc is the DC-side inductor current; idc is the DC current; and RL is the load resistance.

[0041] The operating state of the rectifier is determined by the three-phase input voltage on the AC side and the switching states of the rectifier bridge transistors. Therefore, when analyzing the working principle of this rectifier, the switching states of the rectifier bridge transistors must be analyzed first. The control method of this rectifier is implemented according to the following steps:

[0042] Step 1: Determine the numerical relationship between the three-phase input voltage and the DC output voltage setting value Vref of the three-phase PFC rectifier;

[0043] Step 2: Based on the numerical relationships obtained in Step 1, switch between boost control, buck control, and synchronous rectification control modes.

[0044] Step 2 is implemented in the following steps:

[0045] When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in buck mode;

[0046] When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in boost mode;

[0047] When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in synchronous rectification mode;

[0048] Where Vref is the DC output voltage setting value, Um is the peak line voltage of the rectifier's three-phase input voltage, and ΔU% represents the fluctuation range of the grid voltage.

[0049] To facilitate the analysis of the entire operation of the rectifier, the following assumptions are made: 1. The three-phase voltages VA, VB, and VC on the grid side have the same amplitude and are 120° out of phase; 2. The saturation problem of the input inductor is not considered; 3. The dead time of the power switching transistors is not considered; 4. The three-phase rectifier operates at unity power factor.

[0050] When the rectifier operates in boost mode, it is powered by... Figure 1 and Figure 2 As shown in the rectifier main circuit structure, the rectifier has three bridge arms: A, B, and C. The switching signals of the upper and lower bridge arms of each phase satisfy a complementary logic relationship. To prevent overcurrent problems caused by bridge arm shoot-through, a dead time needs to be set for the drive signals of the switching transistors on the same bridge arm. The drive signal of the three-phase rectifier is obtained by comparing a sinusoidal modulated wave with a triangular carrier wave; this signal is called a binary logic signal. For PWM modulation, since each bridge arm has two switching modes, namely, the upper bridge arm is on or the lower bridge arm is on, it is described using a binary logic switching function pk (k=a, b, c), i.e.

[0051] (1)

[0052] When pk=1, the upper bridge arm switch is turned on; when pk=-1, the lower bridge arm switch is turned on. Therefore, there are a total of 2 switches across the six bridge arms. 3 =8 combined working modes, as shown in Table 1.

[0053] Table 1. Eight switching modes of three-phase rectifier during boost operation.

[0054]

[0055] In Table 1, switch states 7# and 8# are in the zero-switching state. At this time, the AC input voltage is zero. When performing target vector synthesis, selecting an appropriate zero state can minimize the switching state transitions and make the system operation more stable.

[0056] (2)

[0057] In equation (2), Xa, Xb, and Xc represent the time during which the high-level conduction is maintained within one switching cycle.

[0058] The equivalent circuit operating in buck mode is as follows: Figure 5 As shown, when the three-phase rectifier is operating in buck mode, in order to prevent the DC side inductor current from being discontinuous, the three-phase rectifier requires that one bridge arm be directly connected at any given time, that is, the inductor current freewheeling circuit is formed through the three bridge arms.

[0059] Since binary logic signals cannot represent the situation where a bridge arm is shoot-through, a new switching logic signal is needed for control. This signal is called the ternary logic signal σk (k=a,b,c), and can be represented as:

[0060] (3)

[0061] According to the three-valued logic signal expression shown in equation (3), there are 9 working modes for the three-phase rectifier step-down operation.

[0062] Table 2 Logic Signals During Three-Phase Rectifier Step-Down Operation

[0063]

[0064] Switching states 7#, 8#, and 9# represent the zero state when the three-phase rectifier bridge arms are directly connected. This corresponds to the A-phase bridge arm switches being fully on, the B-phase bridge arm switches being fully on, and the C-phase bridge arm switches being fully on, respectively. The existence of the zero state ensures that the DC-side inductor current always has a path. During the switching state transition within one modulation wave cycle, to reduce switching losses, the selection of switch states should also follow the principle of minimizing the number of switch switching operations during each operating mode transition.

[0065] (4)

[0066] In equation (4), Sk (k=a, b, c), Sa=1 indicates that the voltage of phase A is greater than 0, Sb=1 indicates that the voltage of phase B is greater than 0, and Sc=1 indicates that the voltage of phase A is greater than 0.

Claims

1. A control method for a three-phase PFC rectifier circuit compatible with both boost and buck control, characterized in that: The circuit includes an input filter circuit, a power switch circuit, an output filter circuit, and a control circuit. The input filter circuit is connected to the power switch circuit, the power switch circuit is connected to the output filter circuit, and the output terminal of the control circuit is connected to the power switch circuit. The input filter circuit includes inductors La, Lb, and Lc, and capacitors Ca, Cb, and Cc; the power switching circuit includes power MOSFETs Qa1, Qa2, Qa3, Qa4, Qb1, Qb2, Qb3, Qb4, Qc1, Qc2, Qc3, and Qc4; the output filter circuit includes inductor Ldc and capacitor Co; one end of inductor La is connected to the A-phase voltage, and the other end is connected to one end of capacitor Ca; one end of inductor Lb is connected to the B-phase voltage, and the other end is connected to capacitor Cb. One end is connected; one end of inductor Lc is connected to the C-phase voltage, and the other end is connected to one end of capacitor Cc; the other ends of capacitors Ca, Cb, and Cc are connected; one end of inductor Ldc is connected to one end of capacitor Co, and the other ends of inductor Ldc and capacitor Co are respectively connected to the control circuit; the drain of power MOSFET Qa1 is connected to the other end of inductor Ldc, the source of power MOSFET Qa1 is connected to the source of power MOSFET Qa2, the drain of power MOSFET Qa2 is connected to the other end of inductor La, and the gate of power MOSFET Qa1 is connected to the gate of power MOSFET Qa2; the drain of power MOSFET Qa3 is connected to the other end of inductor La, and power M... The source of MOSFET Qa3 is connected to the source of power MOSFET Qa4. The drain of power MOSFET Qa4 is connected to the other end of capacitor Co. The gate of power MOSFET Qa3 is connected to the gate of power MOSFET Qa4. The drain of power MOSFET Qb1 is connected to the other end of inductor Ldc. The source of power MOSFET Qb1 is connected to the source of power MOSFET Qb2. The drain of power MOSFET Qb2 is connected to the other end of inductor Lb. The gate of power MOSFET Qb1 is connected to the gate of power MOSFET Qb2. The drain of power MOSFET Qb3 is connected to the other end of inductor Lb. The source of power MOSFET Qb3 is connected to the source of power MOSFET Qb4. The drain of power MOSFET Qb4 is connected to... The other end of capacitor Co is connected to the power MOSFET Qb3, and the gate of power MOSFET Qb4 is connected to the power MOSFET Qb4. The drain of power MOSFET Qc1 is connected to the other end of inductor Ldc, the source of power MOSFET Qc1 is connected to the source of power MOSFET Qc2, the drain of power MOSFET Qc2 is connected to the other end of inductor Lc, and the gate of power MOSFET Qc1 is connected to the gate of power MOSFET Qc2. The drain of power MOSFET Qc3 is connected to the other end of inductor Lc, the source of power MOSFET Qc3 is connected to the source of power MOSFET Qc4, the drain of power MOSFET Qc4 is connected to the other end of capacitor Co, and the gate of power MOSFET Qc3 is connected to the gate of power MOSFET Qc4. It also includes an auxiliary power supply, which is connected to the control circuit; the other end of the inductor Ldc is connected to the auxiliary power supply; the other end of the capacitor Co is connected to the auxiliary power supply; it also includes a resistor RL, which is connected in parallel with the capacitor Co; the input terminal of the control circuit is connected to a three-phase input voltage signal and a three-phase input current signal, and the output terminal is connected to a power switch circuit. The control method includes the following steps: Step 1: Determine the numerical relationship between the three-phase input voltage and the DC output voltage setting value Vref of the three-phase PFC rectifier; Step 2: Based on the numerical relationships obtained in Step 1, switch between boost control, buck control, and synchronous rectification control operating modes, specifically as follows: When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in buck mode; When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in boost mode; When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in synchronous rectification mode; Where Vref is the DC output voltage setting value, Um is the peak line voltage of the rectifier's three-phase input voltage, and ΔU% represents the fluctuation range of the grid voltage; The three-phase input voltages have the same amplitude, but their phases differ by 120° sequentially.

Images