A method for constructing a five-dimensional hyperchaotic system containing cubic nonlinear terms, a synchronization method and a chaotic signal generator

Abstract

The invention discloses a method for constructing a five-dimensional hyperchaotic system containing cubic nonlinear terms, a synchronization method thereof and a chaotic signal generator, belonging to the technical field of chaotic systems. A new 5-D hyperchaotic system containing high-order nonlinear terms is constructed to solve the problems of poor anti-degradation ability and low security of existing chaotic systems in the digital domain. The mathematical model is expressed as follows: Through dynamic characteristic analysis, it is proved that the maximum Lyapunov exponent of the chaotic system is close to 2. Combining the Lyapunov stability theorem and nonlinear control theory, the invention also proposes a multivariable nonlinear feedback synchronization controller, which is based on FPGA design and realizes the synchronization of high-dimensional complex hyperchaotic systems containing high-order terms, which can greatly shorten the synchronization time, thereby improving the working performance of the entire system and ensuring the real-time performance of chaotic secure communication.

Description

Technical Field

[0001] The invention belongs to the technical field of chaotic systems, and in particular relates to a five-dimensional hyperchaotic system construction method containing cubic nonlinear terms, a synchronization method thereof, and a chaotic signal generator. Background Art

[0002] With the gradual increase in information security requirements, the research on secure communication technology has become particularly important, and the application of chaos theory to secure communication has received more and more attention. Among them, chaos synchronization is an important research topic in chaotic secure communication, and the chaotic synchronization receiving and sending system has gradually expanded from low-dimensional chaotic systems to high-dimensional chaotic systems. Hyperchaotic systems have two or more attractors and positive Lyapunov exponents, and their phase orbits can be separated in more directions. They are much more complex than general low-dimensional chaotic systems in terms of algebraic structure and dynamic behavior, and have higher confidentiality and are more difficult to decipher, and have greater research value and development prospects. Therefore, creating a high-dimensional complex chaotic system and realizing chaotic synchronization has become the key to the research of chaotic secure communication.

[0003] At present, there are few related research contents on high-dimensional chaotic systems with high-order terms. At the same time, the maximum Lyapunov exponent of most hyperchaotic systems does not exceed 1. For hyperchaotic systems, the larger the Lyapunov exponent, the better the system performance. In the field of secure communications, high-dimensional chaotic systems can provide more complex system keys. When applied to image encryption, they can provide a larger key space. On this basis, a larger Lyapunov exponent can further increase the complexity of the system, thereby improving the security of the system, making it more confidential and more difficult to decipher. Therefore, it is very necessary to study higher-dimensional, higher-order hyperchaotic systems with larger Lyapunov exponents. Summary of the invention

[0004] Based on the above shortcomings, the present invention provides a five-dimensional hyperchaotic system containing cubic nonlinear terms to solve the problems of poor anti-degradation ability and low security of existing chaotic systems in the digital domain. According to MATLAB simulation and dynamic characteristics analysis, the maximum Lyapunov exponent of the hyperchaotic system is close to 2, which has higher confidentiality and is more difficult to decipher.

[0005] The technical solution adopted by the present invention is as follows: a five-dimensional hyperchaotic system containing cubic nonlinear terms, the construction method is as follows: on the basis of the Qi hyperchaotic system, dimensions and nonlinear terms are added at the same time to construct a five-dimensional hyperchaotic system, and the mathematical model is expressed as follows:

[0006]

[0007] Among them, x, y, z, w, v are the system state vectors, and a, b, c, d, l, f, h, j, p, k are the system constant parameters.

[0008] Another object of the present invention is to provide a synchronization method for a five-dimensional hyperchaotic system containing cubic nonlinear terms, which ensures the real-time performance of chaotic secure communication.

[0009] The technical solution adopted by the present invention is as follows: a synchronization method of a five-dimensional hyperchaotic system containing a cubic nonlinear term, the steps are as follows:

[0010] Step 1: Based on the Qi hyperchaotic system, dimensions and nonlinear terms are added at the same time to construct a five-dimensional hyperchaotic system with cubic nonlinear terms. The mathematical model is expressed as follows:

[0011]

[0012] Among them, x, y, z, w, v are system state vectors, a, b, c, d, l, f, h, j, p, k are system constant parameters, a=14, b=0.5, c=2, d=2, l=6, f=4.5, h=3, j=0.5, p=15, k=0.423;

[0013] Step 2: Then use the constructed five-dimensional hyperchaotic system as the driving system, and the corresponding response system is:

[0014]

[0015] Among them, x1, y1, z1, w1, v1 are system state vectors, and u1-u5 are synchronous controllers;

[0016] Step 3: Use the Euler algorithm to discretize the drive system. The mathematical model is expressed as follows:

[0017] x(n+1)=[ay(n)-bx(n)+cy(n)z(n)+y(n)z(n)w(n)]×T+x(n)

[0018] y(n+1)=[dx(n)+ly(n)-x(n)z(n)-fv(n)-x(n)z(n)w(n)]×T+y(n)

[0019] z(n+1)=[-hz(n)+y(n) 2 +x(n)y(n)w(n)]×T+z(n)

[0020] w(n+1)=[-jy(n)z(n)-pw(n)+x(n)y(n)z(n)]×T+w(n)

[0021] v(n+1)=[k(x(n)+v(n))]×T+v(n) (3)

[0022] Among them, x(n), y(n), z(n), w(n), v(n) are the state vectors of the drive system;

[0023] The Euler algorithm is used to discretize the response system, and the mathematical model is expressed as follows:

[0024] x1(n+1)=[ay1(n)-bx1(n)+cy1(n)z1(n)+y1(n)z1(n)w1(n)]×T+x1(n)+u1

[0025] y1(n+1)=[dx1(n)+ly1(n)-x1(n)z1(n)-fv1(n)-x1(n)z1(n)w1(n)]×T+y1(n)+u2

[0026] z1(n+1)=[-hz1(n)+y1(n) 2 +x1(n)y1(n)w1(n)]×T+z1(n)+u3

[0027] w1(n+1)=[-jy1(n)z1(n)-pw1(n)+x1(n)y1(n)1z1(n)]×T+w1(n)+u4

[0028] v1(n+1)=[k(x1(n)+v1(n))]×T+v1(n)+u5 (4)

[0030] Where T is the sampling step, x1(n), y1(n), z1(n), w1(n), v1(n) are the state vectors of the response system;

[0031] And, the mathematical model of the error function of the response system and the driving system is expressed as:

[0032] Δe x =T×[ae y -be x +c(y1(n)z1(n)-y(n)z(n))+y1(n)z1(n)w1(n)-y(n)z(n)w(n)]+u1

[0033] Δr y =T×[de x +le y -(x1(n)z1(n)-x(n)z(n))-fe v -x1(n)z1(n)w1(n)+x(n)z(n)w(n)]+u2

[0034] Δe z = T × [-he z + (y1(n) + y(n))e y + x1(n)y1(n)w1(n) - x(n)y(n)w(n)] + u3

[0035] Δe w = T × [-j(y1(n)z1(n) - y(n)z(n)) - pe w + x1(n)y 1n (n)z1(n) - x(n)y(n)z(n)] + u4

[0036] Δe v = T × [k(e x + e v )] + u5 (5)

[0037] where, e x = x1(n) - x(n), e y = y1(n) - y(n), e z = z1(n) - z(n),

[0038] e w = w1(n) - w(n), e v = v1(n) - v(n),

[0039] Step 4: Design the synchronization controller u i , i = 1, 2, 3, 4, 5, and the mathematical model is expressed as follows:

[0040] u1 = x(n) - x1(n) - T × [ae y + cy1(n)z1(n) - cy(n)z(n) + y1(n)z1(n)w1(n) - y(n)z(n)w(n)]

[0041] u2 = y(n) - y1(n) - T × [de x + 2le y - x(n)z(n) + x1(n)z1(n) - fe v + x(n)z(n)w(n) - x1(n)z1(n)w1(n)]

[0042] u3 = z(n) - z1(n) - T × [e y (y1(n) + y(n)) + x1(n)y1(n)z1(n) - x(n)y(n)z(n)]

[0043] u4=w(n)-w1(n)-T×[j(y(n)z(n)-y1(n)z1(n))+x1(n)y1(n)z1(n)-x(n)y(n)z(n)]

[0044] u5=v(n)-v1(n)-T×[2ke v +ke x ] (6)

[0046] The driving system and the response system input different initial values ​​to generate sequences. The sequence generated by the driving system is output to the response system and iterates in the response system. In addition to outputting the generated sequence, the response system also outputs the error between the sequences generated by the two systems. When the error is 0, the output sequences of the two systems are exactly the same, that is, the two systems are completely synchronized.

[0047] Another object of the present invention is to provide a chaotic signal generator, which, when applied to the field of confidential communications, can greatly improve the system key complexity and anti-attack capability, thereby improving the security of the communication system.

[0048] The technical solution adopted by the present invention is as follows: a chaotic signal generator, including a power supply unit, a clock unit, a reset unit, an FPGA digital circuit unit and an output port. The FPGA digital circuit unit adopts the synchronization method as described above to generate a drive system and a response system. Under the action of a synchronization controller, two chaotic systems with the same result but different initial values ​​can quickly achieve synchronization. The bit width used by the FPGA digital circuit unit adopts a 24-bit fixed-point number format, in which the upper 6 bits are the integer part and the lower 18 bits are the decimal part. The FPGA digital circuit unit is used to describe the mathematical model of a five-dimensional hyperchaotic system, including fixed-point multiplication operations, fixed-point addition operations, data rounding and saturation truncation operations and final numerical output; a state machine is written in Verilog language to implement the above operations.

[0049] Among them, the state machine of the drive system includes:

[0050] 1) The state machine is asynchronously reset. When the reset signal is valid, all signals are initialized and the state jumps to S0;

[0051] 2) S0: Assign the initial key tx_key[119:0] to chaos_x[119:96], chaos_y[95:72], chaos_z[71:48], chaos_w[47:24], chaos_v[23:0] respectively, and output the valid signal high, indicating that the output is valid at this time, and the state jumps to S1;

[0052] 3) S1: Complete the shift operation, output the valid signal low, and realize the multiplication of the coefficient in the chaos equation and the state vector by shifting the state vector. After completion, the state jumps to S2;

[0053] 4) S2: When the state jumps to S2, the result of S1 is added and subtracted. To prevent the addition of the two items from overflowing, the result of the operation needs to be extended by one sign bit. The polynomial multiplication and decimal processing operations are completed outside the always block. First, the need for a carry is determined by the characteristics of the sign bit and the truncated part: if the number is positive and the highest bit of the truncated part is 1, then a carry is required. If the number is negative, it is necessary to determine whether the highest bit of the truncated part and the bits other than the highest bit are 1. If so, no carry is required. After calculating the carry, the carry is added to the number after the decimal place is truncated to complete the rounding operation. At the same time, to prevent overflow when adding the carry, a sign bit extension is required, and the state jumps to S3;

[0054] 5) S3: The decimal places have been processed in S2, and the integer places are mainly processed in S3, and the extra integer places need to be truncated:

[0055] If the highest bit of the part to be truncated is the same as the highest bit after truncation, that is, all 0 or all 1, it means that the part to be truncated is an extension of the sign bit and is truncated directly; if they are different, the sign bit is determined. If it is positive, it is converted to the maximum value that can be stored in the required format data. If it is negative, it is converted to the minimum value that can be stored in the required format data, and the final result is assigned to chaos_x, chaos_y, chaos_z, chaos_w, chaos_v, and the output valid signal is pulled high. The state

[0056] Jump to S1, the data is transmitted to the response system, and a set of data generation is completed;

[0057] Among them, the state machine of the response system includes:

[0058] 1) The state machine is reset asynchronously. When the reset signal is valid, all signals are initialized and the state jumps to S00;

[0059] 2) S00: Assign the initial key rx_key[119:0] to syn_x[119:96], syn_y[95:72], syn_z[71:48], syn_w[47:24], syn_v[23:0] respectively; the first output is the initial key value. In the second round of iteration, the output of the drive system will be input to the response system to participate in the loop iteration, and the output valid signal will be pulled high, indicating that the output is valid at this time, and the state jumps to S01;

[0060] 3) S01: Complete the shift operation, output the valid signal low, and realize the multiplication of the coefficient and the state vector in the chaos equation by shifting the state vector; in the response system module, the output needs to add the error signal, and the error signal value is the difference between the syn signal and the chaos signal, which is output at S01. At this time, the error valid signal is pulled high, and the state jumps to S02 after completion;

[0061] 4) S02: Perform addition and subtraction operations on the results of S01. To prevent the addition of two items from overflowing, the operation result needs to be extended by one sign bit. The decimal place processing is also completed outside the always block. The error valid signal is pulled low, and the state jumps to S03;

[0062] 5) S03: The decimal places have been processed in S02. In S03, the integer places are mainly processed. The extra integer places need to be cut off and the final result is assigned to syn_x, syn_y, syn_z, syn_w, syn_v. The output valid signal is pulled high.

[0063] The state jumps to S01, data is output, and a set of data generation is completed.

[0064] The beneficial effects and advantages of the present invention are as follows: compared with the existing hyperchaotic system, the maximum Lyapunov index of the five-dimensional hyperchaotic system containing cubic nonlinear terms created by the present invention is 1.9380, the hyperchaotic characteristics are obvious, the maximum Lyapunov index far exceeds the maximum Lyapunov index of most hyperchaotic systems, the algebraic structure and dynamic behavior are more complex, the confidentiality is higher and more difficult to decipher, and the simulation results of the digitized hyperchaotic system show that the high-dimensional hyperchaotic system has a certain ability to resist the degradation of chaotic characteristics. Its application in the field of confidential communication will greatly improve the system key complexity and anti-attack ability, thereby improving the security of the communication system. In the synchronization design, nonlinear feedback synchronization control is adopted, and the design is completed by hardware. Two hyperchaotic systems with the same structure and different initial values ​​can quickly achieve synchronization. It can be seen from the simulation results that under a 50MHz clock, it only takes 0.0003ms to achieve synchronization. In practical applications, the synchronization establishment time can be greatly shortened, the overall transmission efficiency can be improved, and the system performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 is the phase diagram of the hyperchaotic system;

[0066] Figure 2 is the graph of Lyapunov index changing with k;

[0067] Figure 3 is the bifurcation diagram of x changing with k;

[0068] Figure 4 Phase diagrams for different attractor morphologies;

[0069] Figure 5 This is the top-level architecture diagram of the chaos synchronization system;

[0070] Figure 6 It is the flowchart of the driving system algorithm;

[0071] Figure 7 To respond to the system algorithm flow chart;

[0072] Figure 8 This is the x, y, z, w, v time series diagram of modelim simulation;

[0073] Fig. 9 This is the simulation result diagram of the chaotic synchronization system;

[0074] Fig.10 It is a local diagram of simulation results; DETAILED DESCRIPTION

[0075] The present invention is further described in detail below in conjunction with the embodiments and drawings.

[0076] Example 1

[0077] The hardware implementation in this embodiment is based on FPGA in a programmable device, and the hardware description language or hardware design language used is Verilog HDL. The specific implementation process is as follows:

[0078] (1) Constructing a new hyperchaotic system

[0079] This embodiment adds dimension and nonlinear term on the basis of Qi hyperchaotic system, and proposes a new 5-D chaotic system with cubic nonlinear term, whose mathematical model is expressed as follows:

[0080]

[0081] Among them, x, y, z, w, v are the system state vectors, and a, b, c, d, l, f, h, j, p, k are the system constant parameters.

[0082] Set the initial value of the chaotic system to (x0, y0, z0, w0, v0) = (1, 0.25, 2, -1, 1.5),

[0083] When a=14, b=0.5, c=2, d=2, l=6, f=4.5, h=3, j=0.5, p=15, k=0.423, the Lyapunov exponent of the chaotic system is:

[0084] LE1=1.9380,LE2=0.1391,LE3=-0.0084,LE4=-2.3637,LE5=-11.1328, indicating that the chaotic system is a hyperchaotic system at this time. Figure 1 is the phase diagram of the hyperchaotic system, (a) is the phase diagram of the system xy plane, (b) is the phase diagram of the system xz plane, (c) is the phase diagram of the system xw plane, (d) is the phase diagram of the system xv plane, (e) is the phase diagram of the system yz plane, (f) is the phase diagram of the system yw plane, (g) is the phase diagram of the system zv plane, and (h) is the phase diagram of the system zw plane. Figure 2 and Figure 3 As shown in the figure, as the coefficient k increases, the attractor shows different forms. When k = -0.095, there are four negative and one zero Lyapunov exponents, and the attractor is a periodic attractor; when k = 0.055, the Lyapunov exponents of the system are one positive, one zero and three negative, and the system begins to show chaotic characteristics; when k = 0.424, the Lyapunov exponents of the system are two positive, one zero and two negative, and the system is a hyperchaotic system. It can also be seen from the bifurcation diagram that with the change of k, the system switches between periodic, chaotic and hyperchaotic states. The specific values ​​are shown in Table 1. Figure 4 These are phase diagrams of attractors of different forms, namely, xyz plane phase diagram of periodic attractor (a), ywv plane phase diagram of periodic attractor (b), xyz plane phase diagram of chaotic attractor (c), ywv plane phase diagram of chaotic attractor (d), xyz plane phase diagram of hyperchaotic attractor (e), ywv plane phase diagram of hyperchaotic attractor (f).

[0085] Table 1 Lyapunov exponent and attractor morphology

[0086]

[0087] From Table 1, it can be concluded that the maximum Lyapunov exponent of the hyperchaotic system can reach 1.9380, indicating that the designed hyperchaotic system has better performance.

[0088] (2) Chaos synchronization design

[0089] Let the new five-dimensional hyperchaotic system be the driving system, then the corresponding response system is:

[0090]

[0091] Among them, x1, y1, z1, w1, v1 are system state vectors, and u1-u5 are synchronous controllers;

[0092] The Euler method discrete drive system and response system are expressed as:

[0093]

[0094] Where T is the sampling period, this time T = 2 × 10 -8 , x(n), y(n), z(n), w(n), v(n) are the state vectors of the driving system, and x1(n), y1(n), z1(n), w1(n), v1(n) are the state vectors of the response system.

[0095] The error function of the driving system and the response system can be expressed as:

[0096] Δe x =T×[ae y -be x +c(y1(n)z1(n)-y(n)z(n))+y1(n)z1(n)w1(n)-y(n)z(n)w(n)]+u1

[0097] Δe y =T×[de x +le y -(x1(n)z1(n)-x(n)z(n))-fe v -x1(n)z1(n)w1(n)+x(n)z(n)w(n)]+u2

[0098] Δe z =T×[-he z +(y1(n)+y(n))e y +x1(n)y1(n)w1(n)-x(n)y(n)w(n)]+u3

[0099] Δe w =T×[-j(y1(n)z1(n)-y(n)z(n))-pe w +x1(n)y1(n)z1(n)-x(n)y(n)z(n)]+u4

[0100] Δe v =T×[k(e x +e v )]+u5 (5)

[0102] where e x =x1(n)-x(n),e y =y1(n)-y(n),e z =z1(n)-z(n),

[0103] e w =w1(n)-w(n),e v =v1(n)-v(n).

[0104] Construct synchronization controller u i (i=1,2,3,4,5) can be expressed as:

[0105] u1=x(n)-x1(n)-T×[ae y +cy1(n)z1(n)-cy(n)z(n)+y1(n)z1(n)w1(n)-y(n)z(n)w(n)]

[0106] u2=y(n)-y1(n)-T×[de x +2le y -x(n)z(n)+x1(n)z1(n)-fe v +x(n)z(n)w(n)-x1(n)z1(n)w1(n)]

[0107] u3=z(n)-z1(n)-T×[e y (y1(n)+y(n))+x1(n)y1(n)z1(n)-x(n)y(n)z(n)]

[0108] u4=w(n)-w1(n)-T×[j(y(n)z(n)-y1(n)z1(n))+x1(n)y1(n)z1(n)-x(n)y(n)z(n)]

[0109] u5=v(n)-v1(n)-T×[2ke v +ke x ] (6) The driving system and the response system input different initial values ​​to generate sequences. The sequence generated by the driving system is output to the response system and iterates in the response system. In addition to outputting the generated sequence, the response system also outputs the error between the sequences generated by the two systems. When the error is 0, the output sequences of the two systems are exactly the same, that is, the two systems are completely synchronized.

[0111] (3) Hardware Implementation

[0112] The top-level architecture of the chaotic synchronization system is shown in Figure 5, and the definitions of each signal interface are shown in Table 2.

[0113] The state machine of the drive system includes:

[0114] 1) The state machine is asynchronously reset. When the reset signal is valid, all signals are initialized and the state jumps to S0;

[0115] 2) S0: Assign the initial key tx_key[119:0] to chaos_x[119:96], chaos_y[95:72], chaos_z[71:48], chaos_w[47:24], chaos_v[23:0] respectively, and output the valid signal high, indicating that the output is valid at this time, and the state jumps to S1;

[0116] 3) S1: Complete the shift operation, output the valid signal low, and realize the multiplication of the coefficient in the chaos equation and the state vector by shifting the state vector. After completion, the state jumps to S2;

[0117] 4) S2: When the state jumps to S2, the result of S1 is added and subtracted. To prevent the addition of the two items from overflowing, the result of the operation needs to be extended by one sign bit. The polynomial multiplication and decimal processing operations are completed outside the always block. First, the need for a carry is determined by the characteristics of the sign bit and the truncated part: if the number is positive and the highest bit of the truncated part is 1, then a carry is required. If the number is negative, it is necessary to determine whether the highest bit of the truncated part and the bits other than the highest bit are 1. If so, no carry is required. After calculating the carry, the carry is added to the number after the decimal place is truncated to complete the rounding operation. At the same time, to prevent overflow when adding the carry, a sign bit extension is required, and the state jumps to S3;

[0118] 5) S3: The decimal place processing has been completed in S2, and the integer place is mainly processed in S3, and the extra integer place needs to be truncated: if the part to be truncated is the same as the highest place after truncating, that is, all are 0 or all are 1, it means that the part to be truncated is an extension of the sign bit, and it is directly truncated; if they are not the same, the sign bit is judged, if it is positive, it is converted to the maximum value that can be stored in the required format data, if it is negative, it is converted to the minimum value that can be stored in the required format data, and the final result is assigned to chaos_x, chaos_y, chaos_z, chaos_w, chaos_v, the output valid signal is pulled high, the state jumps to S1, the data is transmitted to the response system, and a set of data generation is completed;

[0119] Among them, the state machine of the response system includes:

[0120] 1) The state machine is reset asynchronously. When the reset signal is valid, all signals are initialized and the state jumps to S00;

[0121] 2) S00: Assign the initial key rx_key[119:0] to syn_x[119:96], syn_y[95:72], syn_z[71:48], syn_w[47:24], syn_v[23:0] respectively; the first output is the initial key value. In the second round of iteration, the output of the drive system will be input to the response system to participate in the loop iteration, and the output valid signal will be pulled high, indicating that the output is valid at this time, and the state jumps to S01;

[0122] 3) S01: Complete the shift operation, output the valid signal low, and realize the multiplication of the coefficient and the state vector in the chaos equation by shifting the state vector; in the response system module, the output needs to add the error signal, and the error signal value is the difference between the syn signal and the chaos signal, which is output at S01. At this time, the error valid signal is pulled high, and the state jumps to S02 after completion;

[0123] 4) S02: Perform addition and subtraction operations on the results of S01. To prevent the addition of two items from overflowing, the operation result needs to be extended by one sign bit. The decimal place processing is also completed outside the always block. The error valid signal is pulled low, and the state jumps to S03;

[0124] 5) S03: The decimal places have been processed in S02, and the integer places are mainly processed in S03. The extra integer places need to be truncated, and the final result is assigned to syn_x, syn_y, syn_z, syn_w, syn_v. The output valid signal is pulled high, the state jumps to S01, the data is output, and a set of data generation is completed.

[0125] Figure 6 and Figure 7 The algorithm flow charts of the driving system and the response system are shown in Figure 2. The simulation results of the new five-dimensional hyperchaotic system are shown in Figure 2. Figure 8 As shown in the figure, the output data of x, y, z, w, v are compared with the MATLAB simulation data, and the results are the same, and there is no periodic phenomenon in the output sequence, indicating that the digitized high-dimensional chaotic system has a certain ability to resist the degradation of chaotic characteristics. Fig. 9 As shown, observe Fig. 9 It can be seen that under the condition of 50MHz clock, the output time of the first synchronization sequence is 0.00066ms, and at 0.00096ms, error_x[23:0], error_y[23:0], error_z[23:0], error_w[23:0] and error_v[23:0] are all zero, achieving complete synchronization of hyperchaotic systems with the same structure and different initial values, and the synchronization establishment time is very short, reflecting the superior performance of hardware-implemented chaotic synchronization. It shows the correctness of the design scheme of the present invention.

[0126] Table 2 Signal Definition

[0127]

Claims

1. A chaotic signal generator, comprising a power supply unit, a clock unit, a reset unit, an FPGA digital circuit unit and an output port, characterized in that: The FPGA digital circuit unit adopts a synchronization method of a five-dimensional hyperchaotic system containing cubic nonlinear terms to generate a driving system and a response system. Under the action of a synchronization controller, two chaotic systems with the same result but different initial values ​​can quickly achieve synchronization. The bit width used by the FPGA digital circuit unit adopts a 24-bit fixed-point number format, in which the upper 6 bits are the integer part and the lower 18 bits are the decimal part. The FPGA digital circuit unit is used to describe the mathematical model of the five-dimensional hyperchaotic system, including fixed-point number multiplication, fixed-point number addition, data rounding and saturation truncation operations and the final numerical output; the state machine is written in Verilog language to realize fixed-point number multiplication, fixed-point number addition, data rounding and saturation truncation operations. The synchronization method of a five-dimensional hyperchaotic system containing a cubic nonlinear term comprises the following steps: Step 1: Based on the Qi hyperchaotic system, dimensions and nonlinear terms are added at the same time to construct a five-dimensional hyperchaotic system with cubic nonlinear terms. The mathematical model is expressed as follows: Among them, x, y, z, w, v are system state vectors, a, b, c, d, l, f, h, j, p, k are system constant parameters, a=14, b=0.5, c=2, d=2, l=6, f=4.5, h=3, j=0.5, p=15, k=0.423; Step 2: Then use the constructed five-dimensional hyperchaotic system as the driving system, and the corresponding response system is: Among them, x1, y1, z1, w1, v1 are system state vectors, and u1-u5 are synchronous controllers; Step 3: Use the Euler algorithm to discretize the drive system. The mathematical model is expressed as follows: x(n+1)=[ay(n)-bx(n)+cy(n)z(n)+y(n)z(n)w(n)]×T+x(n) y(n+1)=[dx(n)+ly(n)-x(n)z(n)-fv(n)-x(n)z(n)w(n)]×T+y(n) z(n+1)=[-hz(n)+y(n) 2 +x(n)y(n)w(n)]×T+z(n) w(n+1)=[-jy(n)z(n)-pw(n)+x(n)y(n)z(n)]×T+w(n) v(n+1)=[k(x(n)+v(n))]×T+v(n) (3) Among them, x(n), y(n), z(n), w(n), v(n) are the state vectors of the drive system; The Euler algorithm is used to discretize the response system, and the mathematical model is expressed as follows: x1(n+1)=[ay1(n)-bx1(n)+cy1(n)z1(n)+y1(n)z1(n)w1(n)]×T+x1(n)+u1 y1(n+1)=[dx1(n)+ly1(n)-x1(n)z1(n)-fv1(n)-x1(n)z1(n)w1(n)]×T+y1(n)+u2 z1(n+1)=[-hz1(n)+y1(n) 2 +x1(n)y1(n)w1(n)]×T+z1(n)+u3 w1(n+1)=[-jy1(n)z1(n)-pw1(n)+x1(n)y1(n)1z1(n)]×T+w1(n)+u4 v1(n+1)=[k(x1(n)+v1(n))]×T+v1(n)+u5 (4) Where T is the sampling step, x1(n), y1(n), z1(n), w1(n), v1(n) are the state vectors of the response system; And, the mathematical model of the error function of the response system and the driving system is expressed as: Δe x =T×[ae y -path x +c(y1(n)z1(n)-y(n)z(n))+y1(n)z1(n)w1(n)-y(n)z(n)w(n)]+u1 Δe y =T×[of x +and y -(x1(n)z1(n)-x(n)z(n))-fe v -x1(n)z1(n)w1(n)+x(n)z(n)w(n)]+u2 Δe z =T×[-he z +(y1(n)+y(n))e y +x1(n)y1(n)w1(n)-x(n)y(n)w(n)]+u3 Δe2=T×[-j(y1(n)z1(n)-y(n)z(n))-pe w +x1(n)y 1n (n)z1(n)-x(n)y(n)z(n)]+u4 Δe v =T×[k(e x +e v )]+u5 (5) Among them, e x = x1(n)-x(n), e y = y1(n)-y(n), e z = z1(n)-z(n), e w =w1(n)-w(n),e v =v1(n)-v(n), Step 4: Design the synchronization controller u i , i=1,2,3,4,5, the mathematical model is expressed as follows: u1=x(n)-x1(n)-T×[ae y +cy1(n)z1(n)-cy(n)z(n)+y1(n)z1(n)w1(n)-y(n)z(n)w(n)] u2=y(n)-y1(n)-T×[de x +2and y -x(n)z(n)+x1(n)z1(n)-fe v +x(n)z(n)w(n)-x1(n)z1(n)w1(n)] u3=z(n)-z1(n)-T×[e y (y1(n)+y(n))+x1(n)y1(n)z1(n)-x(n)y(n)z(n)] u4=w(n)-w1(n)-T×[j(y(n)z(n)-y1(n)z1(n))+x1(n)y1(n)z1(n)-x(n)y(n)z(n)] u5=v(n)-v1(n)-T×[2ke v +ke x , (6) The drive system and the response system input different initial values ​​to generate sequences. The sequence generated by the drive system is output to the response system. The response system not only outputs the generated sequence, but also outputs the error between the generated sequences of the two systems. When the error is 0, the output sequences of the two systems are exactly the same, that is, the two systems are completely synchronized. Among them, the state machine of the drive system includes: 1) The state machine is asynchronously reset. When the reset signal is valid, all signals are initialized and the state jumps to S0; 2) S0: Assign the initial key tx_key[119:0] to chaos_x[119:96], chaos_y[95:72], chaos_z[71:48], chaos_w[47:24], chaos_v[23:0] respectively, and output the valid signal high, indicating that the output is valid at this time, and the state jumps to S1; 3) S1: Complete the shift operation, output the valid signal low, and realize the multiplication of the coefficient in the chaos equation and the state vector by shifting the state vector. After completion, the state jumps to S2; 4) S2: When the state jumps to S2, the result of S1 is added and subtracted. To prevent the addition of the two items from overflowing, the result of the operation needs to be extended by one sign bit. The polynomial multiplication and decimal processing operations are completed outside the always block. First, the need for a carry is determined by the characteristics of the sign bit and the truncated part: if the number is positive and the highest bit of the truncated part is 1, then a carry is required. If the number is negative, it is necessary to determine whether the highest bit of the truncated part and the bits other than the highest bit are 1. If so, no carry is required. After calculating the carry, the carry is added to the number after the decimal place is truncated to complete the rounding operation. At the same time, to prevent overflow when adding the carry, a sign bit extension is required, and the state jumps to S3; 5) S3: The decimal place processing has been completed in S2, and the integer place is processed in S3. The extra integer place needs to be truncated: if the part to be truncated is the same as the highest place after truncating, that is, all are 0 or all are 1, it means that the part to be truncated is an extension of the sign bit, and it is directly truncated; if they are not the same, the sign bit is judged, if it is positive, it is converted to the maximum value that can be stored in the required format data, if it is negative, it is converted to the minimum value that can be stored in the required format data, and the final result is assigned to chaos_x, chaos_y, chaos_z, chaos_w, chaos_v, the output valid signal is pulled high, the state jumps to S1, the data is transmitted to the response system, and a set of data generation is completed; Among them, the state machine of the response system includes: 1) The state machine is reset asynchronously. When the reset signal is valid, all signals are initialized and the state jumps to S00; 2) S00: Assign the initial key rx_key[119:0] to syn_x[119:96], syn_y[95:72], syn_z[71:48], syn_w[47:24], syn_v[23:0] respectively; the first output is the initial key value. In the second round of iteration, the output of the drive system will be input to the response system to participate in the loop iteration, and the output valid signal will be pulled high, indicating that the output is valid at this time, and the state jumps to S01; 3) S01: Complete the shift operation, output the valid signal low, and realize the multiplication of the coefficient and the state vector in the chaos equation by shifting the state vector; in the response system module, the output needs to add the error signal, and the error signal value is the difference between the syn signal and the chaos signal, which is output at S01. At this time, the error valid signal is pulled high, and the state jumps to S02 after completion; 4) S02: Perform addition and subtraction operations on the results of S01. To prevent the addition of two items from overflowing, the operation result needs to be extended by one sign bit. The decimal place processing is also completed outside the always block. The error valid signal is pulled low, and the state jumps to S03; 5) S03: The decimal places have been processed in S02. In S03, the integer places are processed. The extra integer places need to be truncated and the final result is assigned to syn_x, syn_y, syn_z, syn_w, syn_v. The output valid signal is pulled high, the state jumps to S01, the data is output, and a set of data generation is completed.

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