Image sensing computing unit and operation method thereof, image sensing computing unit and electronic device

Abstract

The present disclosure provides an image sensing operation unit and an operation method thereof, an image sensing operation unit and an electronic device. The image sensing operation unit includes a first photosensitive unit and a second photosensitive unit, and the second photosensitive unit is connected in series with the first photosensitive unit. The direction of change of the first threshold voltage of the first photosensitive unit when receiving light is opposite to the direction of change of the second threshold voltage of the second photosensitive unit when receiving light, so as to realize in-situ logical operation between light input signals. Therefore, compared with the prior art, the image sensing operation unit of the embodiment of the present disclosure can directly realize the in-situ logical processing function while performing photoelectric conversion, so that the image sensing operation unit directly outputs an electrical signal representing the corresponding logical operation result, thereby omitting the traditional signal processing module that plays a role of logical processing, effectively reducing the complexity of the system and improving the efficiency of light signal processing.

Description

Technical Field

[0001] The present disclosure relates to the fields of semiconductor technology and integrated circuit technology, and in particular to an image sensing computing unit and an operating method thereof, an image sensing computing unit, and an electronic device. Background Art

[0002] Image sensing and computing systems can effectively implement image perception and processing functions such as facial recognition and fingerprint recognition, and are widely used in fields such as surveillance and security, and human-computer interaction. Traditional image sensing and computing systems consist of an image sensing module and a processing module. These systems convert optical signals into electrical signals within the image sensing module before transmitting them to the processing module for logical operations. This results in complex image sensing and computing systems, large amounts of redundant data, and long transmission distances, severely impacting the system's image perception and computing efficiency. Summary of the Invention

[0003] (1) Technical issues to be resolved

[0004] In order to solve the technical problem in the prior art that traditional image sensing computing systems have low image perception computing efficiency due to the complex system composition, the present disclosure provides an image sensing computing unit and its operation method, an image sensing operator and an electronic device that can directly realize logical operations between light signals.

[0005] (2) Technical solution

[0006] One aspect of the present disclosure provides an image sensing computing unit, which includes a first photosensitive unit and a second photosensitive unit, and the second photosensitive unit is connected in series with the first photosensitive unit, wherein the direction of change of the first threshold voltage of the first photosensitive unit when receiving light is opposite to the direction of change of the second threshold voltage of the second photosensitive unit when receiving light, so as to realize in-situ logical operations between light input signals.

[0007] According to an embodiment of the present disclosure, the first photosensitive unit includes a first transistor, a first buried oxide layer and a first doped well layer, wherein the first buried oxide layer is located under the first transistor; and the first doped well layer is located under the first buried oxide layer.

[0008] According to an embodiment of the present disclosure, the second photosensitive unit includes a second transistor, a second buried oxide layer and a second doped well layer, the second buried oxide layer is located under the second transistor; the second doped well layer is located under the second buried oxide layer.

[0009] According to an embodiment of the present disclosure, the first transistor and the second transistor are of different transistor types, and the first doped well layer and the second doped well layer have the same well doping type. According to an embodiment of the present disclosure, the source of the first transistor is connected to a power supply voltage, the drain of the first transistor is connected to the drain of the second transistor, and the source of the second transistor is grounded; wherein the gate of the first transistor is connected to a first gate-control voltage, and the gate of the second transistor is connected to a second gate-control voltage; and the first doped well layer is connected to the first well-control voltage, and the second doped well layer is connected to the second well-control voltage.

[0010] Another aspect of the present disclosure provides an operating method for the above-mentioned image sensing computing unit, which includes: performing an exposure operation on the image sensing computing unit in a turned-off state, so that the equivalent resistance of the first photosensitive unit and / or the second photosensitive unit of the image sensing computing unit changes; controlling the first gate control voltage of the first photosensitive unit and / or the second gate control voltage of the second photosensitive unit of the image sensing computing unit that has undergone the exposure operation to generate an output voltage of the image sensing computing unit to implement a readout operation on the image sensing computing unit; and controlling the first gate control voltage of the first photosensitive unit and / or the second gate control voltage of the second photosensitive unit of the image sensing computing unit that has undergone the readout operation to turn off the first photosensitive unit and / or the second photosensitive unit; and simultaneously controlling the first trap control voltage and / or the second trap control voltage to implement a reset operation on the image sensing computing unit.

[0011] According to an embodiment of the present disclosure, in performing an exposure operation on an image sensing computing unit that is in a shut-off state, it includes: controlling the first gate-controlled voltage of the first photosensitive unit and / or the second gate-controlled voltage of the second photosensitive unit of the image sensing computing unit, so that the first photosensitive unit and / or the second photosensitive unit of the image sensing computing unit are shut off, and the image sensing computing unit is in a shut-off state; and simultaneously controlling the first trap-controlled voltage of the first photosensitive unit and / or the second trap-controlled voltage of the second photosensitive unit to implement the exposure operation.

[0012] According to an embodiment of the present disclosure, in controlling the first gate-controlled voltage of the first photosensitive unit and / or the second gate-controlled voltage of the second photosensitive unit of the image sensing computing unit that has undergone an exposure operation to generate the output voltage of the image sensing computing unit, it includes: when the first trap-controlled voltage of the first photosensitive unit and / or the second trap-controlled voltage of the second photosensitive unit remain unchanged, controlling the first gate-controlled voltage and / or the second gate-controlled voltage to turn on the first photosensitive unit and / or the second photosensitive unit; and reading the drain voltage between the first photosensitive unit and the second photosensitive unit as the output voltage.

[0013] Yet another aspect of the present disclosure provides an image sensor computing unit, which includes an image sensor array composed of the above-mentioned image sensor computing units.

[0014] Another aspect of the present disclosure provides an electronic device, which includes the above-mentioned image sensor operator.

[0015] (3) Beneficial effects

[0016] The present disclosure provides an image sensing operation unit and its operation method, an image sensing operation unit and an electronic device. The image sensing operation unit includes a first photosensitive unit and a second photosensitive unit, and the second photosensitive unit is connected in series with the first photosensitive unit. The direction of change of the first threshold voltage of the first photosensitive unit when receiving light is opposite to the direction of change of the second threshold voltage of the second photosensitive unit when receiving light, so as to realize in-situ logical operation between light input signals. Therefore, compared with the situation in the prior art where the image sensing operation system requires both the image sensing module to complete the photoelectric signal conversion and the signal operation processing module to perform further operation processing before finally realizing the logical operation between the light input signals, the image sensing operation unit of the embodiment of the present disclosure can directly realize the in-situ logical processing function while performing photoelectric conversion, so that the image sensing operation unit directly outputs an electrical signal representing the corresponding logical operation result, thereby omitting the signal processing module for traditional logical processing, effectively reducing the complexity of the system and improving the efficiency of image information processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The figure schematically shows a circuit diagram of an image sensing computing unit according to an embodiment of the present disclosure;

[0018] Figure 2 Schematic diagram showing the structure of the Np type photosensitive unit and its corresponding equivalent circuit diagram, the threshold voltage V th Relationship diagram with changes in light intensity;

[0019] Figure 3 Schematic diagram showing the structure of the Nn type photosensitive unit and its corresponding equivalent circuit diagram, the threshold voltage V th Relationship diagram with changes in light intensity;

[0020] Figure 4 Schematic diagram showing the structure of the Pp type photosensitive unit and its corresponding equivalent circuit diagram, the threshold voltage V th Relationship diagram with changes in light intensity;

[0021] Figure 5 Schematic diagram showing the structure of the Pn type photosensitive unit and its corresponding equivalent circuit diagram, the threshold voltage V th Relationship diagram with changes in light intensity;

[0022] Figure 6Schematically illustrates an equivalent circuit diagram of an image sensing computing unit composed of Pn-type photosensitive units and Nn-type photosensitive units capable of implementing NOR / NAND logic between light signals according to an embodiment of the present disclosure, and a schematic diagram of the corresponding NOR / NAND operation output;

[0023] Figure 7 Schematically illustrates an equivalent circuit diagram of an image sensing computing unit composed of a Pp-type photosensitive unit and an Np-type photosensitive unit capable of implementing AND / OR logic between light signals according to an embodiment of the present disclosure, and a corresponding AND / OR operation output diagram;

[0024] Figure 8 A flowchart schematically illustrates an operating method of an image sensing computing unit according to an embodiment of the present disclosure; and

[0025] Figure 9 The operation timing diagram of the above-mentioned image sensing operation unit that can realize the logical operation between light inputs according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0027] It should be noted that any implementations not shown or described in the drawings or the main text of the specification are known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods described in the embodiments; those skilled in the art may easily modify or replace them.

[0028] It should also be noted that directional terms such as "upper," "lower," "front," "back," "left," and "right" mentioned in the embodiments are merely references to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure.

[0029] Furthermore, the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but are merely illustrative of the contents of the embodiments of the present disclosure. In addition, in the claims, any reference signs placed between brackets should not be construed as limiting the claims.

[0030] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0031] The use of ordinal numbers such as "first," "second," "third," etc. in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

[0032] Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively modified and deployed in one or more devices different from the embodiments. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and furthermore, they can be divided into multiple sub-modules, sub-units, or sub-components. All features disclosed in this specification (including the accompanying claims, abstract, and drawings), as well as all processes or units of any method or device disclosed therein, can be combined in any combination, unless at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose. Furthermore, in a unit claim enumerating several means, several of these means may be embodied by the same item of hardware.

[0033] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, the disclosed aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present disclosure.

[0034] In order to solve the technical problems in the prior art that the optical signal operation processing of traditional image sensing computing systems requires a signal operation processing module to be implemented, resulting in a complex system composition and low logical processing efficiency, the present disclosure provides an image sensing computing unit and its operation method, an image sensing operator and an electronic device that can directly realize logical operations between optical signals.

[0035] like Figure 1As shown, one aspect of the present disclosure provides an image sensing computing unit 100 , which includes a first photosensitive unit 101 and a second photosensitive unit 102 , and the second photosensitive unit 102 is connected in series with the first photosensitive unit 101 .

[0036] The first threshold voltage V of the first photosensitive unit 101 when receiving light is th1 The change direction is related to the second threshold voltage V th2 The direction of change is opposite to achieve in-situ logical operations between optical input signals.

[0037] The image sensing computing unit 100 may be a structural unit having a photoelectric conversion function, wherein the first photosensitive unit 101 and the second photosensitive unit 102 may both be transistor units having a photosensitive function.

[0038] The first photosensitive unit 101 and the second photosensitive unit 102 are connected in series. The equivalent resistance of each of them in the series circuit directly affects the voltage-dividing effect of the two in the circuit. The larger the equivalent resistance, the larger the voltage value of the voltage division, and the smaller the equivalent resistance, the smaller the voltage value of the voltage division. At this time, if the two photosensitive units connected in series can show threshold voltages with different change directions under their respective lighting conditions, then their corresponding equivalent resistances also have corresponding different change directions. For example, when the first photosensitive unit 101 is exposed to light, the first threshold voltage V th1 increases, the equivalent resistance increases; correspondingly, when the second photosensitive unit 102 is illuminated by light, the second threshold voltage V th2 Thus, different illumination conditions correspond to different voltage division conditions of the two photosensitive units, and the output voltage V outputted from the output end of the image sensing computing unit 100 is out It can be directly output as a voltage signal of the corresponding logical operation result without the need for additional processing by other operation processing modules, thus realizing in-situ logical operation between optical input signals.

[0039] The two photosensitive cells in the disclosed embodiment exhibit opposite threshold voltage changes when illuminated, resulting in opposite changes in their corresponding equivalent resistances. When connected in series, the voltage divider relationship varies depending on the illumination conditions. By setting a reasonable voltage comparison value to determine the logic value corresponding to the output voltage, in-situ logic operations can be performed on the optical input signals.

[0040] Therefore, compared with the situation in the prior art where the image sensing module can only be used for photoelectric signal conversion, and the output electrical signal needs to be further converted and processed by the signal operation processing module before the logical operation between the optical input signals can be finally realized, the image sensing operation unit of the embodiment of the present disclosure can directly realize the in-situ logical processing function while performing photoelectric conversion, so that the image sensing operation unit directly outputs the electrical signal representing the corresponding logical operation result, thereby omitting the signal processing module with traditional logical processing function, effectively reducing the complexity of the system and improving the efficiency of optical signal processing.

[0041] It should be noted that the image sensing computing unit of the present disclosure, which can perform in-situ logical operations between light signals, can be described as assuming that illumination is a logical value of "1" and that absence of illumination is a logical value of "0." Therefore, those skilled in the art should understand that if illumination is a logical value of "0" and absence of illumination is a logical value of "1," the image sensing computing unit of the present disclosure implements a logical operation opposite to the aforementioned "illumination is a logical value of '1' and absence of illumination is a logical value of '0'," which will not be further described below.

[0042] like Figure 2-Figure 7 As shown, according to an embodiment of the present disclosure, the first photosensitive unit includes a first transistor, a first buried oxide layer and a first doped well layer.

[0043] A first buried oxide layer is located under the first transistor;

[0044] The first doped well layer is located under the first buried oxide layer.

[0045] like Figure 2-Figure 7 As shown, according to an embodiment of the present disclosure, the second photosensitive unit includes a second transistor, a second buried oxide layer and a second doped well layer.

[0046] The second buried oxide layer is located under the second transistor;

[0047] The second doped well layer is located under the second buried oxide layer.

[0048] like Figure 2-Figure 7 As shown, the photosensitive unit of the embodiment of the present disclosure can be a semiconductor structure in which a transistor and a doped well layer are respectively arranged above and below the buried oxide layer, wherein the semiconductor structure can constitute a photosensitive transistor unit with an ultra-thin body and buried oxide structure, namely a UTBB photosensitive transistor unit. The semiconductor structure also includes a substrate layer for support provided below the doped well layer, and isolation trenches for isolation provided on both sides of the doped well layer. The isolation trenches are generally used as shallow trench isolation to isolate the corresponding photosensitive unit from other adjacent device units. A buried oxide layer is formed on the surface of the doped well layer, and a transistor is formed on the upper surface of the buried oxide layer, thereby constituting the main structure of the photosensitive unit.

[0049] For the same image sensing computing unit, the two first and second photosensitive units connected in series have the same structural form, but may differ in the structural materials and structural function types of certain structural layers. This ensures that the two exhibit threshold voltages that change in different directions when exposed to light. This ensures the in-situ logical processing effect between the optical signals of the image sensing computing unit of the disclosed embodiment.

[0050] like Figure 2-Figure 7 As shown, according to an embodiment of the present disclosure, the first transistor and the second transistor are of different transistor types, and the first doped well layer and the second doped well layer have the same well doping type.

[0051] The transistor type can be an N-type doped or P-type doped field effect transistor, such as NMOS and PMOS; the well doping type can be an n-type doped or p-type doped well structure. Figure 2-Figure 5 As shown, according to the difference in transistor type and well doping type, the above-mentioned photosensitive unit of the embodiment of the present disclosure can be divided into an NMOS transistor 201+p-type doped well layer 203 Np photosensitive unit 200 (such as Figure 2 As shown), NMOS transistor 301+n-type doped well layer 303 Nn photosensitive unit 300 (as shown Figure 3 As shown), PMOS transistor 401+p-type doped well layer 403 Pp photosensitive unit 400 (as shown Figure 4 As shown) and the PMOS transistor 501+n-type doped well layer 503 of the Pn photosensitive unit 500 (as shown Figure 5 ). A buried oxide layer is provided between each transistor and the corresponding doped well layer, such as buried oxide layers 202, 302, 402, and 502. The buried oxide layer can be a highly transparent support layer, such as a silicon dioxide layer, that allows light to pass through and illuminate the doped well layer. Therefore, when configuring the transistor, a light window must be reserved on the surface of the buried oxide layer for light to pass through, so that the transistor is not completely covered by the buried oxide layer.

[0052] Each transistor may have a gate terminal G, a drain terminal D and a source terminal S, and the corresponding doped well layer has a lead terminal B. Specifically, Figure 2 The gate terminal G2, drain terminal D2, source terminal S2 and lead terminal B2 of the Np photosensitive unit are shown as follows: Figure 3 The gate terminal G3, drain terminal D3, source terminal S3 and lead terminal B3 of the Nn photosensitive unit are shown as follows: Figure 4 The gate terminal G4, drain terminal D4, source terminal S4 and lead terminal B4 of the Pp photosensitive unit shown in FIG. Figure 5The gate terminal G5, drain terminal D5, source terminal S5, and lead terminal B5 of the Pn photosensitive unit are shown. As shown in the corresponding equivalent circuit, each photosensitive unit is a circuit form in which the back gate of the transistor unit is connected to a photosensitive capacitor, wherein the capacitance value of the corresponding photosensitive capacitor can decrease as the light effect increases, or can increase as the light effect increases. Preferably, the capacitance value of the photosensitive capacitor corresponding to each of the above-mentioned photosensitive units can decrease as the light effect increases. In this way, it can be ensured that after the corresponding photosensitive units are connected in series, the direction of change of the threshold voltage after being exposed to light is opposite, so as to realize the above-mentioned image sensing operation unit for in-situ optical logic operation.

[0053] Combined with the above Figure 2-Figure 5 The structural composition diagram of the photosensitive unit, the corresponding equivalent circuit diagram and the threshold voltage V of the photosensitive unit are shown in FIG. TH The following is a schematic diagram showing how the light changes, and further explains the working principles of each of the above-mentioned photosensitive units under light:

[0054] like Figure 2 As shown, the doped well layer 203 of the Np photosensitive unit 200 can control the well control voltage V corresponding to the lead terminal B2 during exposure. B <0, a depletion region is generated in the well of the corresponding doped well layer 203 and collects photogenerated electrons, thereby lowering the potential of the depletion region. On the one hand, its equivalent capacitance is reduced, and on the other hand, a back-gate modulation effect is generated on the NMOS transistor 201 above the buried oxide layer 202, making the threshold voltage V TH Increase.

[0055] like Figure 4 As shown, the doped well layer 403 of the Pp photosensitive unit 400 can control the well control voltage V corresponding to the lead terminal B4 during exposure. B <0, a depletion region is generated in the well of the corresponding doped well layer 403 and collects photogenerated electrons, thereby lowering the potential of the depletion region. On the one hand, its equivalent capacitance is reduced, and on the other hand, a back-gate modulation effect is generated on the PMOS transistor above the buried oxide layer 402, making the threshold voltage V TH Decrease.

[0056] like Figure 3 As shown, when the Nn photosensitive unit 300 is exposed, the well control voltage V of the corresponding doped well layer 303 is controlled. B >0, the depletion region of the doped well layer 303 collects photogenerated holes, which will raise the potential of the depletion region and reduce its equivalent capacitance. At the same time, it will produce a back-gate modulation effect on the NMOS transistor 301 that is opposite to the photosensitive unit of the P-type doped well layer, making the threshold voltage V TH Decrease.

[0057] like Figure 5 As shown, when the Pn photosensitive unit 500 is exposed, the well control voltage V of the corresponding doped well layer 503 is controlled. B >0, the depletion region of the doped well layer 503 collects photogenerated holes, which will raise the potential of the depletion region and reduce its equivalent capacitance. At the same time, it will produce a back-gate modulation effect on the PMOS transistor 501 that is opposite to the photosensitive unit of the P-type doped well layer, making the threshold voltage V TH Increase.

[0058] Based on the illumination and threshold voltage V of the photosensitive unit of each transistor type mentioned above TH The corresponding relationship between Figure 6 and Figure 7 The equivalent circuit diagrams of the image sensing computing units of the two different photosensitive units and their corresponding output results are shown. The image sensing computing unit 600 that can implement the "NOR" / "NAND" logic between light signals and the image sensing computing unit 700 that can implement the "OR" / "AND" logic between light signals in the embodiment of the present disclosure are described below.

[0059] like Figure 6 As shown, the image sensing computing unit 600 is connected in series with the Pn photosensitive unit and the Nn photosensitive unit to realize the 'NOR' / 'NAND' logic between the light signals. After the Pn photosensitive unit is exposed, the threshold voltage V TH increases, its equivalent resistance will increase; after the Nn photosensitive unit connected in series with the above-mentioned Pn photosensitive unit is exposed, the threshold voltage V TH decreases, its equivalent resistance will decrease.

[0060] The Pn photosensitive unit and the Nn photosensitive unit are connected in series to realize voltage division. The larger the proportion of the equivalent resistance of the PMOS transistor, the higher the output result V out The smaller the value, the smaller the value. You can set the light input illumination of the photosensitive unit as the logic value '1', and no light as the logic value '0'.

[0061] Therefore, when the two photosensitive units connected in series are both illuminated, that is, when the light input is '1 1', the output voltage V out The output value is the minimum; when only one of the two photosensitive units connected in series is illuminated, that is, when the light input is '1 0' and '0 1', the output voltage V out The output value is second; when the two photosensitive units connected in series are not illuminated, that is, when the light input is '0 0', the output voltage V out The output value is maximum.

[0062] It can be seen that we can further set two different voltage comparison values ​​(such as Figure 6The comparison values ​​1 and 2 are shown to determine the output voltage V of the corresponding image sensing unit. out The logic value represented by the comparison value is greater than the comparison value, and the output is '1', and less than '0'. Two different comparison values ​​can obtain two logical results: 'NOR' or 'NAND'. Among them, setting a larger comparison value 1 makes the output voltage V only when the input is '0 0' out When it is '1', the 'NOR' operation is implemented; on the contrary, setting a smaller comparison value 2 is a 'NAND' operation, which will not be described in detail here.

[0063] like Figure 7 As shown, the image sensing computing unit 700 is connected in series with the Pp photosensitive unit and the Np photosensitive unit to realize the 'OR' / 'AND' logic between the light signals. After the Pp photosensitive unit is exposed, the threshold voltage V TH decreases, its equivalent resistance will decrease; after the Np photosensitive unit connected in series with the above-mentioned Pp photosensitive unit is exposed, the threshold voltage V TH As it increases, its equivalent resistance will increase.

[0064] Therefore, with the above Figure 6 The working principle of the image sensing computing unit 600 is similar, but the functional performance is basically opposite. When the two photosensitive units connected in series are both illuminated, that is, when the light input is '1 1', the output voltage V out The output value is the largest; when only one of the two photosensitive units connected in series is illuminated, that is, when the light input is '1 0' and '01', the output voltage V out The output value is second; when the two photosensitive units connected in series are not illuminated, that is, the logic value of the light input is '0 0', the output voltage V out The output value is minimum.

[0065] It can be seen that we can further set two different voltage comparison values ​​(such as Figure 7 The comparison values ​​3 and 4 shown in the figure can obtain two logical results: 'OR' or 'AND'. Setting a larger comparison value 3 makes the output voltage V only when the input is '1 1'. out When it is '1', the 'AND' operation is implemented, while the smaller comparison value 4 is the 'OR' operation, which will not be described here.

[0066] Therefore, the image sensing computing unit described in the disclosed embodiment can be composed of two ultra-thin body and buried oxide structure photosensitive transistor units (UTBB photosensitive transistor units) with different transistor types but the same well doping type, connected in series. Because the threshold voltages of the two photosensitive units with different transistor types but the same well doping type change in opposite directions when illuminated, their equivalent resistances change in opposite directions when illuminated. When the two are connected in series, the voltage divider relationship between them will also vary depending on the illumination conditions. Therefore, by setting a voltage comparison value, the logic value corresponding to the output voltage value can be determined, thereby enabling in-situ logical operations between optical input signals.

[0067] like Figure 2-Figure 7 As shown, according to an embodiment of the present disclosure, the source of the first transistor is connected to the power supply voltage,

[0068] The drain of the first transistor is connected to the drain of the second transistor,

[0069] The source of the second transistor is grounded;

[0070] The gate of the first transistor is connected to a first gate control voltage, and the gate of the second transistor is connected to a second gate control voltage; and the first doped well layer is connected to the first well control voltage, and the second doped well layer is connected to the second well control voltage.

[0071] like Figure 6 As shown, the image sensing computing unit 600 that can realize the 'NOR' or 'NAND' logical operation between the input light signals can be composed of a Pn photosensitive unit and an Nn photosensitive unit connected in series. DD Its drain is connected to the drain of the Nn photosensitive unit, and the source of the Nn photosensitive unit is grounded. In addition, the gate of the Pn photosensitive unit can be connected to the gate control signal V Gp , the gate of the Nn photosensitive unit is connected to another gate control signal V Gn , as the well electrodes of the doped well layers of the two are connected to the well control signal V B Therefore, when the input of the image sensing computing unit 600 is the incident light of each of the two photosensitive units, the output is the drain voltage corresponding to the Nn photosensitive units.

[0072] like Figure 7 As shown, the image sensing operation unit 700 that can realize the 'OR' or 'AND' logic operation between the input light signals can be composed of a Pp photosensitive unit and an Np photosensitive unit in series, that is, the source of the Pp photosensitive unit is connected to V DD Its drain is connected to the drain of the Np photosensitive unit, and the source of the Np photosensitive unit is grounded. In addition, the gate of the Pp photosensitive unit can be connected to the gate control signal V Gp , the gate of the Np unit can be connected to another gate control signal V Gn, as the well electrodes of the doped well layers of the two are connected to the well control signal V B Therefore, when the input of the image sensing computing unit 700 is the incident light of each of the two photosensitive units, the output is the drain voltage corresponding to the Np photosensitive units.

[0073] On this basis, the output voltage V can be further determined by setting the voltage comparison value. out The system can realize the logical value of 'NOR' / 'NAND' logical operation and 'OR' / 'AND' logical operation between optical signals without the need for additional signal operation processing modules and other circuit components, which simplifies the processing system, shortens the logical operation time, and improves the logical operation efficiency.

[0074] like Figure 8 As shown, another aspect of the present disclosure provides a Figure 1-Figure 7 The operating method of the image sensing computing unit shown includes operations S801-S803.

[0075] In operation S801, an exposure operation is performed on the image sensing operation unit in the off state, so that the equivalent resistance of the first photosensitive unit and / or the second photosensitive unit of the image sensing operation unit changes;

[0076] In operation S802, a first gate control voltage of a first photosensitive unit and / or a second gate control voltage of a second photosensitive unit of an image sensing computing unit that has undergone an exposure operation is controlled to generate an output voltage of the image sensing computing unit, thereby implementing a readout operation on the image sensing computing unit; and

[0077] In operation S803, the first gate-controlled voltage of the first photosensitive unit and / or the second gate-controlled voltage of the second photosensitive unit of the image sensing computing unit that has undergone the readout operation is controlled to turn off the first photosensitive unit and / or the second photosensitive unit; at the same time, the first trap-controlled voltage and / or the second trap-controlled voltage is controlled to implement a reset operation on the image sensing computing unit.

[0078] like Figure 6-Figure 9 As shown, according to an embodiment of the present disclosure, in operation S801, performing an exposure operation on an image sensing operation unit in a turned-off state includes:

[0079] Controlling the first gate control voltage of the first photosensitive unit and / or the second gate control voltage of the second photosensitive unit of the image sensing computing unit so that the first photosensitive unit and / or the second photosensitive unit of the image sensing computing unit are turned off, and the image sensing computing unit is in the off state;

[0080] The first trap-controlled voltage of the first photosensitive unit and / or the second trap-controlled voltage of the second photosensitive unit are controlled to implement an exposure operation.

[0081] Combine Figure 6 or Figure 7 ,like Figure 9 As shown, when the image sensing computing unit of the embodiment of the present disclosure performs an exposure operation, the gate control voltage V of the two photosensitive units connected in series is controlled. Gp >0,V Gn =0, so that the two photosensitive units are turned off and maintain the off state. In this off state, at the same time, for Figure 6 The image sensing computing unit 600 composed of the Pn photosensitive unit and the Nn photosensitive unit controls the well control voltage V corresponding to the two doped well layers. B <0, on this basis, the exposure operation of at least one of the two photosensitive units is maintained; or, in this off state, for Figure 7 The image sensing computing unit 700 composed of the Pp photosensitive unit and the Np photosensitive unit shown controls the corresponding well control voltage V B >0, and on this basis, the exposure operation of at least one of the two photosensitive units is maintained. In this way, the exposure operation of at least one of the two photosensitive units connected in series can be achieved.

[0082] like Figure 6-Figure 9 As shown, according to an embodiment of the present disclosure, in operation S802, controlling the first gate control voltage of the first photosensitive unit and / or the second gate control voltage of the second photosensitive unit of the image sensing computing unit that has undergone the exposure operation to generate the output voltage of the image sensing computing unit includes:

[0083] When the first trap control voltage of the first photosensitive unit and / or the second trap control voltage of the second photosensitive unit remain unchanged, controlling the first gate control voltage and / or the second gate control voltage to turn on the first photosensitive unit and / or the second photosensitive unit;

[0084] The drain voltage between the first photosensitive unit and the second photosensitive unit is read as the output voltage.

[0085] Combine Figure 6 or Figure 7 ,like Figure 9 As shown, when the corresponding image sensing computing unit is performing a readout operation, the corresponding well control voltage V B Keep the value unchanged from the exposure operation, corresponding to the gate control voltage V of two different photosensitive units Gp = 0 and V Gn >0, thereby turning on the two photosensitive units and directly reading the output signal V out The value of .

[0086] like Figure 6-Figure 9As shown, according to an embodiment of the present disclosure, in operation S803, controlling the first gate control voltage of the first photosensitive unit and / or the second gate control voltage of the second photosensitive unit of the image sensing computing unit that has undergone the readout operation to implement a reset operation of the image sensing computing unit includes:

[0087] Controlling the first gate control voltage and / or the second gate control voltage to turn off the first photosensitive unit and / or the second photosensitive unit;

[0088] The first well-controlled voltage and / or the second well-controlled voltage are controlled to implement a reset operation.

[0089] Combine Figure 6 or Figure 7 ,like Figure 9 As shown, when the corresponding image sensing computing unit is performing a reset operation, the gate control voltage V corresponding to the two different photosensitive units Gp >0 and V Gn = 0, turn off the two photosensitive units again. In this open state, at the same time, Figure 6 The image sensing computing unit 600 composed of the Pn photosensitive unit and the Nn photosensitive unit controls the well control voltage V corresponding to the two doped well layers. B >0, thereby resetting each photosensitive unit; or, in this open state, for example Figure 7 The image sensing computing unit 700 composed of the Pp photosensitive unit and the Np photosensitive unit controls the well control voltage V corresponding to the two doped well layers. B <0, thereby achieving the reset of each photosensitive unit. In the process of achieving the reset operation, it is necessary to control the first well-controlled voltage and / or the second well-controlled voltage to be reversed to a voltage value with a polarity opposite to that of the corresponding well-controlled voltage during the exposure operation, so as to ensure the reset.

[0090] Another aspect of the present disclosure provides an image sensor computing unit, comprising an image sensor array composed of the aforementioned image sensor computing units. The image sensor array can simultaneously include N×M of the aforementioned image sensor computing units, that is, 2N×M of the aforementioned photosensitive units. The two photosensitive units in each image sensor computing unit are connected in series, and their respective threshold voltages change in opposite directions when illuminated, thereby enabling in-situ logic operations between corresponding light signals. This allows the image sensor array to directly serve as a logic voltage output device, eliminating the need for additional processing modules.

[0091] Another aspect of the present disclosure provides an electronic device comprising the aforementioned image sensor computing unit. The electronic device may be a device capable of at least one of optical communication and optical imaging, such as an optical communication laser device, to implement image perception and processing functions such as face recognition and fingerprint recognition. It may also be a portable intelligent electronic device such as a laptop, computer, iPad, or smartphone, thus being well-suited for applications in surveillance, security, human-computer interaction, and other fields, without limitation.

[0092] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0093] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An image sensing computing unit, wherein: include: a first photosensitive unit, and A second photosensitive unit is connected in series with the first photosensitive unit. The direction of change of the first threshold voltage of the first photosensitive unit when receiving light is opposite to the direction of change of the second threshold voltage of the second photosensitive unit when receiving light, and their corresponding equivalent resistances also have different change directions; The light exposure conditions of the first photosensitive unit and the second photosensitive unit are independent of each other, and their respective equivalent resistances in the series circuit determine the voltage division relationship; The output voltage of the image sensing operation unit is determined by the voltage division relationship, and a corresponding output voltage is generated according to the combination of the illumination conditions of the first photosensitive unit and the second photosensitive unit to realize in-situ logic operation between the optical input signals.

2. The image sensing computing unit according to claim 1, wherein: The first photosensitive unit includes: The first transistor, a first buried oxide layer, located under the first transistor; The first doped well layer is located under the first buried oxide layer.

3. The image sensing computing unit according to claim 2, wherein: The second photosensitive unit includes: The second transistor, a second buried oxide layer, located under the second transistor; The second doped well layer is located under the second buried oxide layer.

4. The image sensing computing unit according to claim 3, wherein: The first transistor and the second transistor are of different transistor types, and the first doped well layer and the second doped well layer have the same well doping type.

5. The image sensing computing unit according to claim 3, wherein: The source of the first transistor is connected to the power supply voltage, The drain of the first transistor is connected to the drain of the second transistor, The source of the second transistor is grounded; The gate of the first transistor is connected to a first gate control voltage, and the gate of the second transistor is connected to a second gate control voltage; and the first doped well layer is connected to the first well control voltage, and the second doped well layer is connected to the second well control voltage.

6. An operating method of the image sensing computing unit according to any one of claims 1 to 5, wherein: include: Performing an exposure operation on the image sensing computing unit in the off state, so that the equivalent resistance of the first photosensitive unit and / or the second photosensitive unit of the image sensing computing unit changes; Controlling a first gate control voltage of a first photosensitive unit and / or a second gate control voltage of a second photosensitive unit of the image sensing computing unit that has undergone the exposure operation to generate an output voltage of the image sensing computing unit, thereby implementing a readout operation on the image sensing computing unit; and Control the first gate-controlled voltage of the first photosensitive unit and / or the second gate-controlled voltage of the second photosensitive unit of the image sensing computing unit that has undergone the readout operation to turn off the first photosensitive unit and / or the second photosensitive unit; and at the same time control the first trap-controlled voltage and / or the second trap-controlled voltage to realize the reset operation of the image sensing computing unit.

7. The operating method according to claim 6, wherein: The step of performing an exposure operation on the image sensing computing unit in the off state includes: Controlling the first gate control voltage of the first photosensitive unit and / or the second gate control voltage of the second photosensitive unit of the image sensing computing unit so that the first photosensitive unit and / or the second photosensitive unit of the image sensing computing unit are turned off, and the image sensing computing unit is in the off state; The exposure operation is achieved by controlling the first trap-controlled voltage of the first photosensitive unit and / or the second trap-controlled voltage of the second photosensitive unit.

8. The operating method according to claim 6, wherein: In the step of controlling the first gate control voltage of the first photosensitive unit and / or the second gate control voltage of the second photosensitive unit of the image sensing computing unit after the exposure operation to generate the output voltage of the image sensing computing unit, the step includes: When the first trap control voltage of the first photosensitive unit and / or the second trap control voltage of the second photosensitive unit remain unchanged, controlling the first gate control voltage and / or the second gate control voltage to turn on the first photosensitive unit and / or the second photosensitive unit; A drain voltage between the first photosensitive unit and the second photosensitive unit is read as the output voltage.

9. An image sensor computing unit, wherein: An image sensing array comprising a plurality of image sensing computing units according to any one of claims 1 to 5.

10. An electronic device, wherein: Includes the image sensor computing unit described in claim 9.

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