Power management chip and information sampling device thereof

Abstract

Provided are a power management chip and an information sampling device thereof. The information sampling device used in the power management chip includes a sampling control circuit and an information storage circuit. The sampling control circuit is configured to shield pin information at specific pins of the power management chip or transmit the pin information to the information storage circuit based on an internal control signal associated with external interference in the power management chip; and the information storage circuit is configured to store the pin information and transmit the pin information to other circuits in the power management chip.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and more particularly to a power management chip and an information sampling device thereof. Background Art

[0002] Electronic devices have become an indispensable item in people's lives, and power management chips are an indispensable component of electronic devices. Therefore, the working performance of power management chips directly affects the overall working performance of electronic devices, thereby affecting people's experience of using electronic devices and thus affecting people's daily lives. Summary of the Invention

[0003] According to an embodiment of the present invention, an information sampling device used in a power management chip includes a sampling control circuit and an information storage circuit, wherein: the sampling control circuit is configured to shield pin information at a specific pin of the power management chip or transmit the pin information to the information storage circuit based on an internal control signal associated with external interference in the power management chip; and the information storage circuit is configured to store the pin information and transmit the pin information to other circuits in the power management chip.

[0004] A power management chip according to an embodiment of the present invention includes the above-mentioned information sampling device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0006] Figure 1 A system diagram of an example power management chip for LED lighting is shown.

[0007] Figure 2 Shown Figure 1 The waveform diagram of the relevant signals when the power management chip is interfered by switch coupling is shown.

[0008] Figure 3 An exemplary block diagram of an information sampling device used in a power management chip according to an embodiment of the present invention is shown.

[0009] Figure 4 Shown Figure 3 An example implementation block diagram of the information sampling device is shown.

[0010] Figure 5 Shown Figure 4 The information sampling device shown is applied to Figure 1 The waveform diagram of the relevant signals of the power management chip shown.

[0011] Figure 6 Shown Figure 3Another example implementation block diagram of the information sampling device is shown.

[0012] Figure 7 Shown Figure 3 Another example implementation block diagram of the information sampling device is shown. DETAILED DESCRIPTION

[0013] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement, and improvement of elements, components, and algorithms without departing from the spirit of the present invention. In the accompanying drawings and the following description, known structures and techniques are not shown to avoid causing unnecessary ambiguity to the present invention.

[0014] Figure 1 FIG. 1 shows a system diagram of a power management chip 100 for LED lighting. Figure 1 As shown, the power management chip 100 includes an information sampling module 102, a function execution module 104, a constant current control module 106, and a switch tube M, wherein: the information sampling module 102 samples external voltage, current, or impedance information via pin 1, and converts the sampled information into voltage, current, or digital logic signals and transmits them to the function execution module 104; the function execution module 104 performs corresponding actions based on the signals from the information sampling module 102, such as overvoltage protection action, overtemperature protection action, etc.; the constant current control module 106 controls the conduction and shutdown of the switch tube M based on the current flowing through the switch tube M, so as to keep the current flowing through the LED load constant.

[0015] Figure 2 Shown Figure 1 The waveform diagram of the relevant signals when the power management chip 100 is interfered by the switch coupling is shown in FIG. 1 , wherein Gate represents the gate voltage of the switch tube M, Drain represents the drain voltage of the switch tube M, and Pin1 represents the pin voltage at pin 1. Figure 2 As shown, when the power management chip 100 is in sleep mode, the gate voltage Gate of the switch tube M is at a low level (that is, the switch tube M is in the off state), the drain voltage Drain of the switch tube M is at a high voltage level HV, and the pin voltage Pin1 at pin 1 is at a DC level Vpin.

[0016] like Figure 2As shown, when the power management chip 100 is in the working mode, due to the parasitic capacitance between the drain of the switch tube M and pin 1, when the gate voltage Gate of the switch tube M changes from a low level to a high level and the drain voltage Drain of the switch tube M changes from a high voltage level HV to a low voltage level V0, the pin voltage Pin1 at pin 1 is coupled to a voltage V2 lower than the DC level Vpin; when the gate voltage Gate of the switch tube M changes from a high level to a low level and the drain voltage Drain of the switch tube M changes from a low voltage level V0 to a high voltage level HV, the pin voltage Pin1 on pin 1 is coupled to a voltage V1 higher than the DC level Vpin.

[0017] for Figure 1 When various interferences including switch coupling interference occur in the external circuit of the power management chip 100 shown, if the information sampling module 102 does not include relevant anti-interference measures, it is possible to sample erroneous information, which may cause the function execution module 104 to perform erroneous actions, which may cause damage to the chip in some cases.

[0018] In view of the above situation, an information sampling device for use in a power management chip according to an embodiment of the present invention is proposed, which can sample pin information (e.g., current, voltage, or impedance information) at specific pins of the power management chip without external interference.

[0019] Figure 3 FIG. 3 shows an example block diagram of an information sampling device 300 used in a power management chip according to an embodiment of the present invention. Figure 3 As shown, the information sampling device 300 includes a sampling control circuit 302 and an information storage circuit 304, wherein: the sampling control circuit 302 is configured to shield the pin information (hereinafter referred to as pin information Pin_Info) at a specific pin (hereinafter referred to as pin Pin_s) of the power management chip based on an internal control signal (hereinafter referred to as internal control signal Ctr_in) associated with external interference in the power management chip, or transmit the pin information Pin_Info to the information storage circuit 304; and the information storage circuit 304 is configured to store the pin information Pin_Info and transmit the pin information Pin_Info to other circuits in the power management chip.

[0020] In some embodiments, the sampling control circuit 302 is further configured to: shield the pin information Pin_Info when the internal control signal Ctr_in indicates the presence of external interference; and transfer the pin information Pin_Info to the information storage circuit 304 when the internal control signal Ctr_in indicates the absence of external interference.

[0021] In some embodiments, the information storage circuit 304 is further configured to: when the internal control signal Ctr_in indicates the presence of external interference, transmit the pin information Pin_Info transmitted to it by the sampling control circuit 302 when the internal control signal Ctr_in indicates the absence of external interference to other circuits in the power management chip.

[0022] For example, when the information sampling device 300 is applied to Figure 1 In the case of the power management chip 100 shown, the gate voltage Gate at pin 1 can be used as an internal control signal Ctr_in to indicate whether there is switch coupling interference outside the power management chip 100. When there is no switch coupling interference outside the power management chip 100 (i.e., the gate voltage Gate of the switch transistor M is stable at a high level or a low level), the sampling control circuit 302 can transmit the pin information at pin 1 to the information storage circuit 304, and the information storage circuit 304 can store the pin information at pin 1 and transmit it to other circuits in the power management chip 100. When there is switch coupling interference outside the power management chip 100 (i.e., the gate voltage Gate of the switch transistor M changes from a high level to a low level or from a low level to a high level), the sampling control circuit 302 can shield the pin information at pin 1, and the information storage circuit 304 can transmit the pin information at pin 1 that was transmitted to it by the sampling control circuit 302 before the switch coupling interference occurred to other circuits in the power management chip 100. In this way, the pin information at the pin 1 can be sampled without being interfered by the switch coupling, thereby preventing the power management chip 100 from malfunctioning.

[0023] Figure 4 Shown Figure 3 The example implementation block diagram of the information sampling device 300 is shown in FIG. Figure 4 As shown, sampling control circuit 302 includes control logic and a transmission gate, wherein: the control logic is configured to generate a sampling control signal based on an internal control signal Ctr_in; and the transmission gate is configured to, under the control of the sampling control signal, shield the pin information Pin_Info or transmit the pin information Pin_Info to the information storage circuit 304. Here, information sampling apparatus 300 can implement sampling, storage, and transmission of voltage information at pin Pin_s. Information storage circuit 304 can include a capacitor connected between the output terminal of sampling control circuit 302 and ground.

[0024] exist Figure 4In the illustrated information sampling device 300 , the control logic includes, for example, a pulse generator and an inverter. The pulse generator is configured to generate a first sampling control signal A based on an internal control signal Ctr_in, and the inverter is configured to generate a second sampling control signal B based on the first sampling control signal A (i.e., the second sampling control signal B is an inverted signal of the first sampling control signal A). In this case, under the control of the first sampling control signal A and the second sampling control signal B, the transmission gate masks the pin information Pin_Info or transmits the pin information Pin_Info to the information storage circuit 304 .

[0025] Figure 5 Shown Figure 4 The information sampling device 300 shown is applied to Figure 1 1 is a waveform diagram of relevant signals of the power management chip 100 shown in FIG. 1 , wherein Gate represents the gate voltage of the switch tube M, Pin1 represents the pin voltage at pin 1 of the power management chip 100, A represents the first sampling control signal, B represents the second sampling control signal, and the pin information represents the voltage information at pin 1 of the power management chip 100 transmitted to the information storage circuit 304 by the sampling control circuit 302.

[0026] like Figure 5 As shown, when there is switch coupling interference outside the power management chip 100, the gate voltage Gate of the switch tube M will switch from a low level to a high level or from a high level to a low level. Therefore, the gate voltage Gate of the switch tube M can be used as the internal control signal Ctr_in to perform anti-interference sampling on the pin voltage Pin1 at pin 1.

[0027] Combine Figure 1 、 Figure 4 ,and Figure 5It can be seen that when the gate voltage Gate of the switch tube M is at a high level or a low level, the pin voltage Pin1 at pin 1 of the power management chip 100 is stable at a DC level Vpin. At this time, the first sampling control signal A is at a low level, and the second sampling control signal B is at a high level. The information storage circuit 304 stores the DC level Vpin and transmits it to other circuits in the power management chip 100. When the gate voltage Gate of the switch tube M changes from a low level to a high level, the first sampling control signal A changes from a low level to a high level and remains at the high level for a duration t1, and the second sampling control signal B changes from a high level to a low level and remains at the low level for a duration t1. The sampling control circuit 302 shields the pin voltage Pin1 at pin 1 of the power management chip 100 during time t1. The information storage circuit 304 transmits the pin voltage Pin1 transmitted to it by the sampling control circuit 302 before the switch coupling interference occurs to other circuits in the power management chip 100. When the gate voltage Gate of the switch tube M changes from a high level to a low level, the first sampling control signal A changes from a low level to a high level and remains at the high level for a duration of t2, and the second sampling control signal B changes from a high level to a low level and remains at the low level for a duration of t2. During time t2, the sampling control circuit 302 shields the pin voltage Pin1 at pin 1 of the power management chip 100, and the information storage circuit 304 transmits the pin voltage Pin1 transmitted to it by the sampling control circuit 302 before the switch coupling interference occurs to other circuits in the power management chip 100. In other words, the information sampling device 300 can stably provide pin information at pin 1 of the power management chip 100 that is not subject to external interference to other circuits in the power management chip 100.

[0028] Figure 6 Shown Figure 3 Another example implementation block diagram of the information sampling device 300 is shown. Figure 6 As shown, sampling control circuit 302 includes control logic, a comparator, and an AND gate, wherein: the control logic is configured to generate a sampling control signal based on an internal control signal Ctr_in; the comparator is configured to generate a pin information characterizing signal Pin_Info_s based on pin information Pin_Info and a reference voltage Vref; and the AND gate is configured, under the control of the sampling control signal, to shield the pin information characterizing signal Pin_Info_s or transmit the pin information characterizing signal Pin_Info_s to information storage circuit 304. Here, information sampling apparatus 300 can implement sampling, storage, and transmission of voltage information at pin Pin_s by converting the voltage information at pin Pin_s into the pin information characterizing signal Pin_Info_s for storage and transmission. Information storage circuit 304 may include an inverter and two NOR gates.

[0029] exist Figure 6 In the illustrated information sampling device 300, the control logic includes, for example, a pulse generator and an inverter, wherein: the pulse generator is configured to generate a first sampling control signal A based on an internal control signal Ctr_in; and the inverter is configured to generate a second sampling control signal B based on the first sampling control signal A (i.e., the second sampling control signal B is an inverted signal of the first sampling control signal A). In this case, under the control of the second sampling control signal B, the AND gate masks the pin information characterization signal Pin_Info_s or transmits the pin information characterization signal Pin_Info_s to the information storage circuit 304. The information storage circuit 304, under the control of the second sampling control signal B, stores the pin information characterization signal Pin_Info_s and transmits the pin information characterization signal Pin_Info_s to other circuits in the power management chip.

[0030] Specifically, in Figure 6In the illustrated information sampling device 300, a comparator compares the pin voltage at pin Pin_s with a reference voltage Vref. When the pin voltage at pin Pin_s is greater than the reference voltage Vref, the comparator outputs a high level (i.e., the pin information characterization signal Pin_Info_s is high), and when the pin voltage at pin Pin_s is lower than the reference voltage Vref, the comparator outputs a low level (i.e., the pin information characterization signal Pin_Info_s is low). When the internal control signal Ctr_in is at a low level or a high level (i.e., not switching between high and low levels), the second sampling control signal B is high, and the pin information characterization signal Pin_Info_s output by the comparator is transmitted to the information storage circuit 304 via an AND gate. The information storage circuit 304 stores the pin information characterization signal Pin_Info_s and transmits it to other circuits in the power management chip. When the internal control signal Ctr_in changes from a high level to a low level or from a low level to a high level, the second sampling control signal B changes from a high level to a low level. The pin information characterizing signal Pin_Info_s output by the comparator cannot be transmitted to the information storage circuit 304 through the AND gate (i.e., the pin information characterizing signal Pin_Info_s is shielded). The information storage circuit 304 transmits the pin information characterizing signal Pin_Info_s stored before the second sampling control signal B changes to a low level to other circuits in the power management chip. In other words, when there is no interference outside the power management chip, the information sampling device 300 can sample, store, and transmit the voltage information at pin Pin_s by converting the voltage information at pin Pin_s into the pin information characterizing signal Pin_Info_s for storage and transmission. When there is interference outside the power management chip, the information sampling device 300 can shield the voltage information at pin Pin_s and transmit the pin information characterizing signal Pin_Info_s stored before the external interference occurs to other circuits in the power management chip.

[0031] Figure 7 Shown Figure 3 Another example implementation block diagram of the information sampling device 300 is shown. Figure 6As shown, sampling control circuit 302 includes control logic, a voltage regulator, and a transmission gate, wherein: the control logic is configured to generate a sampling control signal based on an internal control signal Ctr_in; the voltage regulator is configured to generate a pin information representative current Pin_Info_I based on pin information Pin_Info and a reference voltage Vref; and the transmission gate is configured to, under the control of the sampling control signal, shield the pin information representative current Pin_Info_I or transmit the pin information representative current Pin_Info_I to information storage circuit 304. Here, information sampling apparatus 300 can implement sampling, storage, and transmission of impedance information at pin Pin_s by converting the impedance information at pin Pin_s into the pin information representative current Pin_Info_I for storage and transmission.

[0032] exist Figure 7 In the illustrated information sampling device 300 , the control logic includes, for example, a pulse generator and an inverter. The pulse generator is configured to generate a first sampling control signal A based on an internal control signal Ctr_in, and the inverter is configured to generate a second sampling control signal B based on the first sampling control signal A. In this case, under the control of the first sampling control signal A and the second sampling control signal B, the transmission gate shields the pin information representative current Pin_Info_I or transmits the pin information representative current Pin_Info_I to the information storage circuit 304 .

[0033] Specifically, in Figure 7In the illustrated information sampling device 300, a voltage regulator adjusts the pin information representing current Pin_Info_I flowing from pin Pin_s based on the impedance information at pin Pin_s. The voltage regulator includes a first diode-connected switch M1. The pin information representing current Pin_Info_I flows through the first switch M1, forming a voltage V1 at the gate of the first switch M1. This voltage V1 can be transmitted to the information storage circuit 304 via a transmission gate. The information storage circuit 304 can include a capacitor C2 and a second switch M2 for storing the pin information representing current Pin_Info_I. The width-to-length ratio of the second switch M2 is the same as that of the first switch M1. The gate voltage V1 of the first switch M1 can be transmitted to the gate of the second switch M2 via a transmission gate, thereby ensuring that the current I2 flowing out of the second switch M2 is the same as the current I1 flowing into the first switch M1. When the internal control signal Ctr_in is at a low level or a high level (i.e., not switching between high and low levels), the first sampling control signal A is at a low level, the second sampling control signal B is at a high level, and the pin information current Pin_Info_I is transmitted through the transmission gate to the information storage circuit 304. The information storage circuit 304 stores the pin information current Pin_Info_I and transmits it to other circuits in the power management chip. When the internal control signal Ctr_in changes from a high level to a low level or from a low level to a high level, the first sampling control signal A changes from a low level to a high level, and the second sampling control signal B changes from a high level to a low level. The pin information current Pin_Info_I cannot be transmitted through the transmission gate to the information storage circuit 304 (i.e., the pin information current Pin_Info_I is blocked). The information storage circuit 304 transmits the pin information current Pin_Info_I stored before the second sampling control signal B changes to a low level to other circuits in the power management chip. That is, when there is no external interference to the power management chip, the information sampling device 300 can sample, store, and transmit the impedance information at pin Pin_s by converting the impedance information at pin Pin_s into a pin information representative current Pin_Info_I for storage and transmission. When there is external interference to the power management chip, the information sampling device 300 can shield the impedance information at pin Pin_s and transmit the pin information representative current Pin_Info_I stored before the external interference occurs to other circuits in the power management chip.

[0034] In summary, according to an embodiment of the present invention, the information sampling device can shield the pin information Pin_Info at pin Pin_s when there is interference outside the power management chip, and transmit the pin information Pin_Info sampled and stored before the external interference occurs to other circuits in the power management chip. Then, after a preset time, when the external interference ends, the sampling, storage, and transmission of the pin information Pin_Info are resumed. In this way, the information sampling device 300 can stably provide pin information at pin Pin_s of the power management chip that is not subject to external interference to other circuits in the power management chip.

[0035] The present invention may be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the present invention. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention is defined by the appended claims rather than the foregoing description, and all modifications coming within the meaning and scope of equivalents of the claims are intended to be included within the scope of the present invention.

Claims

1. An information sampling device for a power management chip, comprising a sampling control circuit and an information storage circuit, wherein the sampling control circuit includes a pulse generator and an inverter, wherein the pulse generator is configured to generate a first sampling control signal based on an internal control signal associated with external interference in the power management chip, and the inverter is configured to generate a second sampling control signal based on the first sampling control signal, wherein: The sampling control circuit is configured to, under the control of the first sampling control signal and the second sampling control signal or under the control of the second sampling control signal, transfer the pin information at the specific pin of the power management chip to the information storage circuit when the internal control signal indicates that there is no external interference, and shield the pin information when the internal control signal indicates that there is external interference; The information storage circuit is configured to store the pin information and transmit the pin information to other circuits in the power management chip when the internal control signal indicates that external interference exists.

2. The information sampling device according to claim 1, wherein: The sampling control circuit further includes a transmission gate configured to shield the pin information or transmit the pin information to the information storage circuit under the control of the first sampling control signal and the second sampling control signal.

3. The information sampling device according to claim 2, wherein: The information storage circuit includes a capacitor connected between an output terminal of the sampling control circuit and ground.

4. The information sampling device according to claim 1, wherein: The sampling control circuit further includes a comparator and an AND gate, wherein: The comparator is configured to generate a pin information representative signal based on the pin information and a reference voltage; and The AND gate is configured to shield the pin information characterizing signal or transmit the pin information characterizing signal to the information storage circuit under the control of the second sampling control signal.

5. The information sampling device according to claim 4, wherein: The information storage circuit includes an inverter and two NOR gates.

6. The information sampling device according to claim 4, wherein: Under the control of the second sampling control signal, the information storage circuit stores the pin information characterizing signal and transmits the pin information characterizing signal to other circuits in the power management chip.

7. The information sampling device according to claim 1, wherein: The sampling control circuit further includes a voltage regulator and a transmission gate, wherein: The voltage regulator is configured to generate a pin information representative current based on the pin information and a reference voltage; and The transmission gate is configured to shield the pin information representative current or transfer the pin information representative current to the information storage circuit under the control of the first sampling control signal and the second sampling control signal.

8. The information sampling device according to claim 7, wherein: The voltage regulator includes a first switching tube, the information storage circuit includes a capacitor and a second switching tube, and the width-to-length ratio of the second switching tube is equal to the width-to-length ratio of the first switching tube.

9. A power management chip, comprising the information sampling device according to any one of claims 1 to 8.

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