A PMR function optimization method for SSD

Abstract

The present invention discloses a method for optimizing the PMR function of an SSD. This method designs a linkage module. After power-on initialization and activation, the linkage module automatically restores data stored in the NAND flash to the DDR corresponding to the PMR function. Upon power-off, the linkage module saves the data from the DDR to the pre-erased NAND flash. This method also categorizes and stores data in the PMR area, synchronously updating frequently accessed data in the PMR to MRAM for permanent storage, while saving less frequently accessed data in the DDR. Upon power-off, less frequently accessed data is stored in the NAND flash. This method optimizes both power-on recovery and power-off preservation, accelerating data recovery and preservation in the PMR area and enhancing data preservation security.

Description

Technical Field

[0001] The present invention relates to the field of solid-state storage, and in particular to a method for optimizing the PMR function of an SSD. Background Art

[0002] PMR (Persistent Memory Region) is a persistent memory feature of NVMe SSDs. When an SSD supports PMR, the host allocates a BAR space address to the SSD. Data read or written through this address falls within the SSD's PMR region, which is responsible for data storage and recovery. Unlike Nand Flash, the PMR region provides non-volatile data storage without the many limitations of flash memory (such as erase-before-write and page-based operations). This makes it particularly suitable for random data reads and writes and frequently changing data, effectively reducing the SSD's write amplification. Traditional designs map the PMR region to the SSD's DDR cache, then save the data from DDR to Nand Flash upon a power outage. This approach requires software intervention, is slow, and places pressure on handling abnormal power outages. Summary of the Invention

[0003] In response to the shortcomings of the existing technology, the present invention provides a method for optimizing the PMR function of an SSD, which optimizes both power-on recovery and power-off preservation, thereby accelerating the data recovery and preservation speed of the PMR area and enhancing the security of data preservation.

[0004] To address the aforementioned technical issues, the present invention employs a technical solution: a method for optimizing the PMR function of an SSD. This method employs a linkage module, a hardware module that enables automated hardware storage and data migration, achieving greater speed than existing methods. After power-on initialization, the linkage module automatically restores data stored in the NAND flash to the DDR corresponding to the PMR function. Upon power-off, the linkage module saves the data from the DDR to the pre-erased NAND flash. This method also categorizes and stores data in the PMR region, synchronously updating frequently accessed data in the PMR to MRAM for permanent storage, while storing less frequently accessed data in the DDR. Upon power-off, less frequently accessed data is stored in the NAND flash.

[0005] Furthermore, data classification and storage in the PMR area is accomplished through a self-optimizing algorithm, which includes a PMR active data index, adaptive granularity, and data queues. The PMR active data index establishes a relationship between the offset address, access count, and time of data within the PMR, reflecting the activity level of the data within the PMR. The offset address with the highest number of accesses per unit time is identified as active data. Adaptive granularity uses an adaptive algorithm to count the read and write volume of PMR data sent by the host and predict the most appropriate granularity. The data queue is used to store received and to-be-sent data packets. The receiving data queue is divided into active and inactive queues based on data activity. After the data classification module classifies data based on the activity index, the address translation module converts the address and places the corresponding data into active and inactive queues respectively. The data in the active queue is moved to MRAM, and the data in the inactive queue is moved to DDR.

[0006] Furthermore, the address translation module is used to convert the data sent by the host into the bus address inside the SSD for data routing; the address translation module integrates address routing rules. The address routing rules are based on the activity of PMR data. The data address range with high activity is translated into the address space where the MRAM is located; the data address range with low activity is translated into the address space where the DDR is located. At the same time, a table of address mapping relationships between PMR addresses and granularity units is established.

[0007] Furthermore, the PMR area is divided into N segments, the initial granularity of the PMR area is set to N, the initial access count is 0, and the adaptive granularity uses an adaptive algorithm to count the read and write volume of the PMR data sent by the host, and optimize and learn based on the size of frequently accessed units (units where active data is located), adaptively adjust the size of the granularity unit, and dynamically adjust the size of N.

[0008] Furthermore, when powered on, the linkage module automatically reads the PMR data from the NAND flash into the DDR according to the address mapping table between the PMR granularity unit and the Nand Flash physical unit; when powered off, the linkage module saves the data from the DDR into the pre-erased NAND flash and updates the address mapping table between the PMR granularity unit and the Nand Flash physical unit.

[0009] Furthermore, MRAM and DDR use DMA modules as data movement engines.

[0010] Furthermore, the specific process of power-on data recovery is as follows:

[0011] S11), power on, initialize the linkage module to dual base address mode;

[0012] S12), recovering initialization information from the nand flash, the initialization information including PMR data distribution variables, the PMR data distribution variables including mapping tables and other management variables;

[0013] S13) Configure the linkage module, which automatically reads the data stored in the nand flash;

[0014] S14) Restore the inactive PMR data of the linkage module to the DDR automatically;

[0015] S15), configure the bus address translation unit of the PCIe module to map the PMR address domain to the MRAM and DDR respectively;

[0016] S16) Enable the NVMe PMR function and wait for host access.

[0017] Furthermore, the specific process of PMR regional data classification storage is as follows:

[0018] S21), the host accesses the PMR, and the data classification module counts the access to the PMR data and calculates the PMR active data indicators;

[0019] S22) Determine whether it is the first access. If yes, translate to the active data queue by default. If not, distinguish the active data according to the active data index and execute step S23);

[0020] S23), determine whether it is active data, if yes, translate the data into MRAM address, if not, translate the data into DDR address;

[0021] S24), update granularity to a chart;

[0022] S25), adaptive algorithm update granularity;

[0023] S25), update the active data index and return to step S23).

[0024] Furthermore, the specific process of data preservation after power-off is as follows:

[0025] S31) Power off and turn off the PMR function;

[0026] S32) Save PMR data granularity and data distribution variables to nand flash;

[0027] S33) Configure the linkage module to save inactive data to nand flash;

[0028] S34) Complete other processes for powering off the SSD.

[0029] Beneficial effects of the present invention: Compared with traditional PMR designs, the present invention can realize classified storage of PMR data and optimize the permanent preservation performance of written data. At the same time, a hardware linkage module is designed for power-on data recovery and power-off data preservation, which effectively shortens the time for data recovery and preservation, greatly reduces the data storage pressure during abnormal power-off, and improves the performance of PMR. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of an SSD storage system;

[0031] Figure 2 This is a flowchart for power-on data recovery;

[0032] Figure 3 Flowchart for classification and storage of PMR regional data;

[0033] Figure 4 This is a flowchart for saving power-off data. DETAILED DESCRIPTION

[0034] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0035] Example 1

[0036] This embodiment discloses a method for optimizing the PMR function of an SSD. This method designs a hardware linkage module for power-on data recovery and power-off data preservation. The linkage module is a hardware module that can realize hardware automatic storage and data migration, which is faster than existing methods. When power is turned on, the data saved in the nand flash is automatically restored to the DDR corresponding to the PMR function, effectively shortening the data recovery time; when power is turned off, the data in the DDR is moved to the fixed physical unit of the Nand Flash, effectively shortening the data preservation time. Secondly, for data preservation, this method classifies and stores the data in the PMR area, synchronously updates the data frequently accessed by the PMR to the MRAM for permanent storage, and the data that is not frequently accessed will be stored in the Nand Flash when power is turned off, greatly reducing the data storage pressure during abnormal power-off.

[0037] This method is implemented based on Figure 1 The SSD storage system shown in the figure adds a data classification module, a linkage module and MRAM on the basis of the existing SSD storage system. The MRAM is a non-volatile cache memory used for non-volatile storage of data.

[0038] The linkage module is used to automatically move DDR data between Nand Flash and Nand Flash. The linkage module includes a Nand Flash driver and a DMA unit. When the linkage module is initialized and activated upon power-up, it automatically moves the PMR data stored in Nand Flash to the DDR. At power-down, the DDR data is moved to fixed physical units in Nand Flash. The linkage module uses an address mapping table between PMR granularity units and Nand Flash physical units to determine the address correspondence between Nand Flash physical units and DDR space. Specifically, at power-up, the module automatically reads PMR data from Nand Flash into the DDR based on the address mapping table between PMR granularity units and Nand Flash physical units. At power-down, the module saves the data from the DDR to pre-erased Nand Flash and updates the address mapping table between PMR granularity units and Nand Flash physical units. If a read error occurs during power-up, a hardware interrupt is triggered, notifying the CPU firmware of the error address information. The firmware then configures the PMR register to notify the host.

[0039] The data classification module is used to classify and store PMR data sent by the host. Specifically, high-activity data is stored in MRAM, while low-activity data is stored in DDR. This data classification module uses a self-optimizing algorithm for data classification.

[0040] In this embodiment, the self-optimization algorithm includes a PMR activity index, adaptive granularity, and data queues. The PMR activity index establishes a relationship between data offsets within the PMR, access counts, and time. This relationship reflects the activity of data within the PMR. Specifically, the offsets with the highest number of accesses per unit time are considered active data.

[0041] Granularity determines the data block size when saving and restoring data to NAND. Adaptive granularity uses an adaptive algorithm to calculate the read and write volume of PMR data sent by the host and predict the most appropriate granularity. Specifically, the PMR area is divided into N segments, with the initial granularity set to N and the initial access count to 0. Adaptive granularity uses an adaptive algorithm to calculate the read and write volume of PMR data sent by the host. It then optimizes and learns based on the size of frequently accessed units (units containing active data), adaptively adjusting the granularity unit size and dynamically adjusting the size of N.

[0042] The data queue is used to store received and to-be-sent data packets. The data queue in the receiving direction is divided into active queue and inactive queue according to the data activity. After the data classification module classifies the data according to the activity index, the address translation module converts the address and puts the corresponding data into the active queue and inactive queue respectively. The data in the active queue is moved to MRAM by the DMA unit, and the data in the inactive queue is moved to DDR by the DMA unit.

[0043] The implementation of data queues can not only complete data classification, but also reduce the data flow pressure of the PCIe interface and ensure the bandwidth of PMR access; the adaptive granularity is maintained by an adaptive algorithm.

[0044] The above process involves an address translation module and address routing rules. The address translation module converts data addresses sent by the host into bus addresses within the SSD for data routing. The address routing rules are based on the PMR classification module's algorithm. High-activity data address ranges are translated into the MRAM address space, while low-activity data address ranges are translated into the DDR address space. A table mapping PMR addresses to granularity units is created. The address translation module implements address routing. Data activity classification, as determined by the data classification module, is converted into different addresses recognized by the SSD's internal bus, enabling automatic routing of PMR data.

[0045] This embodiment features a DMA unit, which acts as the engine for data movement between MRAM and DDR. When the designed MRAM space is smaller than the PMR space, an MRAM flush mechanism is required, which is handled by the internal DMA. Flushing granular unit data to the DDR will simultaneously modify the PMR address and granular unit address mapping table.

[0046] like Figure 2 As shown in the figure, the specific process of power-on data recovery is as follows:

[0047] S11), power on, initialize the linkage module to dual base address mode;

[0048] S12), restore initialization information from nand flash, the initialization information includes PMR data distribution variables;

[0049] S13) Configure the linkage module, which automatically reads the data stored in the nand flash;

[0050] S14) Restore the inactive PMR data of the linkage module to the DDR automatically;

[0051] S15), configure the bus address translation unit of the PCIe module to map the PMR address domain to the MRAM and DDR respectively;

[0052] S16) Enable the NVMe PMR function and wait for host access.

[0053] like Figure 3 As shown in the figure, the specific process of PMR regional data classification storage is as follows:

[0054] S21), the host accesses the PMR, and the data classification module counts the access to the PMR data and calculates the PMR active data indicators;

[0055] S22) Determine whether it is the first access. If yes, translate to the active data queue by default. If not, distinguish the active data according to the active data index and execute step S23);

[0056] S23), determine whether it is active data, if yes, translate the data into MRAM address, if not, translate the data into DDR address;

[0057] S24), update granularity to a chart;

[0058] S25), adaptive algorithm update granularity;

[0059] S25), update the active data index and return to step S23).

[0060] like Figure 4 As shown in the figure, the specific process of data power-off preservation is as follows:

[0061] S31) Turn off the power and disable the PMR function;

[0062] S32) Save PMR data granularity and data distribution variables to nand flash;

[0063] S33) Configure the linkage module to save inactive data to nand flash;

[0064] S34) Complete other processes for powering off the SSD.

[0065] This embodiment is applicable to the PMR function design of NVMe SSD. The PMR function is an optional function item of the NVMe protocol. This method does not limit the size of the designed PMR area.

[0066] This embodiment implements power-on data recovery and power-off data preservation through the linkage module, thereby accelerating the speed of data recovery and preservation.

[0067] In order to address possible data preservation issues during abnormal power outages, especially to support large-capacity PMR area designs, this patent proposes a data classification-based self-optimization algorithm to store frequently accessed address unit data directly in the non-volatile medium MRAM, and move less frequently accessed address unit data to Nand Flash through a linkage hardware module.

[0068] This embodiment uses two address mapping tables to effectively maintain PMR data. Table A records the address relationship between PMR addresses and granularity units, i.e., the address mapping table between PMR addresses and granularity units. Table B records the address mapping relationship between PMR granularity units and Nand Flash physical units, i.e., the address mapping table between PMR granularity units and Nand Flash physical units.

[0069] The above description is only the basic principles and preferred embodiments of the present invention. Modifications and replacements made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A method for optimizing the PMR function of an SSD, characterized by: This method designs a linkage module. After power-on initialization and startup, the linkage module automatically restores the data saved in the nand flash to the DDR corresponding to the PMR function. When power is turned off, the linkage module saves the data from the DDR to the pre-erased nand flash. This method stores data in the PMR area in a classified manner, synchronously updates the frequently accessed data in the PMR to the MRAM for permanent storage, saves the infrequently accessed data in the DDR, and stores the infrequently accessed data in the NAND flash when power is off.

2. The method for optimizing the PMR function of an SSD according to claim 1, wherein: Data classification and storage in the PMR region is accomplished through a self-optimizing algorithm, which includes a PMR active data index, adaptive granularity, and data queues. The PMR active data index establishes a relationship between the data's offset address, access count, and time within the PMR. This relationship reflects the activity level of the data within the PMR, identifying the offset address with the highest number of accesses per unit time as active data. Adaptive granularity uses an adaptive algorithm to count the read and write volume of PMR data sent by the host and predict the most appropriate granularity; The data queue is used to store received and to-be-sent data packets. The data queue in the receiving direction is divided into active queue and inactive queue according to the data activity. After the data classification module classifies the data according to the activity index, the address translation module converts the address and puts the corresponding data into the active queue and inactive queue respectively. The data in the active queue is moved to MRAM, and the data in the inactive queue is moved to DDR.

3. The method for optimizing the PMR function of an SSD according to claim 2, wherein: The address translation module is used to convert the data sent by the host into the bus address inside the SSD for data routing. The address translation module integrates address routing rules. The address routing rules are based on the activity of PMR data. The data address range with high activity is translated into the address space where the MRAM is located. The data address range with low activity is translated into the address space where the DDR is located. At the same time, a table of address mapping relationships between PMR addresses and granularity units is established.

4. The method for optimizing the PMR function of an SSD according to claim 2, wherein: The PMR area is divided into N segments, the initial granularity of the PMR area is set to N, the initial access count is 0, and the adaptive granularity uses an adaptive algorithm to count the read and write volume of the PMR data sent by the host, and optimize learning based on the size of frequently accessed units, adaptively adjust the size of the granularity unit, and dynamically adjust the size of N.

5. The method for optimizing the PMR function of an SSD according to claim 1, wherein: When powered on, the linkage module automatically reads the PMR data from the NAND flash to the DDR according to the address mapping table between the PMR granularity unit and the Nand Flash physical unit. When powered off, the linkage module saves the data from the DDR to the pre-erased NAND flash and updates the address mapping table between the PMR granularity unit and the Nand Flash physical unit.

6. The method for optimizing the PMR function of an SSD according to claim 1, wherein: MRAM and DDR use DMA modules as data movement engines.

7. The method for optimizing the PMR function of an SSD according to claim 1, wherein: The specific process of power-on data recovery is as follows: S11), power on, initialize the linkage module to dual base address mode; S12), restore initialization information from nand flash, the initialization information includes PMR data distribution variables; S13) Configure the linkage module, which automatically reads the data stored in the nand flash; S14) Restore the inactive PMR data of the linkage module to the DDR automatically; S15), configure the bus address translation unit of the PCIe module to map the PMR address domain to the MRAM and DDR respectively; S16) Enable the NVMe PMR function and wait for host access.

8. The method for optimizing the PMR function of an SSD according to claim 1, wherein: The specific process of PMR regional data classification storage is as follows: S21), the host accesses the PMR, and the data classification module counts the access to the PMR data and calculates the PMR active data indicators; S22) Determine whether it is the first access. If yes, translate to the active data queue by default. If not, distinguish the active data according to the active data index and execute step S23); S23), determine whether it is active data, if yes, translate the data into MRAM address, if not, translate the data into DDR address; S24), update granularity to a chart; S25), adaptive algorithm update granularity; S25), update the active data index and return to step S23).

9. The method for optimizing the PMR function of an SSD according to claim 1, wherein: The specific process of data power-off preservation is as follows: S31) Turn off the power and disable the PMR function; S32) Save PMR data granularity and data distribution variables to nand flash; S33) Configure the linkage module to save inactive data to nand flash; S34) Complete other processes for powering off the SSD.

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