A parallel computing method and device for an unstructured triangular sparse linear equation system

Abstract

The present invention provides a parallel computing method and device for unstructured triangular sparse linear equations, relating to the field of high-performance numerical computing. The method includes: receiving a solution matrix and a right-hand vector, storing the non-zero elements of the solution matrix column by column; preprocessing the solution matrix, adaptively selecting a solution algorithm according to the analysis result, and starting multi-core parallel processing; allocating space in the local storage space of the core to store the non-zero element information, dependency relationships, and right-hand vector required for the solution, so as to achieve coarse-grained memory access; multiplying the obtained result by the non-zero elements of the matrix based on the solution result of the x vector, and updating the corresponding right-hand vector by using the obtained result to solve the data dependency problem, designing a reasonable communication scheme to achieve correct coarse-grained data transmission; based on the calculation process and communication scheme, solving the matrix blocks in sequence according to the horizontal level until the unstructured linear equation problem is completely and correctly solved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-performance numerical computing, and particularly to a parallel computing method and device for unstructured triangular sparse linear equations. Background Art

[0002] In recent years, numerical simulation and artificial intelligence have been widely applied in fields such as daily life, scientific development, and industrial manufacturing. While greatly promoting the development of human society, they also face challenges in computing performance. Among them, the solution of unstructured sparse linear equations plays an important role in both numerical simulation and artificial intelligence. Whether using direct methods or iterative methods for solution, the solution of unstructured triangular sparse linear equations is an important part. Therefore, optimizing its solution is very important for improving the overall performance.

[0003] At the same time, heterogeneous multi-core systems have gradually become the mainstream framework for computer development. The increase in the number of computing cores has led to a need for more performance optimization research at the thread level and instruction level. Using multi-cores for collaborative computing and maximizing the use of the communication mechanism and memory access mechanism between computing cores for optimized computing has become a research hotspot. Therefore, designing programs according to the communication and memory access characteristics of multi-core heterogeneous platforms is the key to improving program computing performance.

[0004] During the transient stability simulation of large-scale power systems, there are real-time and super-real-time simulation problems, and spatial algorithms need to be used to parallelize them. The spatial parallel algorithm transforms the algorithm design goal into the parallel solution of large-scale sparse linear equations in transient stability problems, that is, parallelly solving the network voltage based on the known injected current of dynamic components. This process can be described as AU = I. The solution process involves the calculation of high-dimensional sparse complex linear equations and requires a large number of forward and backward substitution operations of network equations, which is the most time-consuming part in transient calculations.

[0005] For the above problems, it is currently difficult to find a method with good performance for solving unstructured triangular sparse matrix linear equations. Existing high-performance sparse solution schemes also cannot show good performance in dealing with problems such as data dependence and discrete memory access. Therefore, there is an urgent need for a parallel computing method that relies on multi-core heterogeneous platforms to directly solve unstructured triangular sparse linear equations. Summary of the Invention

[0006] Aiming at the problem in the prior art that during the transient stability simulation of large-scale power systems, there are real-time and super-real-time simulation problems, and there is a lack of a parallel computing method that relies on multi-core heterogeneous platforms to directly solve unstructured triangular sparse linear equations, the present invention proposes a parallel computing method and device for unstructured triangular sparse linear equations.

[0007] To solve the above technical problems, the present invention provides the following technical solutions:

[0008] On the one hand, a parallel computing method for unstructured triangular sparse linear equations is provided. This method is applied to an electronic device and includes the following steps:

[0009] S1: Receive the solution matrix and the right-hand vector, store the non-zero elements of the solution matrix column by column; preprocess the solution matrix, adaptively select a solution algorithm according to the analysis result, and perform multi-core parallel processing;

[0010] S2: Based on the selected solution algorithm, allocate a separate space in the local storage space of the computing core to store the non-zero element information, dependency relationships, and right-hand vector required for the solution. Transfer the data from the main core to the computing core in multiple times in the form of coarse-grained data transfer. After solving for the x vector, write it back to the main core in multiple times through the coarse-grained data transfer form for coarse-grained memory access;

[0011] S3: Multiply the obtained solution result of the x vector with the non-zero elements of the matrix, update the corresponding right-hand vector using the obtained multiplication result, design a reasonable communication scheme, and perform coarse-grained data transfer;

[0012] S4: Based on the computing process and the communication scheme, solve the matrix blocks in sequence according to the horizontal level order to complete the solution of the unstructured linear equation problem.

[0013] Optionally, in step S1, preprocessing the solution matrix includes:

[0014] S11: Determine the matrix size and the number of non-zero elements, perform a horizontal level analysis on the matrix to obtain horizontal level information;

[0015] S12: Reorder the matrix according to the horizontal level information, calculate the average number of non-zero elements in each horizontal level, and determine the number of computing cores to be used and the solution algorithm;

[0016] S13: Divide the matrix according to the size of the matrix block and the preset number of computing cores to be used, determine the position information of the vector x calculated by each computing core and the position information of the non-zero elements it depends on, and store the obtained information continuously.

[0017] Optionally, after performing multi-core parallel processing in step S1, it further includes:

[0018] Start all the computing cores within the core group. Each computing core has independent computing core resources. Start calculating and sending data from the first computing core at the first horizontal level to a certain computing core at the last horizontal level to receive data.

[0019] Optionally, in step S1, adaptively select a solution algorithm, including:

[0020] Select a solution algorithm according to the matrix scale, the number of non-zero elements, and the number of levels of the sparse matrix;

[0021] Among them, select the number of computing cores used according to the matrix scale and the number of non-zero elements, including: M×N computing cores;

[0022] When selecting the producer-consumer pairing algorithm, divide the M×N computing cores into M×N / 2 producers and M×N / 2 consumers. The producers and consumers correspond one by one, and all computing core resources have communication and computing requirements;

[0023] When selecting the producer-consumer fusion algorithm, each computing core is both a producer and a consumer. After each computing core completes the calculation of vector x, it performs intermediate result calculation and sends it to the corresponding computing core. At the same time, it also needs to receive the intermediate results sent by other computing cores to update its own right-hand vector, and all computing core resources have communication and computing requirements.

[0024] Optionally, in step S2, coarse-grained memory access, including:

[0025] In the preprocessing stage, continuously store the non-zero element coordinate information, dependency relationship, and right-hand vector required for each computing core to calculate vector x in the order of levels; when each computing core calculates in the order of levels, when calculating each matrix block, transfer the required non-zero element coordinate information, dependency relationship, and right-hand vector to the computing core from the main core in the form of coarse-grained data transfer multiple times. After solving for vector x, write vector x back to the main memory again through the form of coarse-grained data transfer to achieve coarse-grained data transfer.

[0026] Optionally, in step S3, design a reasonable communication scheme for coarse-grained data transfer, including:

[0027] When selecting the producer-consumer pairing algorithm: The producers and consumers correspond one by one. The producer obtains the updated right-hand vector b transmitted by the consumer, calculates vector x, and writes vector x back to the main memory; calculates the product with the non-zero elements and sends the intermediate result to the target computing core number;

[0028] The consumer coarsely obtains from the main memory the elements of the right-hand vector b corresponding to the producer for updating vector x. According to the number of elements of the right-hand vector b that need to receive from other computing cores for updating its own right-hand vector b provided by the preprocessing, loop to check whether each buffer has received a message and update the elements of the right-hand vector b until all updates are completed, and then send the updated right-hand vector b to the corresponding producer;

[0029] When the producer-consumer fusion algorithm is selected: The role of each computing core is both a producer and a consumer. Each computing core needs to transfer the elements of the right-hand vector b and the corresponding dependencies from the main core, calculate the vector x, and write the vector x back to the main memory; calculate the product with non-zero elements, send the intermediate result to the target computing core number. At the same time, this computing core will also receive the messages used to update the right-hand vector b sent by other computing cores. After the update is completed, it will enter the next level of calculation.

[0030] Optionally, step S3 further includes:

[0031] When the distribution of non-zero elements of the matrix is very uneven, a column of the matrix will not be assigned to only one computing core for calculation, but will be assigned to 2 computing cores or 4 slave computing cores for calculation, that is, the entire computing core is divided into two communication areas or four communication areas; after each computing core calculates the corresponding vector x, except for the first communication area, each communication area will be transmitted to the computing cores in the same group through the RMA method for sharing the vector x among the computing cores in the same group. Before performing the data transmission operation, it is necessary to synchronize the calculation progress of the computing cores in the same group to calculate the correct intermediate results.

[0032] Optionally, step S3 further includes:

[0033] It will enter the next block only after receiving all the messages of all target computing core numbers. At the same time, it will also detect whether each computing core has sent all the messages to be sent. By designing flag bits to judge whether the sending and receiving message operations are completed, it avoids the deadlock of mutual waiting between computing cores.

[0034] Optionally, in step S4, the solution of the unstructured linear equation set problem includes:

[0035] Assume to solve the solution of a sparse linear equation set Lx = b,

[0036] where L is a sparse lower triangular matrix, b is the right-hand vector, and x is the solution vector (unknown);

[0037] where the calculation process includes a total of two calculation formulas. i represents the abscissa and j represents the ordinate: x j = b j / l jj and b i = b i - l ij x i .

[0038] On the one hand, a parallel computing device for an unstructured triangular sparse linear equation set is provided. The device is applied to an electronic device. The device includes:

[0039] A preprocessing module, configured to receive a solution matrix and a right-hand vector, store the non-zero elements of the solution matrix column by column; preprocess the solution matrix, adaptively select a solution algorithm according to the analysis result, and perform multi-core parallel processing;

[0040] A coarse-grained transfer memory access module, configured to, based on the selected solution algorithm, allocate a separate space in the local storage space of the computing core to store the non-zero element information, dependency relationships, and right-hand vector required for the solution, transfer them from the main core to the computing core in the form of coarse-grained data transfer in multiple times, and after solving for the x vector, write them back to the main core in the form of coarse-grained data transfer in multiple times to perform coarse-grained memory access;

[0041] An update module, configured to multiply with the non-zero elements of the matrix based on the solution result of the x vector, update the corresponding right-hand vector using the obtained multiplication result, design a reasonable communication scheme, and perform coarse-grained data transfer;

[0042] A solution module, configured to solve the matrix blocks in sequence according to the horizontal level based on the calculation process and the communication scheme, and complete the solution of the unstructured linear equation system problem.

[0043] On the one hand, an electronic device is provided, where the electronic device includes a processor and a memory, and at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processor to implement the above-mentioned parallel calculation method for an unstructured triangular sparse linear equation system.

[0044] On the one hand, a computer-readable storage medium is provided, where at least one instruction is stored in the storage medium, and the at least one instruction is loaded and executed by a processor to implement the above-mentioned parallel calculation method for an unstructured triangular sparse linear equation system.

[0045] The above technical solutions of the embodiments of the present invention have at least the following beneficial effects:

[0046] In the above solution, 1) The solution algorithm is adaptively selected according to the characteristics of the matrix itself, which is applicable to matrices of various different scales and different parallel degrees.

[0047] 2) By coarse-grained memory access, the memory access bandwidth is fully utilized;

[0048] 3) By maximizing the use of coarse-grained communication (including: designing buffers, producer-consumer pairing algorithms, producer-consumer fusion algorithms), the latency problem of coarse-grained communication is reduced as much as possible, the communication overhead is reduced, and the waste of resources of the computing core is avoided as much as possible, so as to achieve high-efficiency solution of unstructured linear equation systems. Description of the Drawings

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0050] Figure 1 is a flowchart of a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0051] Figure 2 is a flowchart of a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0052] Figure 3 is a schematic diagram of a producer-consumer pairing algorithm using 4×8 computing cores for a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0053] Figure 4 is a schematic diagram of a producer-consumer pairing algorithm using 8×8 computing cores for a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0054] Figure 5 is a schematic diagram of a producer-consumer fusion algorithm using 8×8 computing cores for a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0055] Figure 6 is a schematic diagram of a one-to-one communication process of a producer-consumer pairing algorithm for a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0056] Figure 7 is a schematic diagram of a many-to-many communication process of an 8×8 computing core producer-consumer pairing algorithm for a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0057] Figure 8 is a schematic diagram of a many-to-many communication process of an 8×8 computing core producer-consumer fusion algorithm for a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention;

[0058] Figure 9 is a schematic diagram of the comparison of the main core serial speedup ratio when running on a domestic Shenwei new generation E-class computer for a parallel computing method for an unstructured triangular sparse linear equation system provided by an embodiment of the present invention.

[0059] Figure 10Performance schematic diagram of a parallel computing method for unstructured triangular sparse linear equations provided by an embodiment of the present invention running on a domestic Shenwei new generation E-class computer.

[0060] Figure 11 It is a block diagram of a parallel computing device for unstructured triangular sparse linear equations provided by an embodiment of the present invention;

[0061] Figure 12 It is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0062] To make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments.

[0063] An embodiment of the present invention provides a parallel computing method for unstructured triangular sparse linear equations. This method can be implemented by an electronic device, and the electronic device can be a terminal or a server. As Figure 1 shown in the flowchart of the parallel computing method for unstructured triangular sparse linear equations, the processing flow of this method can include the following steps:

[0064] S101: Receive the solution matrix and the right-hand vector, store the non-zero elements of the solution matrix column by column; preprocess the solution matrix, adaptively select a solution algorithm according to the analysis result, and perform multi-core parallel processing;

[0065] S102: Based on the selected solution algorithm, allocate a separate space in the local storage space of the computing core to store the non-zero element information, dependency relationship and right-hand vector required for the solution. Transfer them from the main core to the computing core in multiple times in the form of coarse-grained data transfer. After solving for the x vector, write them back to the main core in multiple times through the coarse-grained data transfer form for coarse-grained memory access;

[0066] S103: Multiply the obtained solution result of the x vector with the non-zero elements of the matrix, update the corresponding right-hand vector using the obtained multiplication result, design a reasonable communication scheme, and perform coarse-grained data transfer;

[0067] S104: Based on the computing process and the communication scheme, solve the matrix blocks in sequence according to the horizontal level to complete the solution of the unstructured linear equation problem.

[0068] Optionally, in step S101, preprocessing the solution matrix includes:

[0069] S111: Determine the matrix size and the number of non-zero elements, perform a horizontal level analysis on the matrix, and obtain the horizontal level information;

[0070] S112: Reorder the matrix according to the level information, calculate the average number of non-zero elements in each level, and determine the number of computing cores to be used and the solution algorithm.

[0071] S113: Partition the matrix according to the size of the matrix block and the preset number of computing cores to be used, determine the position information of the vector x calculated by each computing core and the position information of the non-zero elements it depends on, and store the obtained information continuously.

[0072] Optionally, after multi-core parallel processing in step S101, it further includes:

[0073] Start all the computing cores within the core group. Each computing core has independent computing core resources. Start calculating and sending data from the first computing core at the first level to a certain computing core at the last level for receiving data.

[0074] Optionally, in step S101, adaptively select the solution algorithm, including:

[0075] Select the solution algorithm according to the matrix scale, the number of non-zero elements, and the number of levels of the sparse matrix;

[0076] Among them, selecting the number of computing cores according to the matrix scale and the number of non-zero elements includes: M×N computing cores;

[0077] When selecting the producer-consumer pairing algorithm, divide the M×N computing cores into M×N / 2 producers and M×N / 2 consumers. The producers and consumers correspond one by one, and all computing core resources have communication and computing requirements;

[0078] When selecting the producer-consumer fusion algorithm, each computing core is both a producer and a consumer. After each computing core finishes calculating the vector x, it calculates the intermediate result and sends it to the corresponding computing core. At the same time, it also needs to receive the intermediate results sent by other computing cores to update its own right-hand vector. All computing core resources have communication and computing requirements.

[0079] Optionally, in step S102, coarse-grained memory access includes:

[0080] In the preprocessing stage, continuously store the non-zero element coordinate information, dependency relationship, and right-hand vector required for each computing core to calculate the vector x in the order of levels; when each computing core calculates in the order of levels, when calculating each matrix block, transfer the required non-zero element coordinate information, dependency relationship, and right-hand vector to the computing core from the main core in multiple times in the form of coarse-grained data transmission. After solving for the x vector, write the vector x back to the main memory again in the form of coarse-grained data transmission to achieve coarse-grained data transmission.

[0081] Optionally, in step S103, a reasonable communication scheme is designed for coarse-grained data transmission, including:

[0082] When the producer-consumer pairing algorithm is selected: The producer and the consumer correspond one by one. The producer obtains the right-end vector b for which the consumer has completed the transmission and update, calculates the vector x, and writes the vector x back to the main memory; calculates the product with the non-zero elements and sends the intermediate result to the target computing core number.

[0083] The consumer coarsely obtains from the main memory the elements of the right-end vector b corresponding to the producer for updating the vector x. According to the number of elements of the right-end vector b that need to receive messages from other computing cores provided by the preprocessing, it circularly checks whether each buffer has received a message, updates the elements of the right-end vector b, and after all updates are completed, sends the updated right-end vector b to the corresponding producer.

[0084] When the producer-consumer fusion algorithm is selected: The role of each computing core is both a producer and a consumer. Each computing core needs to transfer the elements of the right-end vector b and the corresponding dependencies from the main core, calculate the vector x, and write the vector x back to the main memory; calculates the product with the non-zero elements and sends the intermediate result to the target computing core number. At the same time, this computing core will also receive the messages for updating the right-end vector b sent by other computing cores. After the update is completed, it enters the next level of calculation.

[0085] Optionally, step S103 further includes:

[0086] When the non-zero elements of the matrix are very unevenly distributed, a column of the matrix will not be assigned to only one computing core for calculation, but to 2 or 4 slave computing cores for calculation, that is, the entire computing core is divided into two or four communication areas; after each computing core calculates the corresponding vector x, except for the first communication area, each communication area will be transmitted to the computing cores in the same group through the RMA method for sharing the vector x among the computing cores in the same group. Before performing the data transmission operation, it is necessary to synchronize the calculation progress of the computing cores in the same group to calculate the correct intermediate results.

[0087] Optionally, step S103 further includes:

[0088] Only after receiving all the messages of all the target computing core numbers will it enter the next block. At the same time, it will also detect whether each computing core has sent all the messages to be sent. By designing a flag bit to judge whether the sending and receiving message operations are completed, it avoids the deadlock of mutual waiting between computing cores.

[0089] Optionally, in step S104, the solution of the unstructured linear equation system problem includes:

[0090] Assume to solve the solution of a sparse linear equation system \(Lx = b\),

[0091] where \(L\) is a sparse lower triangular matrix, \(b\) is the right - hand vector, and \(x\) is the solution vector (unknown);

[0092] where the calculation process altogether includes two calculation formulas. Let \(i\) represent the abscissa and \(j\) represent the ordinate: \(x\) j = \(b\) j / \(l\) jj and \(b\) i = \(b\) i - \(l\) ij \(x\) i .

[0093] The method provided in the embodiments of the present invention adaptively selects a solution algorithm according to the characteristics of the matrix itself, and is applicable to matrices of various different scales and different parallel degrees. Through coarse - grained memory access, the memory access bandwidth is fully utilized; by maximizing the use of coarse - grained communication (including: designing buffers, producer - consumer pairing algorithms, producer - consumer fusion algorithms), the latency problem of coarse - grained communication is reduced as much as possible, the communication overhead is reduced, and the waste of resources of computing cores is avoided as much as possible, so as to achieve high - efficiency solution of unstructured linear equation systems.

[0094] The embodiments of the present invention provide a parallel computing method for an unstructured triangular sparse linear equation system. This method can be implemented by an electronic device, and the electronic device can be a terminal or a server. As Figure 2 shown in the flowchart of the parallel computing method for an unstructured triangular sparse linear equation system, the processing flow of this method can include the following steps:

[0095] S201: Determine the matrix scale and the number of non - zero elements, perform a horizontal - level analysis on the matrix, and obtain horizontal - level information;

[0096] In the embodiments of the present invention, in this embodiment, receive the solution matrix \(L\) and the right - hand vector \(B\), store the non - zero elements of the solution matrix by column, pre - process the solution matrix, and adaptively select a solution algorithm according to the analysis result. Based on the selected solution algorithm, start multi - core parallel processing. All computing cores within the core group are started. Each computing core has its own computing core resources and does not interfere with each other. Start calculating and sending data from the first computing core of the first batch, and a certain computing core in the last batch receives the data and completes the calculation to achieve the solution of the entire structured linear equation system.

[0097] The relationship among the solution matrix \(L\), the solution vector \(X\), and the right - hand vector \(b\) is: \(L*X = b\).

[0098] In the embodiments of the present invention, during the transient stability simulation of a large-scale power system, there are real-time and super-real-time simulation problems, and it is necessary to parallelize them using a spatial algorithm. The spatial parallel algorithm transforms the algorithm design goal into the parallel solution of a large-scale sparse linear equation system in the transient stability problem, that is, to parallelly solve the network voltage based on the known injected current of dynamic components. This process can be described as AU = I. The solution process involves the calculation of a high-dimensional sparse complex linear equation system and requires a large number of forward and backward substitution operations of network equations, which is the most time-consuming part in transient calculations. In such a problem, parallelly solving triangular sparse linear equation systems can effectively improve the calculation of network equations and thus improve the overall simulation efficiency.

[0099] S202: Reorder the matrix according to the level information, calculate the average number of non-zero elements in each level, and determine the number of computing cores to be used and the solution algorithm;

[0100] S203: Partition the matrix according to the size of the matrix block and the preset number of computing cores to be used, determine the position information of the vector x calculated by each computing core and the position information of the non-zero elements it depends on, and continuously store the obtained information;

[0101] S204: Adaptively select the solution algorithm according to the analysis results and perform multi-core parallel processing.

[0102] In a feasible implementation manner, after performing multi-core parallel processing, it further includes:

[0103] Start all the computing cores in the core group. Each computing core has independent computing core resources. Start calculating and sending data from the first computing core of the first level to a certain computing core of the last level to receive the data.

[0104] In the embodiments of the present invention, each computing core has its own computing core resources and does not interfere with each other. Start calculating and sending data from the first computing core of the first level to a certain computing core of the last level to receive the data and complete the calculation to realize the solution of the entire unstructured linear equation system.

[0105] In a feasible implementation manner, adaptively selecting the solution algorithm includes:

[0106] Select the solution algorithm according to the matrix scale, the number of non-zero elements, and the number of levels of the sparse matrix;

[0107] Among them, selecting the number of computing cores according to the matrix scale and the number of non-zero elements includes: M×N computing cores;

[0108] Such as Figure 3 、 Figure 4, when the producer - consumer pairing algorithm is selected, the M×N computing cores are divided into M×N / 2 producers and M×N / 2 consumers. The producers and consumers correspond one by one, and all computing core resources have communication and computing requirements;

[0109] When the producer - consumer fusion algorithm is selected, each computing core is both a producer and a consumer. After each computing core finishes calculating the vector x, it calculates the intermediate result and sends it to the corresponding computing core. At the same time, it also needs to receive the intermediate results sent by other computing cores to update its own right - hand vector. All computing core resources have communication and computing requirements.

[0110] S205: Based on the selected solution algorithm, a separate space is allocated in the local storage space of the computing core to store the non - zero element information, dependency relationships, and right - hand vectors required for the solution. These are transferred from the main core to the computing core in multiple times in the form of coarse - grained data transfer. After solving for the x vector, it is written back to the main core in multiple times through the coarse - grained data transfer form for coarse - grained memory access;

[0111] In a feasible implementation, during the pre - processing stage, the non - zero element coordinate information, dependency relationships, and right - hand vectors required for each computing core to calculate the vector x are continuously stored in the order of horizontal levels; when each computing core calculates in the order of horizontal levels, when calculating each matrix block, the non - zero element coordinate information, dependency relationships, and right - hand vectors are transferred from the main core to the computing core in multiple times in the form of coarse - grained data transfer. After solving for the x vector, the vector x is written back to the main memory again through the coarse - grained data transfer form to achieve coarse - grained data transfer.

[0112] In the embodiments of the present invention, the implementation process of coarse - grained writing back of the calculated result after solution is as follows:

[0113] a. Affected by the local space size of the computing core, the size of the matrix data, dependency relationships, and right - hand vector data read in each time is fixed, and then they are read in batches;

[0114] b. Perform the calculation of the solution vector x. After the calculation is completed, write it back to the main memory in batches;

[0115] c. According to the newly solved vector x, calculate the intermediate result, and then send it to the target computing core number for updating the right - hand vector b (the producer - consumer pairing algorithm needs to transfer the vector b, and the producer - consumer fusion algorithm does not need to transfer the vector b and directly updates it within the computing core);

[0116] d. After obtaining the newly updated and completed vector b, return to b and continue the calculation of the vector x. If the relevant data is used up during the process, relevant data needs to be read in coarse - grained form from the main core in batches.

[0117] S206: Multiply the solution result of the x vector with the non-zero elements of the matrix, update the corresponding right-hand vector using the obtained multiplication result, design a communication scheme, and perform coarse-grained data transmission.

[0118] In a feasible implementation, based on the solution result of the x vector, multiply it with the non-zero elements of the matrix (production process), and update the corresponding right-hand vector using the obtained result (consumption process) to solve the data dependency problem.

[0119] In a feasible implementation, when starting the calculation at the first level, this block does not depend on other blocks and can be directly calculated without obtaining the intermediate result information for updating the right-hand vector b through communication.

[0120] Calculate the intermediate result (production process) of the computing core within this block and send it to the target computing core.

[0121] Meanwhile, this computing core will also receive the intermediate result (consumption process) of the right-hand vector b sent by other computing cores for updating the vector x required by this computing core in the next level of calculation.

[0122] After judging the dependency relationship and confirming that the right-hand vector b required by this computing core in the next level has been fully updated, enter the calculation of the next level to achieve the necessary data transmission due to data dependency.

[0123] Each subsequent level of calculation is based on the completion of updating the vector b in the previous level. When solving the vector x, the computing cores are independent of each other and there is no dependency relationship, so they can be solved in parallel to improve the calculation efficiency.

[0124] S207: Based on the calculation process and communication scheme, solve the matrix blocks in sequence according to the order of levels to complete the solution of the unstructured linear equation system problem.

[0125] In a feasible implementation, when choosing the producer-consumer pairing algorithm: the producer and consumer correspond one by one. The producer obtains the right-hand vector b whose update has been transmitted by the consumer. Among them, in the first level, it can directly read in batches from the main memory, calculate the vector x, and write the vector x back to the main memory; calculate the product with the non-zero elements and send the intermediate result to the target computing core number (many-to-many communication).

[0126] Consumers obtain the elements of the right-hand vector b corresponding to the producer for updating the vector x from the main memory in a coarse-grained manner (the first level can directly read in batches from the main memory). According to the number of elements of the right-hand vector b that need to receive messages from other computing cores for updating itself provided by the preprocessing, it cyclically checks whether each buffer has received a message and updates the elements of the right-hand vector b until all updates are completed. Then, the updated right-hand vector b is sent to the corresponding producer (one-to-one communication).

[0127] As Figure 5 shown, when the producer-consumer fusion algorithm is selected: the role of each computing core is both a producer and a consumer. Each computing core needs to transfer the elements of the right-hand vector b and the corresponding dependencies from the main core, calculate the vector x, and write the vector x back to the main memory; calculate the product with the non-zero elements and send the intermediate result to the target computing core number (many-to-many communication). At the same time, this computing core will also receive the messages for updating the right-hand vector b sent by other computing cores. After the update is completed, it enters the calculation of the next level.

[0128] In a feasible implementation, when the distribution of non-zero elements of the matrix is very uneven, a column of the matrix will not be assigned to only one computing core for calculation, but to 2 computing cores or 4 slave computing cores for calculation, that is, the entire computing core is divided into two communication regions or four communication regions; after each computing core calculates the corresponding vector x, except for the first communication region, each communication region will be transmitted to the computing cores in the same group through the RMA method for sharing the vector x among the computing cores in the same group. Before performing the data transmission operation, it is necessary to synchronize the calculation progress of the computing cores in the same group to calculate the correct intermediate results.

[0129] In the embodiments of the present invention, in the coarse-grained communication process, it is necessary to reasonably plan when the computing core produces and when it consumes, that is, to reasonably plan the timing of communication between computing cores, avoid load imbalance, deadlocks where computing cores wait for each other, and reduce the waste of computing core resources.

[0130] In a feasible implementation, it will enter the next block only after receiving all the messages of all target computing core numbers, and at the same time, it will also detect whether each computing core has sent all the messages to be sent. The design of flag bits is used to judge whether the sending and receiving message operations are completed, avoiding deadlocks where computing cores wait for each other.

[0131] Avoiding deadlocks where computing cores wait for each other includes:

[0132] Design for the many-to-many communication between computing cores when updating the right-hand vector b.

[0133] Step 1. In the preprocessing stage, the number of updates to the corresponding vector b for each computing core is counted. Therefore, the computing core determines whether the elements of vector b have been updated based on the value of this cnt.

[0134] Step 2. Each computing core has a mask. After entering a new level, a corresponding data mask is designed according to whether there is data to be updated in the current block for the corresponding other computing cores.

[0135] Step 3. If there is a corresponding message, set the mask bit corresponding to the computing core number of the other computing core to 1, otherwise set it to 0.

[0136] Step 4. Continuously update the value of this cnt array during the consumption process.

[0137] Step 5. After the data to be updated by the corresponding computing core is reduced to 0, the corresponding bit of the mask can be set to 0.

[0138] Step 6. Until the entire mask becomes zero, it is proved that the right-end vector b of this computing core in this matrix block has been updated, and the next block calculation can be entered to prevent infinite communication consumption.

[0139] Since the computing progress of different computing cores may be different, if the production and consumption timing is not well controlled, the following situation is very likely to occur:

[0140] Step 1. In the first communication area, computing core 0 and computing core 1, computing core 2 and computing core 3 are in the same group respectively, calculating a column of elements simultaneously, and need to perform a synchronization operation to share the calculated vector x.

[0141] Step 2. There is communication transmission for updating the right-end vector b between computing core 0 and computing core 2, and between computing core 1 and computing core 3.

[0142] Step 3. After computing core 1 sends a message to computing core 3, computing core 3 has not been updated in a timely manner, resulting in computing core 1 being unable to send the messages within this level for a long time.

[0143] Step 4. At the same time, after computing core 2 sends a message to computing core 0, computing core 0 has not been updated in a timely manner, resulting in computing core 2 being unable to send the messages within this level for a long time.

[0144] Step 5: At this time, Core 0 and Core 3 can smoothly proceed to the next communication area. However, Core 1 and Core 2 cannot enter the calculation of the next communication area due to transmission blocking, resulting in Core 0 being unable to synchronize with Core 1 and Core 2 being unable to synchronize with Core 3;

[0145] Step 6: The inability to synchronize means that Core 0 and Core 3 are in a waiting state all the time and do not perform the consumption operation that should quickly solve the problem of blocking Core 1 and Core 2, resulting in a process of mutual waiting between the two sides and causing deadlock.

[0146] Therefore, it is necessary to count the received target core numbers in each communication area of each core.

[0147] Step 1: After receiving all the messages of all the target core numbers, it will enter the next block. At the same time, it will also detect whether each core has sent all the messages to be sent;

[0148] Step 2: By designing a flag bit to judge whether the message operations of sending and receiving are completed, so as to solve the deadlock problem in the communication process.

[0149] In the embodiment of the present invention, for the many-to-many communication between cores, it is designed when updating the right-end vector b. Because in the preprocessing stage, the number of updates of the corresponding vector b for each core is counted, so the core judges whether the elements of the vector b have been updated according to the size of this cnt value.

[0150] Since the calculation progress of different cores may be different, resulting in a process of mutual waiting between the two sides and causing deadlock. Therefore, it is necessary to count the received target core numbers in each communication area of each core. After receiving all the messages of all the target core numbers, it will enter the next block. At the same time, it will also detect whether each core has sent all the messages to be sent. By designing a flag bit to judge whether the message operations of sending and receiving are completed, so as to solve the deadlock problem in the communication process.

[0151] In a feasible implementation, to solve the data dependence problem, when starting the calculation at the first level, this block does not depend on other blocks and can directly perform the calculation without obtaining the intermediate result information of updating the right-hand side vector b through communication. Then, calculate the intermediate result (production process) within this block of the computing core and send it to the target computing core. At the same time, this computing core will also receive the intermediate result (consumption process) of the right-hand side vector b used to update the computing vector x of this computing core at the next level sent by other computing cores. After judging the dependence relationship and confirming that all the right-hand side vectors b required by this computing core at the next level have been updated, enter the calculation of the next level to achieve the necessary data transmission due to data dependence.

[0152] In a feasible implementation, the correct coarse-grained data transmission includes:

[0153] When selecting the producer-consumer pairing algorithm, the producer needs to design a send buffer for each consumer. When the send buffer is full, send out all the messages in the buffer. The consumer also needs to set up a receive buffer for all producers and loop to check whether each buffer has received a message. All producers will send a verification message indicating the end of communication to all consumers to end the entire communication process. Since this process is relatively complex, a communication sub-module is also designed to ensure correct coarse-grained communication.

[0154] When selecting the producer-consumer fusion algorithm, the role of each computing core is both a producer and a consumer. Therefore, each computing core needs to design a send buffer for other computing cores and send out all the messages in the buffer when the send buffer is full. It also needs to design a receive buffer and loop to check whether each buffer has received a message. All computing cores will send a verification message indicating the end of communication to other computing cores to end the entire communication process. Similarly, a communication sub-module is also designed to ensure correct coarse-grained communication.

[0155] In a feasible implementation, to avoid load imbalance, when the distribution of non-zero elements in the matrix is very uneven, a column of the matrix will not be assigned to only one computing core for calculation, but to 2 computing cores or 4 slave computing cores for calculation, that is, the entire computing core is divided into two communication areas or four communication areas. After each computing core calculates the corresponding vector x, except for the first communication area, each communication area will be transmitted to the computing core in the same group through the RMA method to share the vector x among the computing cores in the same group. Before performing the data transmission operation, it is necessary to synchronize the calculation progress of the computing cores in the same group to calculate the correct intermediate result. In this way, the operation of assigning a column to 2 computing cores or 4 computing cores for simultaneous calculation can be realized to achieve load balance.

[0156] In a feasible implementation, to reduce the waste of computing core resources, when the computing core updates the right-hand vector b, it cyclically checks whether each buffer has received a message. However, in many cases, it is often only because a small number of computing cores have not been consumed completely. At this time, it only needs to cyclically judge the computing core numbers that have not been consumed completely. Therefore, in the preprocessing stage, the computing core numbers to be consumed by each computing core at each level and the number of computing core numbers to be consumed are counted, and each time only the computing core numbers and the corresponding number of computing core numbers in the corresponding set need to be cyclically judged, so as to improve and reduce the waste of computing core resources.

[0157] In this embodiment, to reduce the waste of computing core resources, when the computing core updates the right-hand vector b, it cyclically checks whether each buffer has received a message. However, in many cases, it is often only because a small number of computing cores have not been consumed completely. At this time, it only needs to cyclically judge the computing core numbers that have not been consumed completely.

[0158] Step 1: In the preprocessing stage, the computing core numbers to be consumed by each computing core at each level and the number of computing core numbers to be consumed are counted and stored in a set and an array respectively;

[0159] Step 2: After each consumption, if it has been judged that the consumption is complete, the corresponding computing core number is removed from the set and the corresponding consumption number is subtracted;

[0160] Step 3: Each time only the computing core numbers and the corresponding number of computing core numbers in the corresponding set need to be cyclically judged, so as to improve and reduce the waste of computing core resources.

[0161] In this embodiment, implementing coarse-grained communication includes:

[0162] When the producer-consumer pairing algorithm is selected:

[0163] Step 1: The producer needs to design a sending buffer for each consumer, and when the sending buffer is full, the messages in the entire buffer are sent out;

[0164] Step 2: The consumer also needs to set up a receiving buffer for all producers and cyclically check whether each buffer has received a message;

[0165] Step 3: All producers will send a verification message indicating the end of communication to all consumers to end the entire communication process;

[0166] Step 4: Since this process is relatively complex, a communication sub-module is also designed to ensure the correct coarse-grained communication.

[0167] When the producer-consumer fusion algorithm is selected:

[0168] Step 1: The role of each computing core is both a producer and a consumer. Therefore, each computing core needs to design a sending buffer for other computing cores and send out all the messages in the buffer when the sending buffer is full.

[0169] Step 2: Each computing core also needs to design a receiving buffer and loop to check whether each buffer has received a message.

[0170] Step 3: All computing cores will send a verification message indicating the end of communication to other computing cores to end the entire communication process.

[0171] Step 4: Similarly, a communication sub is also designed to ensure correct coarse-grained communication.

[0172] In this embodiment, the reasonable communication scheme design includes:

[0173] When the producer-consumer pairing algorithm is selected:

[0174] Step 1: Producers and consumers are in one-to-one correspondence. First, the producer needs to obtain the right-end vector b (the first level can be directly read in batches from the main memory) after the consumer's transmission and update is completed.

[0175] Step 2: Calculate the vector x and write the vector x back to the main memory in a coarse-grained manner.

[0176] Step 3: Calculate the product with non-zero elements and send the intermediate result to the target computing core number (many-to-many communication).

[0177] Step 4: First, the consumer needs to obtain the elements of the right-end vector b corresponding to the producer for updating the vector x from the main memory in a coarse-grained manner.

[0178] Step 5: Then, according to the number of elements of the right-end vector b that need to receive updates from other computing cores provided by the preprocessing, loop to check whether each buffer has received a message and update the elements of the right-end vector b.

[0179] Step 6: After all updates are completed, send the updated right-end vector b to the corresponding producer (one-to-one communication).

[0180] In this embodiment, when this type of algorithm is selected, there are mainly two types of communication: 1. The consumer sends the right-end vector to the paired producer; 2. The producer sends the result of calculating Δ ij =l ij x j to the target consumer.

[0181] The first type of communication rule is relatively simple as Figure 6As shown: It belongs to "one-to-one communication" and involves the pairing of producers and consumers.

[0182] Step 1: "One-to-one communication" only requires point-to-point synchronization. The paired "producer-consumer" pairs do not interfere with each other, and RMA communication can be directly used.

[0183] Step 2: Data is transferred from the right-end vector b buffer of the consumer to the vector x buffer of the producer, and no additional communication buffer needs to be set up.

[0184] The second type of communication is more complex. Taking the pairing algorithm of 8×8 computing cores' producer-consumer as an example (as Figure 7 shown): The producer acts as the sender and performs one-to-many sending. The consumer acts as the receiver and needs to receive messages from multiple producers simultaneously, which belongs to "many-to-many communication".

[0185] Step 1: In this type of algorithm, once the producer obtains the vector b required to solve the vector x, it can start the calculation.

[0186] Step 2: Once the consumer obtains all the intermediate results for updating the right-end vector b, it can start data update. Therefore, in this type of algorithm, only the x can be solved and the right-end vector b can be updated in the horizontal order, and no additional processing is required for the production and consumption processes.

[0187] When the producer-consumer fusion algorithm is selected (as Figure 8 shown):

[0188] Step 1: The role of each computing core is both a producer and a consumer. First, each computing core needs to transfer the elements of the right-end vector b (the first horizontal level can directly read in batches from the main memory) and the corresponding dependencies from the main core.

[0189] Step 2: Calculate the vector x and write the vector x back to the main memory.

[0190] Step 3: Calculate the product with non-zero elements and send the intermediate results to the target computing core number (many-to-many communication). At the same time, this computing core will also receive the messages sent by other computing cores for updating the right-end vector b.

[0191] Step 4: After the update is completed, enter the calculation of the next horizontal level.

[0192] Step 5. At the same time, each computing core can only choose between the producer and consumer roles. If this computing core does not produce in time, other computing cores cannot update the right-end vector b in time. If this computing core does not consume in time, other computing cores will not send and receive new messages because the corresponding receiving buffer of this computing core is full. Therefore, it is necessary to measure the number of message transmissions according to the number of non-zero elements in the actual matrix, and then control whether the computing core should produce or consume. Therefore, the specific production and consumption timing scheme can be specifically described as follows:

[0193] Step 1. According to the number of non-zero elements in the matrix and the number of levels, determine the number of times the production process needs to intersperse the consumption process when the matrix is calculated by the computing core;

[0194] Step 2. When the non-zero elements in the matrix are relatively dense or the distribution of non-zero elements in the matrix is uneven, it is necessary to increase the number of times of interspersing consumption in production as much as possible;

[0195] Step 3. When the non-zero elements are relatively dense, it is more likely to occur the problem that the receiving buffer is blocked and cannot receive new messages. When the distribution of non-zero elements in the matrix is more uneven, it is more likely to slow down the calculation progress of the overall computing core due to the production and consumption of a certain computing core.

[0196] In this embodiment, the way to avoid load imbalance is that when the distribution of non-zero elements in the matrix is very uneven, a column of the matrix will not be assigned to only one computing core for calculation, but will be assigned to 2 or 4 computing cores for calculation, that is, the entire computing core is divided into two or four communication areas.

[0197] Step 1. After each computing core calculates the corresponding vector x, except for the first communication area, each communication area will be transmitted to the computing cores in the same group as it through the RMA method to share the vector x among the computing cores in the same group;

[0198] Step 2. Before performing the data transmission operation, it is necessary to synchronize the calculation progress of the computing cores in the same group to calculate the correct intermediate results. In this way, the operation of assigning a column to 2 or 4 computing cores for simultaneous calculation can be realized to achieve load balance.

[0199] In a feasible implementation manner, the solution of the unstructured linear equation set problem includes:

[0200] Assume to solve the solution of a sparse linear equation set Lx = b,

[0201] where L is a sparse lower triangular matrix, b is the right-end vector, and x is the solution vector;

[0202] Among them, the calculation process includes a total of two calculation formulas, where i represents the abscissa and j represents the ordinate: x j = b j / l jj and b i = b i - l ij x i .

[0203] To better understand the parallel computing method for directly solving unstructured triangular sparse linear equations provided by the embodiments of the present invention, and applying it to a new generation of Shenwei many-core computers, the calculation comparison of the main core speedup ratio and the performance test results of this method are respectively as Figure 9 、 Figure 10 shown.

[0204] Using the method of the present invention to solve an unstructured lower triangular linear equation system, 407 real square matrices in the SuiteSparse sparse matrix dataset are used as test cases. Calculating the floating-point operation performance according to the theory, where nnz represents the number of non-zero elements in the matrix, n represents the scale of the matrix, and time represents the running time:

[0205] F p = nnz * 2 - n / time

[0206] The set average value of the calculation performance is 0.53 Gflop / s. Compared with the serial algorithm that only uses the main core for calculation, the average speedup ratio is 7.6.

[0207] It can be seen that the parallel computing method for directly solving unstructured triangular sparse linear equations provided by this embodiment, by maximizing the use of the communication mechanism and memory access mechanism between multiple cores, realizes the adaptive selection of the solution algorithm according to the characteristics of the matrix itself, so as to efficiently solve the unstructured linear equation system.

[0208] The parallel computing method for directly solving unstructured triangular sparse linear equations provided by this embodiment adaptively selects the solution algorithm according to the characteristics of the matrix itself, and is applicable to matrices of various scales and different parallel degrees; through coarse-grained memory access, it makes full use of the memory access bandwidth; by maximizing the use of coarse-grained communication (including: designing buffers, producer-consumer pairing algorithms, producer-consumer fusion algorithms), it minimizes the latency problem of coarse-grained communication, reduces communication overhead, and avoids wasting the resources of computing cores as much as possible, realizing the efficient solution of unstructured linear equation systems.

[0209] Figure 11 is a block diagram of a parallel computing device for an unstructured triangular sparse linear equation system shown according to an exemplary embodiment. Referring to Figure 11 , this device 300 includes:

[0210] The preprocessing module 310 is configured to receive a solution matrix and a right-hand side vector, store the non-zero elements of the solution matrix column by column; preprocess the solution matrix, adaptively select a solution algorithm according to the analysis result, and perform multi-core parallel processing;

[0211] The coarse-grained transfer memory access module 320 is configured to, based on the selected solution algorithm, allocate a separate space in the local storage space of the computing core to store the non-zero element information, dependency relationships, and right-hand side vector required for the solution, transfer them from the main core to the computing core in the form of coarse-grained data transfer in multiple times, and after solving for the x vector, write them back to the main core in the form of coarse-grained data transfer in multiple times to perform coarse-grained memory access;

[0212] The update module 330 is configured to multiply the non-zero elements of the matrix based on the solution result of the x vector, update the corresponding right-hand side vector using the obtained multiplication result, design a reasonable communication scheme, and perform coarse-grained data transfer;

[0213] The solution module 340 is configured to solve the matrix blocks in sequence according to the horizontal level based on the computing process and the communication scheme, and complete the solution of the unstructured linear equation system problem.

[0214] Optionally, the preprocessing module 310 is configured to determine the matrix size, the number of non-zero elements, perform a horizontal level analysis on the matrix, and obtain horizontal level information;

[0215] Perform matrix reordering according to the horizontal level information, calculate the average number of non-zero elements in each horizontal level, determine the number of computing cores to be used and the solution algorithm;

[0216] Perform matrix partitioning according to the size of the matrix block and the preset number of computing cores to be used, determine the position information of the vector x calculated by each computing core and the position information of the non-zero elements it depends on, and store the obtained information continuously.

[0217] Optionally, the preprocessing module 310 is configured to start all the computing cores within the core group. Each computing core has independent computing core resources, starts computing and sending data from the first computing core at the first horizontal level, and receives data at a certain computing core at the last horizontal level.

[0218] Optionally, the preprocessing module 310 is configured to select a solution algorithm according to the matrix size, the number of non-zero elements, and the number of horizontal levels of the sparse matrix;

[0219] Among them, determining the number of computing cores to be used according to the matrix size and the number of non-zero elements includes: M×N computing cores;

[0220] When the producer-consumer pairing algorithm is selected, the M×N computing cores are divided into M×N / 2 producers and M×N / 2 consumers. The producers and consumers correspond one by one, and all computing core resources have communication and computing requirements.

[0221] When the producer-consumer fusion algorithm is selected, each computing core is both a producer and a consumer. After each computing core finishes calculating the vector x, it calculates the intermediate result and sends it to the corresponding computing core. At the same time, it also needs to receive the intermediate results sent by other computing cores to update its own right-hand vector. All computing core resources have communication and computing requirements.

[0222] Optionally, the coarse-grained transfer memory access module 320 is used to continuously store the non-zero element coordinate information, dependency relationship, and right-hand vector required by each computing core to calculate the vector x in the preprocessing stage in the horizontal order; when each computing core calculates in the horizontal order, when calculating each matrix block, the required non-zero element coordinate information, dependency relationship, and right-hand vector are transferred from the main core to the computing core in multiple coarse-grained data transfer forms. After solving for the x vector, the vector x is written back to the main memory again through the coarse-grained data transfer form to achieve coarse-grained data transfer.

[0223] Optionally, in step S3, a reasonable communication scheme is designed for coarse-grained data transfer, including:

[0224] When the producer-consumer pairing algorithm is selected: The producers and consumers correspond one by one. The producer obtains the updated right-hand vector b transmitted by the consumer, calculates the vector x, and writes the vector x back to the main memory; calculates the product with the non-zero element, and sends the intermediate result to the target computing core number.

[0225] The consumer coarsely obtains from the main memory the elements of the right-hand vector b corresponding to the producer for updating the vector x. According to the number of elements of the right-hand vector b that need to receive messages from other computing cores for updating itself provided by the preprocessing, it cyclically checks whether each buffer has received a message, and updates the elements of the right-hand vector b until all updates are completed, and then sends the updated right-hand vector b to the corresponding producer.

[0226] When the producer-consumer fusion algorithm is selected: The role of each computing core is both a producer and a consumer. Each computing core needs to transfer the elements of the right-hand vector b and the corresponding dependency relationship from the main core, calculate the vector x, and write the vector x back to the main memory; calculate the product with the non-zero element, and send the intermediate result to the target computing core number. At the same time, this computing core will also receive the messages sent by other computing cores for updating the right-hand vector b. After the update is completed, it enters the calculation of the next horizontal level.

[0227] Optionally, the update module 330 is used to allocate a column of the matrix to two or four slave computing cores for calculation instead of just one computing core for calculation when the distribution of non-zero elements of the matrix is very uneven, that is, the entire computing core is divided into two communication areas or four communication areas; after each computing core calculates the corresponding vector x, except for the first communication area, each communication area will be transmitted to the computing core in the same group through RMA to share the vector x between the computing cores in the same group. Before performing the data transmission operation, the calculation progress of the computing cores in the same group needs to be synchronized to calculate the correct intermediate results.

[0228] Optionally, the update module 330 is used to enter the next block only after receiving all messages from all target computing core numbers. It also detects whether each computing core has sent all messages to be sent. By designing a flag bit to determine whether the message sending and receiving operations are completed, deadlock caused by computing cores waiting for each other can be avoided.

[0229] Optionally, the solution module 340 is used to solve a sparse linear equation system Lx=b.

[0230] Where L is a sparse lower triangular matrix, b is the right-hand side vector, and x is the solution vector (unknown number).

[0231] The calculation process includes two calculation formulas, i represents the horizontal coordinate and j represents the vertical coordinate: x j =b j / l jj and b i =b i -l ij x i .

[0232] This embodiment provides a parallel computing method for directly solving unstructured triangular sparse linear equations on a heterogeneous multi-core platform. It adaptively selects a solution algorithm based on the characteristics of the matrix itself and is applicable to matrices of various sizes and degrees of parallelism. It fully utilizes memory access bandwidth through coarse-grained memory access. It minimizes the delay problem of coarse-grained communication and communication overhead by maximizing the use of coarse-grained communication (including: designing buffers, producer-consumer pairing algorithms, and producer-consumer fusion algorithms), avoids waste of computing core resources as much as possible, and achieves efficient solution of unstructured linear equations.

[0233] Figure 12FIG. 0 is a schematic structural diagram of an electronic device 400 provided by an embodiment of the present invention. The electronic device 400 may vary greatly due to different configurations or performances, and may include one or more central processing units (CPUs) 401 and one or more memories 402. Among them, at least one instruction is stored in the memory 402, and the at least one instruction is loaded and executed by the processor 401 to implement the steps of the parallel computing method for the unstructured triangular sparse linear equation set as follows:

[0234] S1: Receive a solution matrix and a right-hand vector, store the non-zero elements of the solution matrix column by column; preprocess the solution matrix, adaptively select a solution algorithm according to the analysis result, and perform multi-core parallel processing;

[0235] S2: Based on the selected solution algorithm, allocate a separate space in the local storage space of the computing core to store the non-zero element information, dependency relationship, and right-hand vector required for the solution. Transfer them from the main core to the computing core in multiple times in the form of coarse-grained data transmission. After solving for the x vector, write them back to the main core in multiple times through the coarse-grained data transmission form, and perform coarse-grained memory access;

[0236] S3: Multiply the obtained solution result of the x vector by the non-zero elements of the matrix, update the corresponding right-hand vector using the obtained multiplication result, design a communication scheme, and perform coarse-grained data transmission;

[0237] S4: Based on the above computing process and communication scheme, solve the matrix blocks in sequence according to the horizontal level order to complete the solution of the unstructured linear equation set problem.

[0238] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including instructions. The above instructions can be executed by a processor in a terminal to complete the parallel computing method for the unstructured triangular sparse linear equation set. For example, the computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0239] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or can be completed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a magnetic disk, or an optical disc, etc.

[0240] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A parallel computing method for an unstructured triangular sparse linear equation system, characterized in that It includes the following steps: S1: Receive the solution matrix and the right-hand vector, and store the non-zero elements of the solution matrix column by column; Preprocess the solution matrix, adaptively select a solution algorithm according to the analysis results, and perform multi-core parallel processing; In S1, adaptively selecting a solution algorithm includes: Selecting a solution algorithm according to the matrix size, the number of non-zero elements, and the number of levels of the sparse matrix; Among them, selecting the number of computing cores according to the matrix size and the number of non-zero elements includes: M×N computing cores; When selecting the producer-consumer pairing algorithm, divide the M×N computing cores into M×N / 2 producers and M×N / 2 consumers. The producers and consumers correspond one by one, and all computing core resources have communication and computing requirements; When selecting the producer-consumer fusion algorithm, each computing core is both a producer and a consumer. After the vector x is calculated by each computing core, intermediate results are calculated and sent to the corresponding computing core. At the same time, it also needs to receive the intermediate results sent by other computing cores to update the right-hand vector from itself. All computing core resources have communication and computing requirements; x is the unknown of the solution vector; S2: Based on the selected solution algorithm, allocate a separate space in the local storage space of the computing core to store the non-zero element information, dependency relationship, and right-hand vector required for solving In S2, coarse-grained memory access includes: During the preprocessing stage, continuously store the non-zero element coordinate information, dependency relationship, and right-hand vector required for each computing core to calculate the vector x in the order of levels; when each computing core calculates in the order of levels, when calculating each matrix block, transfer the required non-zero element coordinate information, dependency relationship, and right-hand vector to the computing core in the form of coarse-grained data transmission multiple times. After solving for the x vector, write the vector x back to the main memory in the form of coarse-grained data transmission again to achieve coarse-grained data transmission; The non-zero element information, dependency relationship, and right-hand vector required for solving are transferred from the main core to the computing core in the form of coarse-grained data transmission multiple times. After solving for the x vector, write it back to the main core in the form of coarse-grained data transmission multiple times for coarse-grained memory access; S3: Based on the solution result of the x vector, multiply it by the non-zero elements of the matrix, update the corresponding right-hand vector using the obtained multiplication result, design a communication scheme, and perform coarse-grained data transmission; S4: Based on the calculation process and communication scheme of S1-S3, solve each matrix block in the order of levels in turn to complete the solution of the unstructured linear equation system problem.

2. The method according to claim 1, wherein, In step S1, preprocessing the solution matrix includes: S11: Determine the matrix size and the number of non-zero elements, perform a level analysis on the matrix, and obtain level information; S12: Reorder the matrix according to the level information, calculate the average number of non-zero elements in each level, determine the number of computing cores to be used and the solution algorithm; S13: Divide the matrix according to the size of the matrix block and the preset number of computing cores to be used, determine the position information of the vector x calculated by each computing core and the position information of the non-zero elements it depends on, and continuously store the obtained information.

3. The method according to claim 1, characterized in that After the multi-core parallel processing in step S1, the following steps are further included: Start all computing cores within the core group. Each computing core has independent computing core resources. Start computing and sending data from the first computing core at the first level to a certain computing core at the last level to receive data.

4. The method according to claim 3, wherein In step S3, design a communication scheme for coarse-grained data transmission, including: When the producer-consumer pairing algorithm is selected: The producer and the consumer correspond one by one. The producer obtains the right-end vector b whose transmission and update by the consumer are completed, calculates the vector x, and writes the vector x back to the main memory; calculates the product with the non-zero elements and sends the intermediate result to the target computing core number. The consumer coarsely obtains from the main memory the elements of the right-end vector b corresponding to the producer for updating the vector x. According to the number of elements of the right-end vector b that other computing cores need to send for updating itself provided by the preprocessing, cyclically check whether each buffer has received a message, and update the elements of the right-end vector b until all updates are completed, and then send the updated right-end vector b to the corresponding producer. When the producer-consumer fusion algorithm is selected: The role of each computing core is both a producer and a consumer. Each computing core needs to transfer the elements of the right-end vector b and the corresponding dependencies from the main core, calculate the vector x, and write the vector x back to the main memory; calculate the product with the non-zero elements and send the intermediate result to the target computing core number. At the same time, this computing core will also receive the messages for updating the right-end vector b sent by other computing cores. After the update is completed, it will enter the calculation of the next level.

5. The method according to claim 3, characterized in that, Step S3 further includes: When the non-zero elements of the matrix are unevenly distributed, a column of the matrix will not be assigned to only one computing core for calculation, but will be assigned to 2 computing cores or 4 slave computing cores for calculation, that is, the entire computing core is divided into two communication areas or four communication areas; after each computing core calculates the corresponding vector x, except for the first communication area, each communication area will be transmitted to the computing cores in the same group through the RMA method to share the vector x among the computing cores in the same group. Before performing the data transmission operation, it is necessary to synchronize the calculation progress of the computing cores in the same group to calculate the correct intermediate results.

6. The method according to claim 1, wherein Step S3 further includes: Only after receiving all the messages of all target computing core numbers will it enter the next block. At the same time, it will also detect whether each computing core has sent all the messages to be sent. A flag bit is designed to judge whether the sending and receiving message operations are completed, so as to avoid deadlocks where computing cores wait for each other.

7. The method according to claim 6, wherein In step S4, the solution of the unstructured system of linear equations problem includes: Assume to solve the solution of a sparse system of linear equations Lx = b. Where L is a sparse lower triangular matrix and b is the right-end vector. Among them, the calculation process includes two calculation formulas in total. Let \(i\) represent the abscissa and \(j\) represent the ordinate: \(x\) j = b j / l jj And \(b\) i = b i - l ij x i .

8. A parallel computing device for an unstructured triangular sparse linear equation system, characterized in that, The device is applicable to the method described in any one of claims 1-7 above. The device includes: A preprocessing module, which is used to receive a solution matrix and a right-hand vector, store the non-zero elements of the solution matrix column by column; preprocess the solution matrix, adaptively select a solution algorithm according to the analysis results, and perform multi-core parallel processing; A coarse-grained transfer memory access module, which is used to, based on the selected solution algorithm, allocate a separate space in the local storage space of the computing core to store the non-zero element information, dependency relationships, and right-hand vector required for the solution, transfer them from the master core to the computing core in multiple times in the form of coarse-grained data transfer, and after solving for the x vector, write them back to the master core in multiple times through the form of coarse-grained data transfer for coarse-grained memory access; An update module, which is used to, based on the solution result of the x vector, multiply it with the non-zero elements of the matrix, use the obtained multiplication result to update the corresponding right-hand vector, design a communication scheme, and perform coarse-grained data transfer; A solution module, which is used to, based on the calculation process and the communication scheme, solve the matrix blocks in sequence according to the horizontal level order to complete the solution of the unstructured linear equation set problem.

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