A parsing layout method based on graph neural network

Abstract

The present invention discloses a parsing layout method based on a graph neural network. The method includes an encoder and a decoder. By applying a graph neural network, the original input feature data, namely the attributes of each module in the chip and the chip's netlist and other feature data, is encoded, greatly improving the expressiveness of the original features. The graph embedding representation obtained by the encoder is given as output to the decoder, and the half-circle length indicator is used as the output of the encoder to be predicted. By applying a neural network structure, the position coordinates (x, y) of each module to be solved are used as the weights of the neural network for training, thereby obtaining the final circuit layout result. Compared with traditional chip layout technology, this method has a stronger feature expression capability, allowing the model to have a faster convergence speed and better prediction results, realizing intelligent and efficient layout.

Description

Technical Field

[0001] The present invention relates to the field of chip layout technology, and more specifically, to an analytical layout method based on graph neural network. Background Art

[0002] Floorplanning is a critical step in integrated circuit design. With the exponential growth of integrated circuit scale, the need for intelligent floorplanning has become increasingly urgent and indispensable. This intelligent development will undoubtedly save significant manpower and time. The primary goal of IC layout is to determine the location of each macromodule while minimizing trace length and eliminating overlapping cells.

[0003] In existing methods, the process of solving the layout problem is mapped to the training process of a neural network: the circuit diagram is used as a network (net), which can also be a graph (graph). A feature vector and a label of size 0 (i.e., the ideal value of the half-circle line length) are generated for the graph through calculation. Then, this graph with the feature vector and label is fed into the neural network, and the position coordinates (x, y) of each module are used as the weight parameters of the neural network to be trained. The absolute value of the difference between the predicted line length of the circuit diagram after layout and the true value (i.e., the label value, size 0) is used as the loss function. However, this method only uses simple feature information such as the length and width of the module as input, and does not further explore the module's characteristics.

[0004] Prior art discloses a system and method for optimizing chip layout based on deep reinforcement learning. This method utilizes a data preprocessing module to read and parse .pl and .net files, converting the netlist information contained therein into the initial state of the agent and a reward function. The policy network module utilizes a convolutional neural network and a graph neural network to obtain coarse-grained global and node embedding features, respectively. The feature vectors obtained from the two networks are then fused to ultimately predict the current behavior, i.e., the probability distribution of possible component placements. This solution, based on reinforcement learning, suffers from the drawbacks of requiring large amounts of training data, numerous iterations, and long training times.

[0005] To this end, in combination with the above requirements and the shortcomings of the existing technology, this application proposes a parsing layout method based on graph neural network. Summary of the Invention

[0006] The present invention provides an analytical layout method based on graph neural networks, which has powerful feature expression capabilities, enabling the model to have faster convergence speed and better prediction results, and realizing intelligent and efficient layout.

[0007] The primary purpose of the present invention is to solve the above technical problems, and the technical solutions of the present invention are as follows:

[0008] A first aspect of the present invention provides a parsing layout method based on a graph neural network, comprising the following steps:

[0009] S1. Extracting netlist files and module attributes from circuit diagram data to construct a data set and dividing the data set into a training set and a validation set according to a preset ratio.

[0010] S2. Construct an encoder model, i.e., a GNN model, based on a graph neural network. The encoder is used to encode the netlist file and module attributes to obtain a graph embedding representation. Construct a decoder model, i.e., a neural network model, input the graph embedding representation into the decoder, and output the half-circle line length indicator to be predicted.

[0011] S3. Use the training set data to train the encoder and decoder, set the loss function of the entire network, input the training set into the GNN model, output the graph embedding representation input into the neural network model, and finally output the predicted value of the half-circle length of the circuit diagram data. Use the loss function to calculate the error between the predicted value and the true value, and update the weight parameters of the two models through backpropagation technology to complete an iterative process; repeat the iteration until the entire training set is traversed and one training period is completed;

[0012] S4. Repeat step S3 until the set number of training cycles is completed, input the validation set into the trained GNN model and neural network model, and save the weight parameters of the model that performs best on the validation set;

[0013] S5. Load the saved weight parameters into the GNN model and solidify them. Pass the M layout results of the circuit diagram data to be laid out through the GNN model and the neural network model in turn. Fine-tune the parameters of the neural network model by calculating the mean square error. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network are the position coordinates of the circuit to be laid out.

[0014] Furthermore, the process of step S1 is specifically as follows: determining a circuit diagram, mapping the circuit diagram into several layout diagrams, wherein the layout diagram includes: nodes and edges, wherein a node represents a module in a circuit, an edge represents a connection relationship between modules, a netlist file indicates the edge relationship between modules in the circuit diagram, and a module attribute file contains attribute information of the module.

[0015] Among them, each circuit diagram data is mapped into a graph through the actual circuit. This graph is composed of nodes and edges. A node represents a module in the circuit, and an edge represents the connection relationship between modules.

[0016] Furthermore, several layout diagrams of each circuit diagram share the same netlist file and module properties; the netlist files and module properties of several circuit diagrams are combined into a data set; the half-circuit length indicators of several circuit diagrams are used as labels, i.e., true values, and the data set is divided into a training set and a validation set.

[0017] Furthermore, the process of constructing the encoder model in step S2 is specifically as follows: specifying hyperparameters, including the number of network layers, and selecting a specific graph network layer to build a GNN model.

[0018] Furthermore, the process of constructing the decoder model in step S2 is specifically as follows: specifying hyperparameters, which include the number of network layers, input and output dimensions, setting the weight dimension of the last layer of the neural network to 2*R, where R is the number of modules in the circuit diagram data, and selecting the set network layer to build the neural network model.

[0019] Furthermore, the back propagation technology specifically back propagates the error between the predicted value and the true value through the Adam optimizer to achieve the update of the GNN model.

[0020] Furthermore, the training process of steps S3 and S4 is as follows:

[0021] S31. Set the number of iterations and the number of training periods, shuffle the order of the netlist files and module attribute files of several circuit diagrams in the training set, and input them into the GNN model in sequence. After encoding by the GNN model, the graph embedding representation of the currently input circuit diagram is obtained, and then the graph embedding representation is input into the decoder. The decoder output predicts the half-circle length value of the currently input circuit diagram.

[0022] S32. Use the loss function to calculate the error between the predicted value and the true value, use the Adam optimizer to backpropagate the error, update the weight parameters of the GNN model and the neural network model, and complete an iterative process. When the set number of iterations is reached or the entire training set is traversed, it is considered that one round of training is completed; when the model completes the set number of training rounds, the data in the validation set is input into the trained model, and the weight parameters of the GNN model and neural network model that perform best on the validation set are saved.

[0023] S33. Load the saved weight parameters into the model and solidify the weight parameter values ​​of the GNN model.

[0024] Furthermore, the loss function in step S3 is a mean square error function.

[0025] Furthermore, the step S5 is specifically as follows: after shuffling the order of the netlist files and module attribute files of several layout results of the circuit diagram data to be laid out, the netlist files and module attribute files are passed through the GNN model and the neural network model in turn to obtain the mean square error between the netlist files and the true value of the half-circle length, and only the weight parameters of the neural network model part are fine-tuned, and the weight parameters of the GNN model part remain unchanged. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network in the neural network model part are the position coordinates of the circuit layout.

[0026] A second aspect of the present invention provides a chip layout system based on a graph neural network, comprising a memory and a processor. The memory includes a chip layout program based on a graph neural network. When the chip layout program based on a graph neural network is executed by the processor, the following steps are implemented:

[0027] S1. Extracting netlist files and module attributes from circuit diagram data to construct a data set and dividing the data set into a training set and a validation set according to a preset ratio.

[0028] S2. Construct an encoder model, i.e., a GNN model, based on a graph neural network. The encoder is used to encode the netlist file and module attributes to obtain a graph embedding representation. Construct a decoder model, i.e., a neural network model, input the graph embedding representation into the decoder, and output the half-circle line length indicator to be predicted.

[0029] S3. Use the training set data to train the encoder and decoder, set the loss function of the entire network, input the training set into the GNN model, output the graph embedding representation input into the neural network model, and finally output the predicted value of the half-circle length of the circuit diagram data. Use the loss function to calculate the error between the predicted value and the true value, and update the weight parameters of the two models through backpropagation technology to complete an iterative process; repeat the iteration until the entire training set is traversed and one training period is completed.

[0030] S4. Repeat step S3 until the set number of training periods is completed, input the validation set into the trained GNN model and neural network model, and save the weight parameters of the model that performs best on the validation set.

[0031] S5. Load the saved weight parameters into the GNN model and solidify them. Pass the M layout results of the circuit diagram data to be laid out through the GNN model and the neural network model in turn. Fine-tune the parameters of the neural network model by calculating the mean square error. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network are the position coordinates of the circuit to be laid out.

[0032] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0033] The present invention provides a parsing layout method based on graph neural networks. By applying graph neural networks, the original input feature data, namely the attributes of each module in the chip and the chip netlist and other feature data, is encoded, thereby greatly improving the expressive ability of the original features; the half-circle length indicator is used as the output of the encoder to be predicted, and the position coordinates (x, y) of each module to be solved are used as the weights of the neural network for training through the application of a neural network structure to obtain the final circuit layout result; with powerful feature expression capabilities, the model has a faster convergence speed and better prediction results, realizing intelligent and efficient layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a flowchart of a parsing layout method based on graph neural network of the present invention.

[0035] Figure 2 This is a schematic diagram of an analytical layout method based on graph neural network in the present invention.

[0036] Figure 3 This is a schematic diagram of a parsing layout system based on graph neural network in the present invention. DETAILED DESCRIPTION

[0037] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0039] Example 1

[0040] like Figure 1 As shown, the present invention provides a parsing layout method based on a graph neural network, specifically comprising the following steps:

[0041] S1. Extracting netlist files and module attributes from circuit diagram data to construct a data set and dividing the data set into a training set and a validation set according to a preset ratio.

[0042] S2. Construct an encoder model, i.e., a GNN model, based on a graph neural network. The encoder is used to encode the netlist file and module attributes to obtain a graph embedding representation. Construct a decoder model, i.e., a neural network model, input the graph embedding representation into the decoder, and output the half-circle line length indicator to be predicted.

[0043] S3. Use the training set data to train the encoder and decoder, set the loss function of the entire network, input the training set into the GNN model, output the graph embedding representation input into the neural network model, and finally output the predicted value of the half-circle length of the circuit diagram data. Use the loss function to calculate the error between the predicted value and the true value, and update the weight parameters of the two models through backpropagation technology to complete an iterative process; repeat the iteration until the entire training set is traversed and one training period is completed;

[0044] S4. Repeat step S3 until the set number of training cycles is completed, input the validation set into the trained GNN model and neural network model, and save the weight parameters of the model that performs best on the validation set;

[0045] S5. Load the saved weight parameters into the GNN model and solidify them. Pass the M layout results of the circuit diagram data to be laid out through the GNN model and the neural network model in turn. Fine-tune the parameters of the neural network model by calculating the mean square error. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network are the position coordinates of the circuit to be laid out.

[0046] Furthermore, the process of step S1 is specifically as follows: determining a circuit diagram, mapping the circuit diagram into several layout diagrams, wherein the layout diagram includes: nodes and edges, wherein a node represents a module in a circuit, an edge represents a connection relationship between modules, a netlist file indicates the edge relationship between modules in the circuit diagram, and a module attribute file contains attribute information of the module.

[0047] Among them, each circuit diagram data is mapped into a graph through the actual circuit. This graph is composed of nodes and edges. A node represents a module in the circuit, and an edge represents the connection relationship between modules.

[0048] Furthermore, several layout diagrams of each circuit diagram share the same netlist file and module properties; the netlist files and module properties of several circuit diagrams are combined into a data set; the half-circuit length indicators of several circuit diagrams are used as labels, i.e., true values, and the data set is divided into a training set and a validation set.

[0049] Furthermore, the process of constructing the encoder model in step S2 is specifically as follows: specifying hyperparameters, including the number of network layers, and selecting a specific graph network layer to build a GNN model.

[0050] Furthermore, the process of constructing the decoder model in step S2 is specifically as follows: specifying hyperparameters, which include the number of network layers, input and output dimensions, setting the weight dimension of the last layer of the neural network to 2*R, where R is the number of modules in the circuit diagram data, and selecting the set network layer to build the neural network model.

[0051] Furthermore, the back propagation technology specifically back propagates the error between the predicted value and the true value through the Adam optimizer to achieve the update of the GNN model.

[0052] Furthermore, the training process of steps S3 and S4 is as follows:

[0053] S31. Set the number of iterations and the number of training periods, shuffle the order of the netlist files and module attribute files of several circuit diagrams in the training set, and input them into the GNN model in sequence. After encoding by the GNN model, the graph embedding representation of the currently input circuit diagram is obtained, and then the graph embedding representation is input into the decoder. The decoder output predicts the half-circle length value of the currently input circuit diagram.

[0054] S32. Use the loss function to calculate the error between the predicted value and the true value, use the Adam optimizer to backpropagate the error, update the weight parameters of the GNN model and the neural network model, and complete an iterative process. When the set number of iterations is reached or the entire training set is traversed, it is considered that one round of training is completed; when the model completes the set number of training rounds, the data in the validation set is input into the trained model, and the weight parameters of the GNN model and neural network model that perform best on the validation set are saved.

[0055] S33. Load the saved weight parameters into the model and solidify the weight parameter values ​​of the GNN model.

[0056] Furthermore, the loss function in step S3 is a mean square error function.

[0057] Furthermore, the step S5 is specifically as follows: after shuffling the order of the netlist files and module attribute files of several layout results of the circuit diagram data to be laid out, the netlist files and module attribute files are passed through the GNN model and the neural network model in turn to obtain the mean square error between the netlist files and the true value of the half-circle length, and only the weight parameters of the neural network model part are fine-tuned, and the weight parameters of the GNN model part remain unchanged. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network in the neural network model part are the position coordinates of the circuit layout.

[0058] Example 2

[0059] Based on the above embodiment 1, combined Figure 2 , this embodiment describes the process of the present invention in detail.

[0060] In a specific embodiment, the corresponding circuit diagram data extracted from N circuit diagrams, each circuit diagram data is mapped into a graph through the actual circuit, and this graph is composed of nodes and edges, a node represents a module in the circuit, and an edge represents the connection relationship between modules. Each circuit diagram data corresponds to M different circuit layout results and two files: a netlist file and a module attribute file. Taking the first circuit diagram data as an example, the circuit diagram contains 5 modules, and its M layouts share the netlist file of the circuit diagram data, but each has a different module attribute file. Among them, the netlist file indicates the edge relationship between the five modules in the first circuit diagram, and the module attribute file contains the attribute information of these five modules.

[0061] The netlist files and module property files for N circuit diagrams in the pre-prepared training set are shuffled and fed into the GNN model in sequence. After GNN encoding, a graph embedding representation of the input circuit diagram is obtained. This graph embedding representation is then fed into the neural network model, which outputs the model's predicted half-circuit length for the input circuit diagram. The error between the predicted and true values ​​is calculated using the mean squared error function, and the error is backpropagated using the Adam optimizer to update the model's weight parameters, completing one iteration. Once the entire training set has been traversed, one training epoch is complete. After the model completes the predetermined number of epochs, the data from the validation set is fed into the trained model, and the weight parameters of the model that performs best on the validation set are saved.

[0062] Load the saved model parameters and solidify the weight parameter values ​​of the GNN model, that is, keep the weight parameter values ​​​​no longer changing.

[0063] After shuffling the netlist files and module attribute files for the M layout results of the circuit diagram data to be laid out, the model is passed through the GNN model and the neural network model in sequence. After calculating the mean square error between the ideal half-circle length and the model parameters, only the weights of the neural network are fine-tuned, while the weights of the GNN model remain unchanged. Through iterative optimization, when the entire model outputs the optimal result, the weight parameters of the last layer of the neural network become the position coordinates of the circuit layout.

[0064] Example 3

[0065] like Figure 3 As shown, the present invention also provides a chip layout system based on a graph neural network, including a memory and a processor. The memory includes a chip layout program based on a graph neural network. When the chip layout program based on a graph neural network is executed by the processor, the following steps are implemented:

[0066] S1. Extracting netlist files and module attributes from circuit diagram data to construct a data set and dividing the data set into a training set and a validation set according to a preset ratio.

[0067] S2. Construct an encoder model, i.e., a GNN model, based on a graph neural network. The encoder is used to encode the netlist file and module attributes to obtain a graph embedding representation. Construct a decoder model, i.e., a neural network model, input the graph embedding representation into the decoder, and output the half-circle line length indicator to be predicted.

[0068] S3. Use the training set data to train the encoder and decoder, set the loss function of the entire network, input the training set into the GNN model, output the graph embedding representation input into the neural network model, and finally output the predicted value of the half-circle length of the circuit diagram data. Use the loss function to calculate the error between the predicted value and the true value, and update the weight parameters of the two models through backpropagation technology to complete an iterative process; repeat the iteration until the entire training set is traversed and one training period is completed.

[0069] S4. Repeat step S3 until the set number of training periods is completed, input the validation set into the trained GNN model and neural network model, and save the weight parameters of the model that performs best on the validation set.

[0070] S5. Load the saved weight parameters into the GNN model and solidify them. Pass the M layout results of the circuit diagram data to be laid out through the GNN model and the neural network model in turn. Fine-tune the parameters of the neural network model by calculating the mean square error. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network are the position coordinates of the circuit to be laid out.

[0071] Furthermore, the process of step S1 is specifically as follows: determining a circuit diagram, mapping the circuit diagram into several layout diagrams, wherein the layout diagram includes: nodes and edges, wherein a node represents a module in a circuit, an edge represents a connection relationship between modules, a netlist file indicates the edge relationship between modules in the circuit diagram, and a module attribute file contains attribute information of the module.

[0072] Among them, each circuit diagram data is mapped into a graph through the actual circuit. This graph is composed of nodes and edges. A node represents a module in the circuit, and an edge represents the connection relationship between modules.

[0073] Furthermore, several layout diagrams of each circuit diagram share the same netlist file and module properties; the netlist files and module properties of several circuit diagrams are combined into a data set; the half-circuit length indicators of several circuit diagrams are used as labels, i.e., true values, and the data set is divided into a training set and a validation set.

[0074] Furthermore, the process of constructing the encoder model in step S2 is specifically as follows: specifying hyperparameters, including the number of network layers, and selecting a specific graph network layer to build a GNN model.

[0075] Furthermore, the process of constructing the decoder model in step S2 is specifically as follows: specifying hyperparameters, which include the number of network layers, input and output dimensions, setting the weight dimension of the last layer of the neural network to 2*R, where R is the number of modules in the circuit diagram data, and selecting the set network layer to build the neural network model.

[0076] Furthermore, the back propagation technology specifically back propagates the error between the predicted value and the true value through the Adam optimizer to achieve the update of the GNN model.

[0077] Furthermore, the training process of steps S3 and S4 is as follows:

[0078] S31. Set the number of iterations and the number of training periods, shuffle the order of the netlist files and module attribute files of several circuit diagrams in the training set, and input them into the GNN model in sequence. After encoding by the GNN model, the graph embedding representation of the currently input circuit diagram is obtained, and then the graph embedding representation is input into the decoder. The decoder output predicts the half-circle length value of the currently input circuit diagram.

[0079] S32. Use the loss function to calculate the error between the predicted value and the true value, use the Adam optimizer to backpropagate the error, update the weight parameters of the GNN model and the neural network model, and complete an iterative process. When the set number of iterations is reached or the entire training set is traversed, it is considered that one round of training is completed; when the model completes the set number of training rounds, the data in the validation set is input into the trained model, and the weight parameters of the GNN model and neural network model that perform best on the validation set are saved.

[0080] S33. Load the saved weight parameters into the model and solidify the weight parameter values ​​of the GNN model.

[0081] Furthermore, the loss function in step S3 is a mean square error function.

[0082] Furthermore, the step S5 is specifically as follows: after shuffling the order of the netlist files and module attribute files of several layout results of the circuit diagram data to be laid out, the netlist files and module attribute files are passed through the GNN model and the neural network model in turn to obtain the mean square error between the netlist files and the true value of the half-circle length, and only the weight parameters of the neural network model part are fine-tuned, and the weight parameters of the GNN model part remain unchanged. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network in the neural network model part are the position coordinates of the circuit layout.

[0083] The icons in the accompanying drawings that describe the structural positional relationships are for illustrative purposes only and should not be construed as limitations on this patent.

[0084] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A parsing layout method based on graph neural network, characterized in that: The following steps are involved: S1, extracting netlist files and module attributes from circuit diagram data to construct a data set and dividing the data set into a training set and a validation set according to a preset ratio; S2. Build an encoder model, i.e., a GNN model, based on a graph neural network. The encoder is used to encode the netlist file and module attributes to obtain a graph embedding representation; build a decoder model, i.e., a neural network model, input the graph embedding representation into the decoder, and output the half-circle length indicator to be predicted; S3. Use the training set data to train the encoder and decoder, set the loss function of the entire network, input the training set into the GNN model, output the graph embedding representation input into the neural network model, and finally output the predicted value of the half-circle length of the circuit diagram data. Use the loss function to calculate the error between the predicted value and the true value, and update the weight parameters of the two models through backpropagation technology to complete an iterative process; repeat the iteration until the entire training set is traversed and one training period is completed; S4. Repeat step S3 until the set number of training cycles is completed, input the validation set into the trained GNN model and neural network model, and save the weight parameters of the model that performs best on the validation set; S5. Load the saved weight parameters into the GNN model and solidify them. Pass the M layout results of the circuit diagram data to be laid out through the GNN model and the neural network model in turn. Fine-tune the parameters of the neural network model by calculating the mean square error. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network are the position coordinates of the circuit to be laid out.

2. The analytical layout method based on graph neural network according to claim 1, characterized in that: The specific process of step S1 is: Determine a circuit diagram and map the circuit diagram into several layout diagrams. The layout diagram includes: nodes and edges, where a node represents a module in the circuit and an edge represents a connection relationship between modules. The netlist file indicates the edge relationship between modules in the circuit diagram, and the module attribute file contains the attribute information of the module.

3. The analytical layout method based on graph neural network according to claim 2 is characterized in that: Several layout diagrams of each circuit diagram share the same netlist file and module properties; the netlist files and module properties of several circuit diagrams are combined into a dataset; the half-circuit length indicators of several circuit diagrams are used as labels, i.e., true values, and the dataset is divided into a training set and a validation set.

4. The analytical layout method based on graph neural network according to claim 1, characterized in that: The process of building the encoder model in step S2 is specifically as follows: specifying hyperparameters, including the number of network layers, and selecting a specific graph network layer to build a GNN model.

5. The analytical layout method based on graph neural network according to claim 1 is characterized in that: The process of constructing the decoder model in step S2 is specifically as follows: specifying hyperparameters, which include the number of network layers, input and output dimensions, setting the weight dimension of the last layer of the neural network to 2*R, where R is the number of modules in the circuit diagram data, and selecting the set network layer to build the neural network model.

6. The analytical layout method based on graph neural network according to claim 1, characterized in that: The back propagation technology specifically back propagates the error between the predicted value and the true value through the Adam optimizer to achieve the update of the GNN model.

7. The analytical layout method based on graph neural network according to claim 6, characterized in that: The training process of steps S3 and S4 is as follows: S31. Set the number of iterations and the number of training periods, shuffle the netlist files and module attribute files of several circuit diagrams in the training set, and input them into the GNN model in sequence. After encoding by the GNN model, obtain the graph embedding representation of the currently input circuit diagram, and then input the graph embedding representation into the decoder. The decoder outputs the prediction to obtain the half-circle length value of the currently input circuit diagram. S32. Calculate the error between the predicted value and the true value using the loss function, backpropagate the error using the Adam optimizer, update the weight parameters of the GNN model and the neural network model, and complete an iterative process. When the set number of iterations is reached or the entire training set is traversed, it is considered that one phase of training is completed. When the model completes the set number of phases of training, input the data in the validation set into the trained model, and save the weight parameters of the GNN model and neural network model that perform best on the validation set. S33. Load the saved weight parameters into the model and solidify the weight parameter values ​​of the GNN model.

8. The analytical layout method based on graph neural network according to claim 1 or 7, characterized in that: The loss function in step S3 is a mean square error function.

9. The analytical layout method based on graph neural network according to claim 1, characterized in that: The step S5 specifically includes: after shuffling the order of the netlist files and module attribute files of several layout results of the circuit diagram data to be laid out, passing them through the GNN model and the neural network model in turn, and obtaining the mean square error between them and the true value of the half-circle line length, only the weight parameters of the neural network model part are fine-tuned, and the weight parameters of the GNN model part remain unchanged. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network in the neural network model part are the position coordinates of the circuit layout.

10. A chip layout system based on a graph neural network, comprising a memory and a processor, wherein the memory includes a chip layout program based on a graph neural network, and when the chip layout program based on a graph neural network is executed by the processor, the following steps are implemented: S1, extracting netlist files and module attributes from circuit diagram data to construct a data set and dividing the data set into a training set and a validation set according to a preset ratio; S2. Build an encoder model, i.e., a GNN model, based on a graph neural network. The encoder is used to encode the netlist file and module attributes to obtain a graph embedding representation; build a decoder model, i.e., a neural network model, input the graph embedding representation into the decoder, and output the half-circle length indicator to be predicted; S3. Use the training set data to train the encoder and decoder, set the loss function of the entire network, input the training set into the GNN model, output the graph embedding representation input into the neural network model, and finally output the predicted value of the half-circle length of the circuit diagram data. Use the loss function to calculate the error between the predicted value and the true value, and update the weight parameters of the two models through backpropagation technology to complete an iterative process; repeat the iteration until the entire training set is traversed and one training period is completed; S4. Repeat step S3 until the set number of training cycles is completed, input the validation set into the trained GNN model and neural network model, and save the weight parameters of the model that performs best on the validation set; S5. Load the saved weight parameters into the GNN model and solidify them. Pass the M layout results of the circuit diagram data to be laid out through the GNN model and the neural network model in turn. Fine-tune the parameters of the neural network model by calculating the mean square error. After a set number of iterative optimizations, the weight parameters of the last layer of the neural network are the position coordinates of the circuit to be laid out.

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