An inference mapping scheme that optimizes conductance drift

Abstract

The application belongs to the technical field of conductance drift, and particularly relates to a reasoning mapping scheme for optimizing conductance drift, which comprises the following steps: S1: according to a conductance drift model, fitting actual device conductance drift data to obtain model parameters; S2: scaling input data and weights respectively as a weight input voltage V0 and a target mapping conductance C; S3: processing the input signal through the S2 step into the weight input voltage V0, multiplying the weight input voltage V0 by a decay factor to obtain a final input voltage V, and then mapping the final input voltage V to a memristor array through a peripheral board card circuit. Compared with a traditional method, the scheme provided by the patent solves the conductance drift problem, optimizes the performance of the system through a unique mechanism of multiplying the input signal by a compensation factor, and directly provides the compensation of the conductance drift by the input signal, thereby reducing the difficulty of hardware network implementation. The system using the scheme can reach an accuracy of 96% after being trained for 20 times, and the accuracy is improved by 10% compared with the traditional scheme.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of conductance drift, and particularly relates to an inference mapping scheme for optimizing conductance drift. BACKGROUND

[0002] Memristor is a fast, low-power, high-integration device, which is considered as a powerful competitor to solve Moore's law, break through the storage wall and the power wall. With the development of artificial intelligence, the availability of non-volatile memory arrays such as phase change memristor and resistive memory promotes the development of many neural network architectures, which not only accelerate the inference speed of the network through parallel operation, but also replace the traditional computer operation to a certain extent, thereby reducing power consumption.

[0003] However, due to some non-ideal factors of the memristor, these have a great influence on network inference mapping, among which the conductance drift will cause the loss of mapping weight information, thereby reducing the network output accuracy. At present, there are few solutions to the conductance drift of the memristor network, and the latest solution is to compensate the conductance drift by changing the slope of the activation function, but this is relatively difficult for the hardware implementation of such an activation function. SUMMARY

[0004] In view of the deficiencies of the prior art, the purpose of the application is to provide an inference mapping scheme for optimizing conductance drift.

[0005] The purpose of the application can be achieved by the following technical scheme:

[0006] An inference mapping scheme for optimizing conductance drift, the method comprising the following steps:

[0007] S1: According to the conductance drift model, the actual device conductance drift data is fitted to obtain the model parameters;

[0008] S2: In the ideal state of the memristor array, the input data and the weight are respectively scaled as the weight input voltage V0 and the purpose mapping conductance C.

[0009] S3: The input signal is processed into the weight input voltage V0 through the step S2, and multiplied by a decay factor to obtain the final input voltage V, and then mapped to the memristor array through the peripheral board circuit.

[0010] Further, in the step S1, the conductance drift model adopts the formula:

[0011]

[0012] Wherein: G0 is the initial conductance, v is the decay coefficient, t0 is the initial time, and G is the conductance at time t.

[0013] Further, in the step S2, the formula of the weight input voltage V0 and the target mapping conductance C is:

[0014]

[0015]

[0016] wherein: V data is the initial input voltage, W max and W min are the maximum and minimum values of the mapping weight respectively, C max and C min are the maximum and minimum conductances of the memristor respectively.

[0017] Further, in the step S3, the formula of the final input voltage V is:

[0018]

[0019] The beneficial effects of the present application: compared with the traditional method, the scheme proposed in the patent solves the conductance drift problem, optimizes the performance of the system through the unique mechanism of multiplying the input signal by a compensation factor, and the compensation of the conductance drift can be directly provided by the input signal, reducing the difficulty of hardware network implementation. In order to reflect the feasibility and practicability of the scheme, we compare it on the mnist handwritten digital recognition task. The simulation results show that the system using the scheme can reach 96% accuracy after 20 times of training, which is 10% higher than the accuracy of the traditional scheme. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0021] Figure 1 is the method flowchart in the embodiment of the present application;

[0022] Figure 2 is the simulation result of the traditional reasoning mapping method in-place training;

[0023] Figure 3 is the simulation result of the reasoning mapping method with drift compensation in the embodiment of the present application. DETAILED DESCRIPTION

[0024] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the protection scope of the present application.

[0025] An inference mapping scheme for optimizing conductance drift, as shown in Figure 1 , the scheme comprises the following steps:

[0026] S1: According to the conductance drift model, the model parameters are obtained by fitting the actual device conductance drift data, and the conductance drift model adopts the formula:

[0027]

[0028] Wherein: G0 is the initial conductance, v is the attenuation coefficient, t0 is the initial time, and G is the conductance at time t.

[0029] S2: Without considering the electric drift state, the input data and the weight are scaled respectively, as the weight input voltage V0 and the purpose mapping conductance C, and the formula adopted is:

[0030]

[0031]

[0032] Wherein: W max and W min are the maximum and minimum values of the mapping weight respectively, C max and C min are the maximum conductance and minimum conductance of the memristor respectively.

[0033] S3: The input signal is processed to the weight input voltage V0 through S2 step, and multiplied by an attenuation factor to obtain the final input voltage V, and then mapped to the memristor array through the peripheral board card circuit, and the specific formula is as follows:

[0034]

[0035] In this way, the input electrical signal and the weight matrix are scaled according to different parameters, and then the input voltage is multiplied by an attenuation factor to obtain the final input voltage, so as to solve the problem of weight information loss caused by conductance drift in the inference mapping process. In this way, the compensation for conductance drift can be directly provided by the input signal, and the difficulty of hardware network implementation is reduced.

[0036] In the description of the specification, reference to a term "one embodiment", "an example", "a specific example" or the like means that a particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Descriptive terms of the above terms do not necessarily refer to the same embodiment or example in the specification. Also, the specific features, structures, materials or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0037] The above shows and describes the basic principles, main features and advantages of the application. Those skilled in the art should understand that the application is not limited to the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the application. Without departing from the spirit and scope of the application, various changes and improvements can be made to the application, and these changes and improvements all fall within the scope of the application.

Claims

1. An inference mapping scheme that optimizes conductance drift, characterized by, The method comprises the following steps: S1: fitting the actual device conductance drift data according to a conductance drift model to obtain model parameters; S2: the input data and the weight value are scaled respectively as the weight input voltage in the ideal state of the memristor array with destination mapping conductance ; S3: the input signal is processed by S2 step to weight input voltage , and multiplied by a decay factor to get the final input voltage , and then mapped to the memristor array through the peripheral board circuit In the step S2, the weight input voltage is obtained The purpose mapping conductance The formula used is: （2） （3） wherein: is the initial input voltage, and are the maximum and minimum of the mapping weight, respectively, and are the maximum and minimum conductance of the memristor, respectively.

2. The reasoning mapping scheme of claim 1, wherein, In the step S1, the conductance drift model adopts the formula: （1） wherein: is the initial conductance, is the decay coefficient, is the initial time, is the time conductance.

3. The reasoning mapping scheme of claim 2, wherein, In the step S3, the final input voltage The calculation formula is: （4）。

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