A MIPI RFFE interface address expansion circuit, method and related equipment

Abstract

A MIPI RFFE interface address expansion circuit and mobile terminal, comprising: a selection signal configuration circuit having an input connected to an ADDR port for outputting a selection signal matching a target signal connected to the ADDR port, the target signal being any one of a VDD signal, a GND signal, an SCLK signal, or an SDATA signal; and an address selection circuit selecting and outputting a USID address matching the selection signal. The selection signal configuration circuit outputs a selection signal matching the target signal obtained from the ADDR port. After obtaining the selection signal, the address selection circuit retrieves and outputs a preset USID address matching the selection signal, thereby achieving interface address expansion for the MIPI communication interface chip. This solution eliminates the need to increase the size of the MIPI communication interface chip, its associated packaging size, testing time, and so on, resulting in low costs.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a MIPI RFFE interface address expansion circuit, method, and related equipment. Background Art

[0002] With the continuous advancement of communication technology, the demand for RF front-end equipment (such as power amplifiers, low-noise amplifiers, antenna tuners, filters, switches, etc.) is also increasing. To meet usage requirements, RF equipment manufacturers face the challenge of complex control of a wide range of devices. In response, the MIPI (Mobile Industry Processor Interface) Alliance has proposed an RFFE radio frequency front-end bus interface for connecting one or more radio frequency integrated circuits (RFICs) in a mobile terminal to its associated front-end module (FEM) for control and monitoring.

[0003] The MIPI RFFE standard defines an interface between RFFE devices, such as Figure 1 As shown in Figure 2, a single RFFE bus can host up to four master RFICs and 15 slave FEMs. The bus consists of clock signal lines (SCLK) and SDATA. SCLK is controlled by the host, while SDATA is a bidirectional data line for data transmission. Both the master RFIC and the slave FEMs can control it. Each slave FEM on the RFFE bus can be identified by the master RFIC using its unique USID, product ID, and manufacturer ID.

[0004] In the prior art, the MIPI RFFE command sequence mainly consists of the following three parts, in order:

[0005] 1. Transmission of sequence start conditions;

[0006] 2. Frame transmission (including one command frame, 0, 1 or more address / data frames, depending on the type of command frame);

[0007] 3. Bus Park Cycle;

[0008] Taking the register write instruction as an example, a typical MIPI communication includes the following process: Figure 2 As shown:

[0009] (1) The master device RFIC sends a start signal "SSC" to start a communication;

[0010] (2) The master device RFIC then sends a command frame. The command frame consists of a 4-bit slave device FEM device address USID, a 3-bit register write identification code, a 5-bit register address, and a 1-bit parity bit. The command frame is used by the slave device FEM to identify the type of instruction sent by the host. For example, MIPI RFFE has a total of 8 read and write instructions, and different read and write instructions correspond to different command frames;

[0011] (3) The master RFIC then generates a data frame. This data frame consists of 8 bits of data and 1 parity bit. It can be data that the master RFIC wants to send to the slave FEM, or data that the master RFIC reads from the slave FEM. These data have different functions depending on the scenario.

[0012] (4) The master device RFIC sends a BPC command to end the communication and release the bus.

[0013] In a communication, the USID is included in the command frame to identify whether the slave device FEM is the device that the master device RFIC is communicating with correctly. Only after the USID matches successfully can the slave device FEM continue to receive other command frames, address frames or data frames from the master device RFIC.

[0014] However, if multiple slave FEMs with the same USID / PID / MID are required in an RF front-end system, that is, the USID / PID / MID of each slave FEM is the same, the master RFIC cannot correctly distinguish these slave FEMs. In order to allow the MIPI bus to mount more similar devices, the common practice is to extend the device address.

[0015] The solution disclosed in the prior art is to use a single ADDR port as the address extension bus of the MIPI communication interface chip. Figure 3a and Figure 3b As shown, Figure 3a and Figure 3b It is an existing MIPI communication interface chip. The chip contains SCLK, SDATA, ADDR, VIO power supply and GND. By adding an ADDR terminal to the chip and connecting the ADDR terminal to VCC or GND, the chip address can be distinguished. In this way, a chip can have two addresses to choose from. In this way, when the circuit is implemented, it only needs to identify the level of the ADDR input from the chip to set the corresponding USID configuration. For example, Figure 3a The ADDR end is connected to the VIO segment, and its corresponding USID is 0010. Figure 3b The ADDR end is connected to the GND segment, and its corresponding USID is 0011.

[0016] The applicant analyzed existing solutions and discovered that they use a single ADDR port as the address expansion bus for the MIPI communication interface chip. By connecting the ADDR port to either VCC or GND, the chip address is distinguished, allowing a single chip to have two address options. However, RF front-end systems are becoming increasingly complex, and a single MIPI bus may potentially host more than two similar chips. If this technology were still used, address conflicts would inevitably occur due to a limited number of chip address options. Increasing the number of address ports would increase chip size, package size, test time, and other factors, raising chip costs. Summary of the Invention

[0017] In view of this, an embodiment of the present invention provides a MIPI RFFE interface address expansion circuit and a mobile terminal, so as to reduce the chip cost while increasing the number of address ports of the MIPI communication interface chip.

[0018] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0019] A MIPI RFFE interface address expansion circuit, comprising:

[0020] A selection signal configuration circuit, wherein the input end of the selection signal configuration circuit is connected to the ADDR port, and the ADDR port is used to be connected to the target pin of the MIPI communication interface chip, and is used to receive the target signal output by the target pin of the MIPI communication interface chip, and output a selection signal that matches the target signal output by the ADDR port, wherein the target signal is any one of a VDD signal, a GND signal, an SCLK signal or an SDATA signal, wherein the VDD signal is the signal of the VDD pin of the MIPI communication interface chip in the RF front-end system, the GND signal is the signal of the GND pin of the MIPI communication interface chip in the RF front-end system, the SCLK signal is the signal of the SCLK pin of the MIPI communication interface chip in the RF front-end system, and the SDATA signal is the signal of the SDATA pin of the MIPI communication interface chip in the RF front-end system;

[0021] The address selection circuit is used to select and output a USID address that matches the selection signal.

[0022] Optionally, the MIPI RFFE interface address expansion circuit includes:

[0023] The selection signal configuration circuit includes:

[0024] N latches, where N is a positive integer greater than 1;

[0025] A logic unit, wherein the signal input end of any latch is connected to the ADDR port and the output end of the latch through the logic unit corresponding to the latch, and the configuration of the logic unit satisfies the condition that when the signal input ends of different latches obtain different target signals, the output signals of different latches are different;

[0026] The clock signal input terminal of the latch is used to obtain the SCLK clock signal;

[0027] The RN ports of N-1 latches of the N latches and the SN port of the remaining latch are used to obtain the SSC start signal sent by the master device, and the start signal is used to reset the N latches;

[0028] A decoder, wherein the input end of the decoder is connected to the output end of the N latches, and is used to output a decoding signal adapted to the output signals of the N latches, and the decoding signal serves as the selection signal.

[0029] Optionally, in the above-mentioned MIPI RFFE interface address expansion circuit, the address selection circuit includes:

[0030] M registers, where M is a positive integer greater than 1;

[0031] The register stores a preset USID address, and different registers store different USID addresses;

[0032] The selector is used to select and output the USID address of the register that matches the selection signal.

[0033] Optionally, in the above-mentioned MIPI RFFE interface address expansion circuit, the value of N is 3.

[0034] Optionally, in the above-mentioned MIPI RFFE interface address expansion circuit, the logic unit includes:

[0035] a first logic OR gate, the first logic OR gate being arranged between the ADDR port, the output terminal of the first latch, and the signal input terminal of the first latch, the first input terminal of the first logic OR gate being connected to the ADDR port, the second input terminal of the first logic OR gate being connected to the output terminal of the first latch, and the output terminal of the first logic OR gate being connected to the signal input terminal of the first latch;

[0036] a second logic OR gate, the second logic OR gate being arranged between the ADDR port, the output terminal of the second latch, and the signal input terminal of the second latch, the first input terminal of the second logic OR gate being connected to the ADDR port, the second input terminal of the second logic OR gate being connected to the output terminal of the second latch, and the output terminal of the second logic OR gate being connected to the signal input terminal of the second latch;

[0037] An inverter, wherein the second latch obtains an SCLK clock signal through the inverter;

[0038] A logic AND gate is arranged between the ADDR port, the output end of the third latch and the signal input end of the third latch, the first input end of the logic AND gate is connected to the ADDR port, the second input end of the logic AND gate is connected to the output end of the third latch, and the output end of the logic AND gate is connected to the signal input end of the third latch.

[0039] Optionally, the MIPI RFFE interface address expansion circuit further includes:

[0040] A delay circuit is provided between the ADDR port and the N latches.

[0041] Optionally, in the above-mentioned MIPI RFFE interface address expansion circuit, the value of M is 4.

[0042] A mobile terminal, applying any one of the MIPI RFFE interface address expansion circuits described above.

[0043] A MIPI RFFE interface address extension method, applying any one of the above-mentioned MIPI RFFE interface address extension circuits, the method comprising:

[0044] Obtain a target signal output by a target pin of the MIPI communication interface chip through the ADDR port, where the target signal is any one of a VDD signal, a GND signal, an SCLK signal, or an SDATA signal. The VDD signal is a signal of a VDD pin of the MIPI communication interface chip in the RF front-end system, the GND signal is a signal of a GND pin of the MIPI communication interface chip in the RF front-end system, the SCLK signal is a signal of an SCLK pin of the MIPI communication interface chip in the RF front-end system, and the SDATA signal is a signal of an SDATA pin of the MIPI communication interface chip in the RF front-end system;

[0045] outputting a selection signal that matches the target signal;

[0046] The USID address that matches the selection signal is selected and output.

[0047] A radio frequency system comprising: a master device, a slave device, a bus, and any one of the above-mentioned MIPI RFFE interface address expansion circuits;

[0048] The MIPI RFFE interface address expansion circuit is integrated in the slave device and is connected to the MIPI communication interface chip in the master device through the bus. The USID address provided by the MIPI RFFE interface address expansion circuit serves as the identity of the slave device.

[0049] Based on the above technical solution, the above solution provided by the embodiment of the present invention outputs a selection signal matching the target signal obtained by the ADDR port through the selection signal configuration circuit 100, and after obtaining the selection signal, the address selection circuit 200 retrieves and outputs the preset USID address matching the selection signal, thereby realizing the interface address expansion of the MIPI communication interface chip. It can be seen that in the above solution, there is no need to increase the size of the MIPI communication interface chip and the related package size, test time, etc., so there is no need to increase the cost of the MIPI communication interface chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0051] Figure 1 Schematic diagram of the interface between RFFE devices defined by the MIPI RFFE standard;

[0052] Figure 2 This is a typical MIPI communication process diagram;

[0053] Figure 3a and Figure 3b They are respectively structural schematic diagrams of existing MIPI communication interface chips;

[0054] Figure 4 A schematic diagram of the structure of the MIPI RFFE interface address expansion circuit provided in an embodiment of the present application;

[0055] Figure 5 A schematic diagram of the structure of the selection signal configuration circuit in the MIPI RFFE interface address expansion circuit provided in an embodiment of the present application;

[0056] Figure 6A schematic diagram of the structure of a logic unit in a MIPI RFFE interface address expansion circuit provided in an embodiment of the present application;

[0057] Figure 7 A signal timing diagram of the communication process when the ADDR port obtains the VDD signal in the MIPI RFFE interface address expansion circuit provided in an embodiment of the present application;

[0058] Figure 8 A signal timing diagram of the communication process when the ADDR port obtains the GND signal in the MIPI RFFE interface address expansion circuit provided in an embodiment of the present application;

[0059] Figure 9 A signal timing diagram of the communication process when the ADDR port obtains the SCLK clock in the MIPI RFFE interface address expansion circuit provided in an embodiment of the present application;

[0060] Figure 10 A signal timing diagram of the communication process when the ADDR port obtains the SDATA signal in the MIPI RFFE interface address expansion circuit provided in an embodiment of the present application;

[0061] Figure 11 This is a schematic diagram of the structure of the address selection circuit in the MIPI RFFE interface address expansion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0063] In order to reduce chip costs while increasing the number of address ports on the MIPI communication interface chip, this application discloses a MIPI RFFE interface address expansion circuit, see Figure 4 , the expansion circuit may include:

[0064] Select signal configuration circuit 100 and address selection circuit 200;

[0065] See also Figure 4 The input end of the selection signal configuration circuit 100 is connected to the ADDR port, and the ADDR port is connected to the ADDR port. Figure 3a and Figure 3bThe ADDR port shown in , in this solution, the ADDR port is used to connect to the target pin of the MIPI communication interface chip, and obtain the target signal through the target pin. In this solution, the target signal obtained by the ADDR port can be any one of the VDD signal, GND signal, SCLK signal or SDATA signal, see Figure 3a and Figure 3b As shown, the VDD signal, GND signal, SCLK signal or SDATA signal can be obtained through the relevant pins of the MIPI communication interface chip, the VDD signal is the signal of the VDD pin of the MIPI communication interface chip in the RF front-end system, the GND signal is the signal of the GND pin of the MIPI communication interface chip in the RF front-end system, the SCLK signal is the signal of the SCLK pin of the MIPI communication interface chip in the RF front-end system, and the SDATA signal is the signal of the SDATA pin of the MIPI communication interface chip in the RF front-end system. In this solution, the input end of the selection signal configuration circuit 100 is used to obtain the target signal output by the target pin of the MIPI communication interface chip through the ADDR port, and output a selection signal matching the target signal. The target signal obtained by the ADDR port is different, and the selection signal output by the selection signal configuration circuit 100 is different. The selection signal output by the selection signal configuration circuit 100 can change according to the different target signals obtained by the ADDR port, and each target signal corresponds to a unique selection signal.

[0066] In this solution, the address selection circuit 200 stores a preset USID address that matches the number of the target signals. The input end of the address selection circuit 200 is connected to the output end of the selection signal configuration circuit 100. After obtaining the selection signal, the address selection circuit 200 is used to call the preset USID address that matches the selection signal based on the selection signal, and output the called USID address as the USID address that matches the MIPI communication interface chip.

[0067] In the technical solution disclosed in the embodiment of the present application, the selection signal configuration circuit 100 output is connected to the target pin of the MIPI communication interface chip through the ADDR port, thereby obtaining the target signal output by the target pin of the MIPI communication interface chip, and outputting a selection signal matching the target signal. After obtaining the selection signal, the address selection circuit 200 retrieves and outputs the preset USID address matching the selection signal, thereby realizing the interface address expansion of the MIPI communication interface chip. It can be seen that in the above solution, there is no need to increase the size of the MIPI communication interface chip and the related packaging size, test time, etc., and thus there is no need to increase the cost of the MIPI communication interface chip.

[0068] The specific structure of the selection signal configuration circuit can be designed based on user needs, as long as it can ensure that the selection signal configuration circuit outputs an adaptive selection signal according to the acquired target signal. For example, in this solution, the selection signal configuration circuit can be a circuit composed of a logical digital logic circuit. For details, see Figure 5 The circuit may include: a latch 101, a logic unit 102, and a decoder 103. The number of the latches 101 is N, and N is a positive integer greater than 1. The latch may be a D flip-flop. For example, in this solution, the value of N may be 3, that is, the selection signal configuration circuit may include three latches 101.

[0069] See also Figure 5 The signal input end of the latch 101 is connected to the ADDR port and the output end of the latch 101 through the logic unit 102. When the latch 101 is a D flip-flop, the signal input end of the latch 101 is the D input end, and the output end of the latch 101 is the Q output end. The configuration mode of the logic unit 102 satisfies the condition: when the signal input ends of different latches 101 obtain the target signal, the output signals of different latches are different; in this solution, the target signal collected by the ADDR port is processed by the logic unit 102, and the processed target signal is sent to the latch 101. The latch 101 outputs a latch signal through the output end based on the processed target signal. In this solution, the output latch signals of the N latches 101 are sent to the decoder, see Figure 5 , the clock signal input end of the latch 101 is used to obtain the SCLK clock signal; the RN port of the latch is used to obtain the SSC start signal sent by the master device, and the SSC start signal is used to provide a reset service for the latch 101; the SCLK clock signal and the SSC start signal can be obtained by the clock signal line SCLK and the bidirectional data line SDATA in the RFFE bus.

[0070] In this solution, the input end of the decoder 103 is connected to the output end of the N latches 101, and is used to output a decoding signal adapted to the output signals of the N latches 101, and the decoding signal serves as the selection signal.

[0071] See also Figure 6 In a specific embodiment disclosed in this application, the logic unit 102 may specifically include:

[0072] A first logic OR gate U1, a second logic OR gate U2, an inverter U3 and a logic AND gate U4;

[0073] The first logic OR gate U1 is provided between the ADDR port, the output end of the first latch 1 and the signal input end of the first latch 1, the first input end of the first logic OR gate U1 is connected to the ADDR port, the second input end of the first logic OR gate U1 is connected to the output end of the first latch 1, the output end of the first logic OR gate U1 is connected to the signal input end of the first latch 1, and the first logic OR gate U1 is used to perform a logic OR process on the latch signal output by the first latch 1 and the target signal acquired by the ADDR port;

[0074] a second logic OR gate U2, the second logic OR gate U2 being arranged between the ADDR port, the output end of the second latch 2 and the signal input end of the second latch 2, the first input end of the second logic OR gate U2 being connected to the ADDR port, the second input end of the second logic OR gate U2 being connected to the output end of the second latch 2, the output end of the second logic OR gate U2 being connected to the signal input end of the second latch 2, the second logic OR gate U2 being used to perform a logic OR process on the latch signal output by the second latch 2 and the target signal acquired by the ADDR port;

[0075] Inverter U3, the second latch 2 obtains the SCLK clock signal through the inverter U3, and the inverter U3 is used to perform inverse processing on the SCLK clock signal;

[0076] A logic AND gate U4 is arranged between the ADDR port, the output end of the third latch 3 and the signal input end of the third latch 3. The first input end of the logic AND gate U4 is connected to the ADDR port, the second input end of the logic AND gate U4 is connected to the output end of the third latch 3, and the output end of the logic AND gate U4 is connected to the signal input end of the third latch 3. The logic AND gate U4 performs logic AND processing on the latch signal output by the third latch 3 and the target signal obtained by the ADDR port.

[0077] In the technical solution disclosed in the embodiments of this application, because the ADDR port is connected to the clock line SCLK, there is a situation where SCLK samples SCLK. Therefore, in order to ensure the setup time of the digital circuit timing, it is necessary to delay the target signal obtained by the ADDR port. Therefore, the above circuit can also include a delay circuit, which is arranged between the ADDR port and the N latches.

[0078] exist Figure 6 In the scheme shown, when a complete RFFE sequence is sent to the slave FEM, Figure 2 For example, the master device RFIC first sends the SSC start signal, followed by the 4-bit device address USID, and the subsequent command frame, address frame, and data frame.

[0079] When the slave FEM receives the SSC signal, the address expansion circuit is reset or set to its initial state. As shown in the circuit diagram, SSC is connected to the reset RN, reset RN, and set SN terminals of latches 1 / 2 / 3, respectively. Therefore, after receiving the SSC signal, the initial states of the latch signals S1 / S2 / S3 output by latches 1 / 2 / 3 are 0 / 0 / 1. Below, we analyze four scenarios where the ADDR port is connected to the target signals VDD / GND / SCLK / SDATA, respectively.

[0080] 1. ADDR port obtains VDD signal;

[0081] After receiving the SSC start signal from the device FEM, the latch in the MIPI RFFE interface address expansion circuit is reset, and the initial state of the latch signal S1 / S2 / S3 output by the latch 1 / 2 / 3 is 0 / 0 / 1. The latch signal S1 will be set to 1 after the first rising edge of the SCLK signal arrives, and will be latched until the SSC signal of the next RFFE communication arrives; the latch signal S2 will be set to 1 after the first falling edge of the SCLK signal arrives, and will be latched until the SSC start signal of the next RFFE communication arrives; since the initial state of S3 is 1, after the rising edge of the SCLK signal arrives, S3 will remain at 1. Therefore, the latch signal S1 / S2 / S3 output by the latch 1 / 2 / 3 is 111, and the USID of the slave device FEM can be set to the preset USID of A through this result. The specific process timing diagram is as follows Figure 7 shown.

[0082] 2. The ADDR port is connected to the GND signal;

[0083] After receiving the SSC start signal from the device FEM, the latch in the MIPI RFFE interface address expansion circuit is reset, and the initial state of the latch signal S1 / S2 / S3 output by the latch 1 / 2 / 3 is 0 / 0 / 1. Since the signal obtained by the ADDR port is a normally low signal, the latch signal S1 will remain at 0 after the rising edge of the SCLK signal arrives; the latch signal S2 will remain at 0 after the falling edge of the SCLK signal arrives; since the initial state of the latch signal S3 is 1, after the rising edge of the SCLK signal arrives, the latch signal S3 will be set to 0 and will be latched until the SSC start signal of the next RFFE communication arrives. Therefore, when the ADDR port is connected to the GND signal, the latch signal S1 / S2 / S3 output by the latch 1 / 2 / 3 is 000, and this result can be used to set the USID of the slave device FEM to the preset USID of B. The specific process timing diagram is as follows Figure 8 shown.

[0084] 3. The ADDR port is connected to the SCLK clock cable. The SCLK signal obtained by the ADDR port is delayed by a delay device. The ADDR_DLY signal output by the delay device is the delayed SCLK signal.

[0085] After receiving the SSC start signal from the device FEM, the latch in the MIPI RFFE interface address expansion circuit is reset, and the latch signals S1 / S2 / S3 output by the latches 1 / 2 / 3 are in the initial state 0 / 0 / 1. Since the target signal obtained by latch 1 / 2 / 3 is the ADDR_DLY signal, and the ADDR_DLY signal is a delayed signal of SCLK, that is, the target signal obtained by the latch 1 / 2 / 3 through the delayer and the ADDR port is a delayed signal of SCLK, that is, when the SCLK rises, the target signal obtained by the latch 1 / 2 / 3 is 0, and when the SCLK falls, the target signal obtained by the latch 1 / 2 / 3 is 1. Therefore, the latch signal S1 will remain at 0 after the rising edge of the SCLK signal arrives; the latch signal S2 will remain at 0 after the falling edge of the SCLK signal arrives; since the latch signal S3 is initially 1, after the rising edge of the SCLK signal arrives, the latch signal S3 will be set to 0, and will be latched until the SSC start signal of the next RFFE communication arrives. Therefore, when the ADDR port obtains the SCLK signal, the latch signal S1 / S2 / S3 output by the latch 1 / 2 / 3 is 010, and the USID of the slave device FEM can be set to the preset USID of C through this result. The specific process timing diagram is as follows Figure 9 shown.

[0086] 4. ADDR is connected to SDATA, and the ADDR_DLY signal is the delayed SDATA signal

[0087] After the slave FEM receives the SSC start signal, the address expansion circuit is reset or set to its initial state. The latch signals S1 / S2 / S3 output by latches 1 / 2 / 3 are initially set to 0 / 0 / 1. Because the ADDR_DLY signal is a delayed signal of SDATA, according to the RFFE timing, the SDATA value is sampled at both the rising and falling edges of SCLK. It is important to note that existing solutions cannot detect MIPI devices with all-0 or all-1 addresses (the RFFE protocol defines all-0 as a broadcast address and does not define it as a slave device USID). The latch signal S1 will be set to 1 when SDATA is sampled as 1 on the rising edge of SCLK, and will be latched until the next SSC start signal of RFFE communication arrives; the latch signal S2 will be set to 1 when SDATA is sampled as 1 on the falling edge of SCLK, and will be latched until the next SSC start signal of RFFE communication arrives; the latch signal S3 is initially 1, so when SDATA is sampled as 0 on the rising edge of SCLK, the latch signal S3 is set to 0, and will be latched until the next SSC start signal of RFFE communication arrives. Therefore, when the ADDR port is connected to SDATA, the latch signals S1 / S2 / S3 output by the latches 1 / 2 / 3 are 110, and this result can be used to set the USID of the slave device FEM to the preset USID of D. The specific process timing diagram is as follows Figure 10 shown.

[0088] From the above analysis, it can be found that when the target signals obtained by the ADDR interface are VCC, GND, SCLK, and SDATA, the latch signals S1 / S2 / S3 output by latches 1 / 2 / 3 are 111, 000, 010, and 110, respectively. Furthermore, the address expansion circuit can encode the different outputs of S1 / S2 / S3 into multiple preset USID addresses, thereby implementing address expansion for the RFFE slave device.

[0089] In this solution, M USID addresses can be pre-stored in the address selection circuit. The value of M can be selected based on user needs. In this solution, the value of M matches the combination result of the latch signals S1 / S2 / S3. That is, the value of M is 4. When the address selection circuit obtains the decoded signal obtained after the decoder decodes the latch signals S1 / S2 / S3 output by the latch 1 / 2 / 3, it retrieves and outputs the USID that matches the decoded signal from the pre-stored M USID addresses. In this solution, the address selection circuit can be a microprocessor or a microprocessor. Figure 9 The circuit structure shown, for example, see Figure 11The address selection circuit may include M registers and a selector. Each register stores a preset USID address, and different registers store different USID addresses. When the value of M is 4, the USID address stored in the first register is A, the USID address stored in the second register is B, the USID address stored in the third register is C, and the USID address stored in the fourth register is D. The selector is used to select and output the USID address of the register that matches the selection signal.

[0090] exist Figure 11 In the specific embodiment shown, four registers ID1 / ID2 / ID3 / ID4 are used respectively, and the default values ​​of the four registers are USID1, USID2, USID3, and USID4, which are the pre-stored USID addresses. The default values ​​of these four registers can be changed through internal USID programming. Based on this and the MIPI RFFE interface address expansion circuit of the present invention, the USID of the slave device FEM is ultimately the register value selected by S1 / S2 / S3. When S0 / S1 / S2=111, the USID is equal to ID1 output; when S0 / S1 / S2=000, the USID is equal to ID2 output; when S0 / S1 / S2=010, the USID is equal to ID3 output; when S0 / S1 / S2=110, the USID is equal to ID4 output. In this way, the present invention not only realizes the USID address expansion of the slave, but also is compatible with the USID programming function.

[0091] Corresponding to the above circuit, the present application also discloses a mobile terminal, which has a master device RFIC, a slave device FEM and the MIPI RFFE interface address expansion circuit described in any one of the above embodiments.

[0092] Furthermore, corresponding to the above solution, the present application also discloses a MIPI RFFE interface address extension method, which includes:

[0093] Obtain a target signal output by a target pin of the MIPI communication interface chip through the ADDR port, where the target signal is any one of a VDD signal, a GND signal, an SCLK signal, or an SDATA signal. The VDD signal is a signal of a VDD pin of the MIPI communication interface chip in the RF front-end system, the GND signal is a signal of a GND pin of the MIPI communication interface chip in the RF front-end system, the SCLK signal is a signal of an SCLK pin of the MIPI communication interface chip in the RF front-end system, and the SDATA signal is a signal of an SDATA pin of the MIPI communication interface chip in the RF front-end system;

[0094] outputting a selection signal that matches the target signal;

[0095] The USID address that matches the selection signal is selected and output.

[0096] The embodiment of this application discloses a MIPI RFFE interface address extension method.

[0097] The above methods disclosed in the above embodiments of this application can be implemented through computer software or hardware circuits. When implemented through computer software, a preset computer program is configured within the chip, and when the computer program is triggered to execute, the above methods are executed. When the above methods are implemented through hardware circuits, the hardware circuit used can be the MIPI RFFE interface address expansion circuit disclosed in any of the above embodiments of this application.

[0098] Corresponding to the above circuit, the present application also discloses a radio frequency system, which includes a master device, a slave device, a bus, and any one of the above-mentioned MIPI RFFE interface address expansion circuits;

[0099] The MIPI RFFE interface address expansion circuit is integrated in the slave device and is connected to the MIPI communication interface chip in the master device through the bus. The USID address provided by the MIPI RFFE interface address expansion circuit serves as the identity of the slave device.

[0100] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0101] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A MIPI RFFE interface address expansion circuit, characterized in that: include: A selection signal configuration circuit, wherein the input end of the selection signal configuration circuit is connected to the ADDR port, and the ADDR port is used to be connected to the target pin of the MIPI communication interface chip, for receiving the target signal output by the target pin of the MIPI communication interface chip, and outputting a selection signal that matches the target signal output by the ADDR port, wherein the target signal is any one of a VDD signal, a GND signal, a SCLK signal or an SDATA signal, wherein the VDD signal is the signal of the VDD pin of the MIPI communication interface chip in the RF front-end system, the GND signal is the signal of the GND pin of the MIPI communication interface chip in the RF front-end system, the SCLK signal is the signal of the SCLK pin of the MIPI communication interface chip in the RF front-end system, and the SDATA signal is the signal of the SDATA pin of the MIPI communication interface chip in the RF front-end system; an address selection circuit is used to select and output a USID address that matches the selection signal.

2. The MIPI RFFE interface address expansion circuit according to claim 1, characterized in that: include: The selection signal configuration circuit includes: N latches, where N is a positive integer greater than 1; A logic unit, wherein the signal input end of any latch is connected to the ADDR port and the output end of the latch through the logic unit corresponding to the latch, and the configuration of the logic unit satisfies the condition that when the signal input ends of different latches obtain the target signal, the output signals of different latches are different; The clock signal input terminal of the latch is used to obtain the SCLK clock signal; The RN ports of N-1 latches of the N latches and the SN port of the remaining latch are used to obtain the SSC start signal sent by the master device, and the start signal is used to reset the N latches; A decoder, wherein the input end of the decoder is connected to the output end of the N latches, and is used to output a decoding signal adapted to the output signals of the N latches, and the decoding signal serves as the selection signal.

3. The MIPI RFFE interface address expansion circuit according to claim 1, characterized in that: The address selection circuit includes: M registers, where M is a positive integer greater than 1; The register stores a preset USID address, and different registers store different USID addresses; The selector is used to select and output the USID address of the register that matches the selection signal.

4. The MIPI RFFE interface address expansion circuit according to claim 2, characterized in that: The value of N is 3.

5. The MIPI RFFE interface address expansion circuit according to claim 4, characterized in that: The logic unit includes: a first logic OR gate, the first logic OR gate is arranged between the ADDR port, the output end of the first latch and the signal input end of the first latch, the first input end of the first logic OR gate is connected to the ADDR port, the second input end of the first logic OR gate is connected to the output end of the first latch, and the output end of the first logic OR gate is connected to the signal input end of the first latch; a second logic OR gate, the second logic OR gate being arranged between the ADDR port, the output terminal of the second latch, and the signal input terminal of the second latch, the first input terminal of the second logic OR gate being connected to the ADDR port, the second input terminal of the second logic OR gate being connected to the output terminal of the second latch, and the output terminal of the second logic OR gate being connected to the signal input terminal of the second latch; An inverter, wherein the second latch obtains an SCLK clock signal through the inverter; A logic AND gate is arranged between the ADDR port, the output end of the third latch and the signal input end of the third latch, the first input end of the logic AND gate is connected to the ADDR port, the second input end of the logic AND gate is connected to the output end of the third latch, and the output end of the logic AND gate is connected to the signal input end of the third latch.

6. The MIPI RFFE interface address expansion circuit according to claim 2, characterized in that: Also includes: A delay circuit is provided between the ADDR port and the N latches.

7. The MIPI RFFE interface address expansion circuit according to claim 3, characterized in that: The value of M is 4.

8. A mobile terminal, characterized in that: The MIPI RFFE interface address extension circuit described in any one of claims 1-7 is applied.

9. A MIPI RFFE interface address extension method, characterized in that: include: Obtain a target signal output by a target pin of the MIPI communication interface chip through the ADDR port, where the target signal is any one of a VDD signal, a GND signal, an SCLK signal, or an SDATA signal. The VDD signal is a signal of a VDD pin of the MIPI communication interface chip in the RF front-end system, the GND signal is a signal of a GND pin of the MIPI communication interface chip in the RF front-end system, the SCLK signal is a signal of an SCLK pin of the MIPI communication interface chip in the RF front-end system, and the SDATA signal is a signal of an SDATA pin of the MIPI communication interface chip in the RF front-end system; outputting a selection signal that matches the target signal; The USID address that matches the selection signal is selected and output.

10. The MIPI RFFE interface address extension method according to claim 9, characterized in that: The MIPI RFFE interface address extension method is implemented by the MIPI RFFE interface address extension circuit described in any one of claims 1-7.

11. A radio frequency system, characterized in that: include: A master device, a slave device, a bus, and a MIPI RFFE interface address extension circuit according to any one of claims 1 to 7; The MIPIRFFE interface address expansion circuit is integrated in the slave device and connected to the MIPI communication interface chip in the master device through the bus. The USID address provided by the MIPIRFFE interface address expansion circuit serves as the identity of the slave device.

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