Memory and Method of Operating the Memory

Abstract

An embodiment of the present disclosure discloses a memory and an operation method thereof. The memory includes: a memory cell array; a write driver coupled to the memory cell array and configured to send data signals to be written to the memory cell array according to received write operation commands; a first column decoder coupled to a first memory cell region of the memory cell array through a first column selection line and configured to perform a write operation on the memory cell array; the first column selection line includes a virtual line and a mounting line; the virtual line is coupled to the first column decoder and the mounting line and is used to transmit a first column selection signal to the mounting line; the mounting line is coupled to the first memory cell region and is used to transmit the first column selection signal to the first memory cell region; the first column selection signal is used to select a memory cell column in the first memory cell region for performing a write operation; wherein, the transmission direction of the data signals to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a memory and an operation method thereof. Background Art

[0002] A dynamic random access memory (DRAM) includes a storage cell array arranged in an array, and each storage cell includes a transistor and a capacitor. Dynamic random access memories are widely used in electronic devices such as mobile devices and computers. With the development of manufacturing process technology, the capacity of dynamic random access memories has gradually increased. However, during the operation of the memory, there is a problem of write errors. Therefore, how to improve the write accuracy of the memory has become an urgent problem to be solved currently. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, there is provided a memory, including:

[0004] A storage cell array;

[0005] A write driver, coupled to the storage cell array, configured to send a data signal to be written to the storage cell array according to a received write operation command;

[0006] A first column decoder, coupled to a first storage cell region of the storage cell array through a first column selection line, configured to perform a write operation on the first storage cell region;

[0007] The first column selection line includes a virtual line and a mounting line;

[0008] The virtual line, coupled to the first column decoder and the mounting line, is configured to transmit a first column selection signal to the mounting line;

[0009] The mounting line, coupled to the first storage cell region, is configured to transmit the first column selection signal to the first storage cell region; the first column selection signal is used to select a storage cell column in the first storage cell region that performs the write operation;

[0010] Wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line.

[0011] In some embodiments, the storage cell array includes a second storage cell region and the first storage cell region arranged side by side in a first direction; wherein, the first direction is the direction in which the write driver, the storage cell array, and the first column decoder are arranged in sequence;

[0012] The virtual line is located in the first memory cell region and is configured to transmit a first column selection signal to the mounting line in a second direction opposite to the first direction.

[0013] The mounting line is coupled to the first memory cell region and is configured to transmit the first column selection signal to the first memory cell region in the first direction; wherein, the first column selection signal is used to select the memory cell columns in the first memory cell region that perform the write operation.

[0014] In some embodiments, the memory further includes: a second column decoder, which is located on opposite sides of the memory cell array from the first column decoder and on the same side of the memory cell array as the write driver;

[0015] The second column decoder is coupled to the second memory cell region and is configured to perform a write operation on the second memory cell region.

[0016] In some embodiments, the memory cell array includes a second memory cell region and the first memory cell region arranged side by side in a first direction; wherein, the first direction is the direction in which the write driver, the first column decoder, and the memory cell array are arranged in sequence.

[0017] The virtual line is located in the second memory cell region and is configured to transmit a first column selection signal to the mounting line in the first direction.

[0018] The mounting line is coupled to the first memory cell region and is configured to transmit the first column selection signal to the first memory cell region in the first direction; wherein, the first column selection signal is used to select the memory cell columns in the first memory cell region that perform the write operation.

[0019] In some embodiments, the memory further includes: a second column decoder, which is located on the same side of the memory cell array as the first column decoder and the write driver;

[0020] The second column decoder is coupled to the second memory cell region and is configured to perform a write operation on the second memory cell region.

[0021] In some embodiments, the memory further includes: a second column selection line, which is coupled to the second column decoder and the second memory cell region and is configured to transmit a second column selection signal to the second memory cell region; wherein, the second column selection signal is used to select the memory cell columns in the second memory cell region that perform the write operation.

[0022] In some embodiments, the memory further includes:

[0023] A command decoder, coupled to the first column decoder, is configured to control the first column decoder to perform a write operation according to a received write operation command.

[0024] In some embodiments, the memory includes a dynamic random access memory.

[0025] According to a second aspect of the embodiments of the present disclosure, there is provided a method for operating a memory, the memory including a memory cell array, a write driver, a first column decoder, and a first column selection line, the first column selection line including a virtual line and a mounting line, the first column decoder being coupled to the memory cell array through the virtual line and the mounting line;

[0026] The operation method includes:

[0027] The write driver sends a data signal to be written to a first memory cell area of the memory cell array according to a received write operation command;

[0028] The first column decoder transmits a first column selection signal to the mounting line through the virtual line;

[0029] The mounting line transmits the first column selection signal to the first memory cell area; the first column selection signal is used to select a memory cell column in the first memory cell area that performs the write operation;

[0030] Wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line.

[0031] In some embodiments, the memory cell array includes a second memory cell area and the first memory cell area arranged side by side in a first direction, the first direction being the direction in which the write driver, the memory cell array, and the first column decoder are arranged in sequence; the method includes:

[0032] The first column decoder transmits a first column selection signal to the mounting line in a second direction opposite to the first direction through the virtual line; wherein, the virtual line is located in the first memory cell area;

[0033] The mounting line transmits the first column selection signal to the first memory cell area in the first direction; wherein, the mounting line is coupled to the first memory cell area, and the first column selection signal is used to select a memory cell column in the first memory cell area that performs the write operation.

[0034] In some embodiments, the memory further includes: a second column decoder, located on opposite sides of the memory cell array from the first column decoder, and on the same side of the memory cell array as the write driver;

[0035] The method further includes:

[0036] The second column decoder performs a write operation on the second memory cell region.

[0037] In some embodiments, the memory cell array includes a second memory cell region and the first memory cell region arranged side by side in a first direction; wherein, the first direction is the direction in which the write driver, the first column decoder, and the memory cell array are sequentially arranged; the method includes:

[0038] The first column decoder transmits a first column selection signal to a mounting line in the first direction through the virtual line; wherein, the virtual line is located in the second memory cell region;

[0039] The mounting line transmits the first column selection signal to the first memory cell region in the first direction; wherein, the mounting line is coupled to the first memory cell region, and the first column selection signal is used to select a memory cell column in the first memory cell region that performs the write operation.

[0040] In some embodiments, the memory further includes: a second column decoder, located on the same side of the memory cell array as the first column decoder and the write driver;

[0041] The method further includes:

[0042] The second column decoder performs a write operation on the second memory cell region.

[0043] In some embodiments, the memory further includes: a second column selection line;

[0044] The second column decoder performing a write operation on the second memory cell region includes:

[0045] Transmitting the second column selection signal to the second memory cell region through the second column selection line; wherein, the second column selection signal is used to select a memory cell column in the second memory cell region that performs the write operation.

[0046] In some embodiments, the memory further includes a command decoder; the operation method further includes:

[0047] The command decoder controls the first column decoder to perform the write operation according to the received write operation command.

[0048] In an embodiment of the present disclosure, a write driver is coupled to a memory cell array and transmits a data signal to be written to the memory cell array according to a received write operation command; a first column decoder is coupled to the memory cell array through a virtual line and a mounting line and transmits a first column selection signal to select a column of memory cells in the memory cell array that perform a write operation. When writing data to the memory cells through the write driver and the first column decoder, since the transmission direction of the data signal to be written is the same as the transmission direction of the first column selection signal transmitted by the mounting line, the consistency of the write operation can be improved, the time margin of the write operation can be increased, thereby avoiding the problem of write errors during high-speed write operations, and further improving the memory performance. Description of the Drawings

[0049] Figure 1 FIG. is a schematic diagram of a memory structure shown according to an exemplary embodiment;

[0050] Figure 2 According to Figure 1 FIG. is a schematic diagram of a write operation of a memory shown;

[0051] Figure 3 According to Figure 1 FIG. is another schematic diagram of a write operation of a memory shown;

[0052] Figure 4 FIG. is a schematic diagram of a memory structure shown according to an embodiment of the present disclosure;

[0053] Figure 5 According to Figure 4 FIG. is a partially enlarged schematic diagram of a memory structure shown;

[0054] Figure 6 FIG. is another schematic diagram of a read operation of a memory shown according to an embodiment of the present disclosure;

[0055] Figure 7 FIG. is a schematic diagram of a write operation timing of a memory shown according to an embodiment of the present disclosure;

[0056] Figure 8 FIG. is another schematic diagram of a write operation timing of a memory shown according to an embodiment of the present disclosure;

[0057] Figure 9 FIG. is a schematic diagram of a method flow for operating a memory shown according to an embodiment of the present disclosure. Detailed Embodiments

[0058] The technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0059] In the embodiments of the present disclosure, terms such as "first" and "second" are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0060] In the embodiments of the present disclosure, the term "A contacts B" includes the case where A directly contacts B, or the case where other components are interposed between A and B and A indirectly contacts B.

[0061] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of a structure below or above, or may have a scope smaller than the scope of the structure below or above. Additionally, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top surface and the bottom surface of the continuous structure, or the layer may be between any horizontal planes at the top surface and the bottom surface of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. Moreover, the layer may include a plurality of sub-layers.

[0062] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, such that "on..." not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0063] The memory includes a storage array, a row address decoding and driving circuit, and a column address decoding and driving circuit. As the memory capacity continuously increases, the area of the storage array becomes larger and larger, and a single column address decoding and driving circuit cannot drive the increasingly long column address lines. Therefore, a column address decoding circuit driving method with bilateral driving can be adopted to drive the storage array.

[0064] Exemplarily, Figure 1 is a schematic diagram of a memory structure shown according to an exemplary embodiment. As Figure 1 shown, the memory 10 includes a storage cell array 11, a first column decoder 12, a second column decoder 13, a row decoder 14, a write driver 15, and a sense amplifier 16 coupled to the storage cell array 11; wherein, the sense amplifier 16, the write driver 15, the first column decoder 12, the storage cell array 11, and the second column decoder 13 are arranged in sequence along the positive X-axis direction, and the storage cell array 11 and the row decoder 14 are arranged in sequence along the positive Y-axis direction. Exemplarily, according to Figure 1 the dashed line shown divides the left region and the right region of the storage cell array 11, wherein, the first column decoder 12 can send a column selection signal to the left region of the storage cell array 11, and the second column decoder 13 can send to the right region of the storage cell array 11. Refer to Figure 2 , Figure 2For Figure 1 Figure 150 shows a schematic diagram of a write operation for a memory structure. The write driver 15 transmits the data signal to be written along the positive X-axis direction to the memory cell A in the right region of the memory cell array 11 according to the received write operation command. As Figure 2 shown, this memory cell A is close to the central dashed line of the memory cell array 11. The second column decoder 13 transmits the column selection signal to the memory cell array 11 along the negative X-axis direction to select the memory cell column in the memory cell array 11 that performs the write operation.

[0065] As Figure 2 shown, Figure 2 the signal lines with arrows in Figure 155 show the process that the write driver 15 transmits the data signal to be written to the memory cell A along the positive X-axis direction, and the second column decoder 13 transmits the column selection signal to the memory cell A along the negative X-axis direction. When performing a write operation on the memory cell A in the right region of the memory cell array 11, as Figure 2 shown, since the second column decoder 13 and the write driver 15 transmit the column selection signal and the data signal to be written to the memory cell array 11 in two different directions (opposite directions) respectively, thus, the column selection signal and the data signal to be written of the memory cell A are driven and transmitted in opposite directions respectively, resulting in poor timing performance for performing a write operation on the memory cells in the right region of the memory cell array 11.

[0066] Referring to Figure 3 , Figure 3 For Figure 1 Figure 161 shows another schematic diagram of a write operation for a memory structure. As Figure 3 shown, the write driver 15 transmits the data signal to be written along the positive X-axis direction to the memory cell B in the right region of the memory cell array 11 according to the received write operation command. As Figure 3 shown, this memory cell B is far from the central dashed line of the memory cell array 11. The second column decoder 13 transmits the column selection signal to the memory cell array 11 along the negative X-axis direction to select the memory cell column in the memory cell array 11 that performs the write operation.

[0067] As Figure 3 shown, Figure 3 the signal lines with arrows in Figure 167 show the process that the write driver 15 transmits the data signal to be written to the memory cell B along the positive X-axis direction, and the second column decoder 13 transmits the column selection signal to the memory cell B along the negative X-axis direction. When performing a write operation on the memory cell B in the right region of the memory cell array 11, as Figure 3As shown, since the second column decoder 13 and the write driver 15 transmit the column selection signal and the data signal to be written to the memory cell array 11 in two different directions (opposite directions) respectively, thus, the column selection signal and the data signal to be written to the memory cell B are driven and transmitted in opposite directions respectively, resulting in poor timing performance for performing write operations on the memory cells in the right region of the memory cell array 11.

[0068] Reference Figure 2 and Figure 3 , when performing a write operation on the right region of the memory cell array 11, for the memory cells A and B at different distances from the second column decoder 13 and the write driver 15, there are problems that the column selection signal and the data signal to be written are driven and transmitted in opposite directions respectively, resulting in poor timing performance for performing write operations on the memory cells in the right region of the memory cell array 11. Thus, the time margin of the write operation will become smaller, and write errors are likely to occur when performing high-speed write operations.

[0069] In view of this, an embodiment of the present disclosure provides another memory.

[0070] Reference Figure 4 , Figure 4 is a schematic diagram of a memory structure shown according to an embodiment of the present disclosure. As Figure 4 shown, the memory 100 includes:

[0071] A memory cell array 101;

[0072] A write driver 102, coupled to the memory cell array 101, configured to send the data signal to be written to the memory cell array 101 according to the received write operation command;

[0073] A first column decoder 103, coupled to the first memory cell area 101a of the memory cell array 101 through a first column selection line 104, configured to perform a write operation on the first memory cell area 101a;

[0074] The first column selection line 104 includes a virtual line 141 and a mounting line 142;

[0075] The virtual line 141, coupled to the first column decoder 103 and the mounting line 142, is used to transmit a first column selection signal to the mounting line 142;

[0076] The mounting line 142, coupled to the first memory cell area 101a, is used to transmit a first column selection signal to the first memory cell area 101a; the first column selection signal is used to select the memory cell column in the first memory cell area 101a that performs the write operation;

[0077] Among them, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal transmitted by the mounting line 142.

[0078] It should be noted that the memory 100 includes a storage cell array 101, a write driver 102, a first column decoder 103, and a second column decoder 105. In this embodiment, Figure 4 The write driver 102, the second column decoder 105, the storage cell array 101, and the first column decoder 103 shown are arranged in sequence in the first direction. Taking the right region of the storage cell array 101 as the first storage cell region 101a as an example for description. However, the device arrangement manner of the present invention is not limited to this. The setting order of the write driver 102, the second column decoder 105, the storage cell array 101, and the first column decoder 103 can be changed, and this embodiment does not limit this. The second column decoder 105, the write driver 102, the storage cell array 101, and the first column decoder 103 are arranged in sequence along the positive X-axis direction, or arranged in other directions, and the present invention can also be realized.

[0079] Exemplarily, referring to Figure 4 , the write driver 102 and the first column decoder 103 are respectively located on opposite sides of the storage cell array 101. The first column decoder 103 is coupled to the storage cell array 101 through the first column selection line 104. The first column selection line 104 includes a dummy routing 141 and a mounting line 142.

[0080] In practical applications, when a write operation instruction is received, a write operation is performed on the first storage cell region 101a of the storage cell array 101 through the write driver 102 and the first column decoder 103. Exemplarily, the input column address obtained by decoding the write operation instruction is transmitted to the first column decoder 102. The first column decoder 102 can decode the input column address and can generate a first column selection signal based on the decoding result. The first column decoder 102 sends the first column selection signal, so as to select the storage cell column corresponding to the input column address to perform the write operation.

[0081] As Figure 4As shown, the write driver 102 drives the memory cell array 101 in the positive X-axis direction. The virtual line 141 transmits the first column selection signal to the mounting line 142 in the negative X-axis direction in the first memory cell region 101a. The mounting line 142 drives the first memory cell region 101a of the memory cell array 101 in the positive X-axis direction according to the first column selection signal. Specifically, the write driver 102 transmits the data signal to be written in the positive X-axis direction to the first memory cell region 101a, and the virtual line 141 transmits the first column selection signal to the mounting line 142 in the negative X-axis direction in the first memory cell region 101a. The write driver 102 continues to transmit the data signal to be written in the positive X-axis direction in the first memory cell region 101a, and the mounting line 142 transmits the first column selection signal in the positive X-axis direction in the first memory cell region 101a. Thus, as Figure 4 shown, in the first memory cell region 101a, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, both in the positive X-axis direction.

[0082] Figure 5 is Figure 4 a partial schematic diagram of, refer to Figure 5 , the first column selection line 104 includes the virtual line 141 and the mounting line 142. Among them, the virtual line 141 is located in the right region of the memory cell array 101 and is not coupled to the memory cells, and the mounting line 142 is located in the right region of the memory cell array 101 and is coupled to each memory cell in the right region of the memory cell array 101. In one example, the first column selection line 104 is divided into two equal-length selection lines, and the length of the virtual line 141 is equal to the length of the mounting line 142. In another example, the first column selection line 104 is divided into the virtual line 141 and the mounting line 142 according to the number of memory cells. Among them, the virtual line 141 passes through M1 memory cells, and the mounting line 142 is coupled to N1 memory cells, and M1 is equal to N1. In yet another example, the first column selection line 104 is divided into the virtual line 141 and the mounting line 142 according to the transmission speed. Among them, the transmission speed of the first column selection signal on the virtual line 141 is M2, and the transmission speed of the first column selection signal on the mounting line 142 is N2. For example, when the transmission time of the first column selection signal passing through the virtual line 141 and the mounting line 142 remains unchanged, when the transmission speed M2 is greater than the transmission speed N2, the length of the virtual line 141 can be set to be greater than the length of the mounting line 142. When the transmission speed M2 is less than the transmission speed N2, the length of the virtual line 141 can be set to be less than the length of the mounting line 142. It should be noted that this is only an example of the division of the virtual line 141 and the mounting line 142, and the present disclosure is not limited to the above division method.

[0083] When performing a write operation on the memory cell array 101 through the write driver 102 and the first column decoder 103 respectively located on opposite sides of the memory cell array 101, since the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, both being along the positive X-axis direction, as Figure 4 shown in the writing process, in the first memory cell area 101a, the transmission directions of the data signal to be written and the first column selection signal are both along the positive X-axis direction, which can improve the consistency of the write operation.

[0084] Compared with the problem of poor timing performance of the write operation caused by the opposite transmission directions of the data signal to be written and the column selection signal, in the memory provided by the embodiments of the present disclosure, when writing data to the memory cells in the first memory cell area 101a through the write driver 102 and the first column decoder 103, since the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal transmitted by the mounting line 142, and the transmission timing can also be regulated through the virtual line, therefore, the consistency of the write operation can be improved, the time margin of the write operation can be increased, the problem of write errors during high-speed write operations can be avoided, and thus the memory performance can be improved.

[0085] In some embodiments, referring to Figure 4 , the memory cell array 101 includes a second memory cell area 101b and a first memory cell area 101a arranged side by side along a first direction; wherein, the first direction is the direction in which the write driver 102, the memory cell array 101, and the first column decoder 103 are arranged in sequence;

[0086] The virtual line 141 is located in the first memory cell area 101a and is used to transmit the first column selection signal to the mounting line 142 in a second direction opposite to the first direction;

[0087] The mounting line 142 is coupled to the first memory cell area 101a and is used to transmit the first column selection signal to the first memory cell area 101a in the first direction; wherein, the first column selection signal is used to select the memory cell column in the first memory cell area 101a where the write operation is performed.

[0088] As Figure 4 shown, the memory cell array 101 is divided into a first memory cell area 101a and a second memory cell area 101b that are symmetric about a central dotted line (as Figure 4 shown). The first memory cell area 101a is the right region of the memory cell array 101, and the second memory cell area 101b is the left region of the memory cell array 101. It should be noted that this is only an example of the division of the memory cell array 101, and the present disclosure is not limited to the above division method.

[0089] Exemplarily, the first column selection signal may be generated by the first column decoder 103. In one example, referring to Figure 4 , the first column decoder 103 may decode the input column address and may generate the first column selection signal based on the decoding result. The first column decoder 103 may transmit the first column selection signal in the first memory cell region 101a through the first column selection line 104, thereby selecting the memory cell column corresponding to the input column address. The first column decoder 103 may drive, select, or activate the virtual line 141 in the negative X-axis direction and drive, select, or activate the mounting line 142 in the positive X-axis direction.

[0090] Specifically, the write driver 102, the memory cell array 101, and the first column decoder 103 are arranged in sequence in the positive X-axis direction. The virtual line 141 is located in the first memory cell region 101a but is not coupled to the memory cells of the first memory cell region 101a, and the mounting line 142 is located in the first memory cell region 101a and is coupled to the memory cells of the first memory cell region 101a.

[0091] The write driver 102 transmits the data signal to be written in the first memory cell region 101a in the positive X-axis direction, and the virtual line 141 transmits the first column selection signal in the first memory cell region 101a in the negative X-axis direction. The data signal to be written continues to be transmitted in the first memory cell region 101a in the positive X-axis direction, and the first column selection signal is transmitted in the first memory cell region 101a in the positive X-axis direction through the mounting line 142. Thus, in the first memory cell region 101a, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, both being in the positive X-axis direction. Therefore, the consistency of the write operation in the first memory cell region 101a can be improved, thereby avoiding write errors during high-speed write operations.

[0092] In some embodiments, referring to Figure 4 , the memory further includes: a second column decoder 105, located on opposite sides of the memory cell array 101 from the first column decoder 103 and on the same side of the memory cell array 101 as the write driver 102;

[0093] The second column decoder 105 is coupled to the second memory cell region 101b and is configured to perform a write operation on the second memory cell region 101b.

[0094] As Figure 4 shown, the write driver 102, the second column decoder 105, the memory cell array 101, and the first column decoder 103 are arranged in sequence in the positive X-axis direction. In addition, the arrangement order of the write driver 102, the second column decoder 105, the memory cell array 101, and the first column decoder 103 may be variable, and this embodiment does not limit this.

[0095] Specifically, the second column selection signal can be generated by the second column decoder 105. In one example, referring to Figure 4 , the second column decoder 105 can decode the input column address and generate the second column selection signal based on the decoding result. The second column decoder 105 can transmit the second column selection signal in the first memory cell region 101a to select the memory cell column corresponding to the input column address. The write driver 102 drives the second memory cell region 101b in the positive X-axis direction, and the second column decoder 105 transmits the second column selection signal in the positive X-axis direction in the second memory cell region 101b. In this way, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the second column selection signal sent by the second column decoder 105, both in the positive X-axis direction. Therefore, the consistency of the write operation in the second memory cell region 101b can be improved, thereby avoiding write errors during high-speed write operations.

[0096] In some embodiments, referring to Figure 6 , the memory cell array 101 includes a second memory cell region 101b and a first memory cell region 101a arranged side by side in a first direction; wherein, the first direction is the direction in which the write driver 102, the first column decoder 103, and the memory cell array 101 are arranged in sequence;

[0097] The virtual line 141 is located in the second memory cell region 101b and is used to transmit the first column selection signal to the mounting line 142 in the first direction;

[0098] The mounting line 142 is coupled to the first memory cell region 101a and is used to transmit the first column selection signal to the first memory cell region 101a in the first direction; wherein, the first column selection signal is used to select the memory cell column that performs the write operation in the first memory cell region 101a.

[0099] It should be noted that this embodiment takes the write driver 102, the second column decoder 105, the first column decoder 103, and the memory cell array 101 arranged in sequence in the positive X-axis direction as shown in Figure 6 as an example for illustration. In addition, the arrangement order of the write driver 102, the second column decoder 105, the first column decoder 103, and the memory cell array 101 can be changed, and this embodiment does not limit this. As shown in Figure 6 , the memory cell array 101 is divided along the central dotted line (such as Figure 6Symmetric first storage cell region 101a and second storage cell region 101b (as shown), where the first storage cell region 101a is the region on the right side of the storage cell array 101, and the second storage cell region 101b is the region on the left side of the storage cell array 101. It should be noted that this is only an example of the division of the storage cell array 101, and the present disclosure is not limited to the above division method. For example, it can also be divided according to the signal transmission speeds on the virtual lines and load lines.

[0100] In one example, as Figure 6 shown, the first column decoder 103 drives the storage cell array through the first column selection lines 104. The first column selection lines 104 include virtual lines 141 and mounting lines 142. Among them, the virtual lines 141 are located in the second storage cell region 101b and are not coupled to the storage cells, and the mounting lines 142 are located in the first storage cell region 101a and are coupled to the respective storage cells in the first storage cell region 101a. The second column decoder 105 drives the storage cell array through the second column selection lines 106. The second column selection lines 106 include second virtual lines and second mounting lines. Among them, the second mounting lines are located in the second storage cell region 101b and are coupled to the respective storage cells in the second storage cell region 101b, and the second virtual lines are located in the first storage cell region 101a and are not coupled to the storage cells. In another example, the first column decoder 103 drives the storage cell array through the first column selection lines 104, where the mounting lines 142 are located in the second storage cell region 101b and are coupled to the respective storage cells in the second storage cell region 101b, and the virtual lines 141 are located in the first storage cell region 101a and are not coupled to the storage cells. The second column decoder 105 drives the storage cell array through the second column selection lines 106. The second column selection lines 106 include second virtual lines and second mounting lines. Among them, the second virtual lines are located in the second storage cell region 101b and are not coupled to the storage cells, and the second mounting lines are located in the first storage cell region 101a and are coupled to the respective storage cells in the first storage cell region 101a.

[0101] In practical applications, when a write operation instruction is received, the write driver 102 and the first column decoder 103 perform a write operation on the storage cell array 101. As Figure 6As shown, the write driver 102 drives the memory cell array 101 in the positive X-axis direction, and the virtual line 141 and the mounting line 142 drive the memory cell array 101 in the positive X-axis direction. Specifically, the write driver 102 transmits the data signal to be written in the positive X-axis direction, and the virtual line 141 transmits the first column selection signal in the positive X-axis direction. The write driver 102 continues to transmit the data signal to be written in the first memory cell area 101a in the positive X-axis direction, and the mounting line 142 transmits the first column selection signal in the first memory cell area 101a in the positive X-axis direction. In this way, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, both in the positive X-axis direction. Therefore, when the write driver 102 and the first column decoder 103 are located on the same side of the memory cell array 101, during the write operation through the write driver 102 and the first column decoder 103, the transmission directions of the data signal to be written and the first column selection signal are the same, both in the positive X-axis direction. Therefore, the consistency of the write operation can be improved, thereby avoiding write errors during high-speed write operations.

[0102] In some embodiments, referring to Figure 6 , the memory further includes: a second column decoder 105, located on the same side of the memory cell array 101 as the first column decoder 103 and the write driver 102;

[0103] The second column decoder 105 is coupled to the second memory cell area 101b and is configured to perform a write operation on the second memory cell area 101b.

[0104] As Figure 6 shown, the write driver 102, the second column decoder 105, the first column decoder 103, and the memory cell array 101 are arranged in sequence in the positive X-axis direction. In addition, the arrangement order of the write driver 102, the second column decoder 105, the first column decoder 103, and the memory cell array 101 can be changed, and this embodiment does not limit this.

[0105] Specifically, the second column selection signal can be generated by the second column decoder 105. In one example, referring to Figure 6 , the second column decoder 105 can decode the input column address and can generate the second column selection signal based on the decoding result. The second column decoder 105 can transmit the second column selection signal in the first memory cell area 101a to select the memory cell column corresponding to the input column address.

[0106] The write driver 102 drives the second memory cell region 101b in the positive X-axis direction, and the second column decoder 105 transmits a second column selection signal in the positive X-axis direction in the second memory cell region 101b. In this way, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the second column selection signal sent by the second column decoder 105, both being in the positive X-axis direction. Therefore, in the second memory cell region 101b, when performing a write operation through the write driver 102 and the second column decoder 105, the transmission direction of the data signal to be written is the same as that of the second column selection signal, both being in the positive X-axis direction. Therefore, the consistency of the write operation in the second memory cell region 101b can be improved, thereby avoiding write errors during high-speed write operations.

[0107] In some embodiments, the memory further includes: a second column selection line 106, coupled to the second column decoder 105 and the second memory cell region 101b, for transmitting a second column selection signal to the second memory cell region 101b; wherein, the second column selection signal is used to select the memory cell columns in the second memory cell region 101b that perform write operations.

[0108] As Figure 4 or Figure 6 shown, the column selection signal can be generated by the first column decoder 103 and the second column decoder 105. Exemplarily, the second column decoder 105 can decode the input column address and can generate a second column selection signal based on the decoding result. The second column decoder 103 can transmit the second column selection signal in the first direction (such as Figure 4 or Figure 6 shown, the positive X-axis direction) through the second column selection line 106 to select the memory cell columns corresponding to the input column address. The second column decoder 103 can drive, select, or activate the second column selection line 106 in the positive X-axis direction. Each of the second column selection lines 106 can be connected to at least one bit line. It should be noted that the mounting lines 142 in the second column selection line 106 and the first column selection line 104 that couple to the same column of memory cells are on the same horizontal line.

[0109] In an exemplary embodiment, the column selection signal can be generated by a command decoder. For example, the command decoder can generate a first column selection line signal and a second column selection signal in response to a write operation command, and send the first column selection signal to the first column decoder 103 and the second column selection signal to the second column decoder 105.

[0110] It should be noted that referring to Figure 5 and Figure 7 , the write driver 102 drives the memory cell 101A in the positive X-axis direction, and the write driver 102 can send the data signal to be written (such as Figure 7In the second column decoder 105, a second column selection signal (e.g., Figure 7 Ysel_A in the middle) is transmitted to the storage unit 101A along the positive X-axis direction. After the second column decoder 105 sends the second column selection signal, after a time t1, the storage unit 101A almost simultaneously receives the data signal to be written (e.g., Figure 7 Data_A in the middle) and the second column selection signal (e.g., Figure 7 Ysel_A in the middle). The transmission direction of the data signal to be written is the same as that of the second column selection signal, and they arrive at the storage unit 101A almost simultaneously. Therefore, the consistency of the write operation in the left region of the storage unit array 101 can be improved, thereby avoiding write errors during high-speed write operations.

[0111] Reference Figure 5 and Figure 8 , the write driver 102 drives the storage unit 101B along the positive X-axis direction. The write driver 102 can send the data signal to be written (e.g., Figure 8 Data in the middle) to the storage unit 101B through the data input line (GIO). The first column decoder 103 transmits the first column selection signal along the negative X-axis direction through the virtual line 141. When the first column selection signal reaches the boundary between the virtual line 141 and the mounting line 142, it turns back, and then transmits the first column selection signal (e.g., Figure 8 Ysel_B in the middle) to the storage unit 101B along the positive X-axis direction through the mounting line 142. After a time t2, the storage unit 101B almost simultaneously receives the data signal to be written (e.g., Figure 8 Data_B in the middle) and the first column selection signal (e.g., Figure 8 Ysel_B in the middle). The transmission direction of the data signal to be written is the same as that of the first column selection signal, and they arrive at the storage unit 101B almost simultaneously. Therefore, the consistency of the write operation in the right region of the storage unit array 101 can be improved, thereby avoiding write errors during high-speed write operations.

[0112] In some embodiments, the memory further includes:

[0113] A command decoder, coupled to the first column decoder 103, configured to control the first column decoder 103 to perform a write operation according to the received write operation command.

[0114] Exemplarily, a command (CMD) decoder (not shown) can control the first column decoder 103, the second column decoder 105, and the row decoder 108 in response to commands (CMD) and addresses (ADD) received from outside the memory 100.

[0115] In one example, the command decoder can control the first column decoder 103 and the second column decoder 105 in response to a write operation command or a read operation command, and can send the input column address to the first column decoder 103 and the second column decoder 105.

[0116] In an exemplary embodiment, the command decoder can also control the row decoder 108 in response to a write operation command, a read operation command, an activation command, a precharge command, a refresh command, etc., and can send the input row address to the row decoder 108.

[0117] In some embodiments, the memory includes a dynamic random access memory.

[0118] It should be noted that the memory may include a dynamic random access memory. The memory may also include other types of memories. For example, static random access memory (SRAM), NAND flash memory, NOR flash memory, resistive random access memory (RRAM), ferroelectric random access memory (FRAM), phase change random access memory (PRAM), thyristor random access memory (TRAM), and magnetic random access memory (MRAM). The present disclosure does not limit this.

[0119] In some embodiments, the memory further includes: a sense amplifier 107, coupled to the memory cell array 101, and configured to receive the read data information output by the memory cell array 101 based on a read operation.

[0120] Exemplarily, when a read operation instruction is received, a read operation is performed on the memory cell array 101. As Figure 4 or Figure 6 shown, the input column address obtained by decoding the read operation instruction is transmitted to the first column decoder 103 or the second column decoder 105. The first column decoder 103 or the second column decoder 105 can decode the input column address and can generate a second column selection signal based on the decoding result.

[0121] Refer to Figure 4, in one example, the first column decoder 103 may send the second column selection signal in the negative X-axis direction, so as to select the memory cell column corresponding to the input column address to perform a read operation. The target memory cell in the memory cell column outputs the read data in the negative X-axis direction to the sense amplifier 107 according to the second column selection signal. In another example, the second column decoder 105 may send the second column selection signal in the positive X-axis direction, so as to select the memory cell column corresponding to the input column address to perform a read operation. The target memory cell in the memory cell column outputs the read data in the negative X-axis direction to the sense amplifier 107 according to the second column selection signal.

[0122] Reference Figure 6 , the first column decoder 103 or the second column decoder 105 may send the second column selection signal in the positive X-axis direction, so as to select the memory cell column corresponding to the input column address to perform a read operation. The target memory cell in the memory cell column outputs the read data in the negative X-axis direction to the sense amplifier 107 according to the second column selection signal.

[0123] In some embodiments, the memory further includes: a row decoder 108, coupled to the memory cell array 101, the row decoder 108 and the memory cell array 101 are arranged in a third direction, and the third direction is perpendicular to the first direction; wherein,

[0124] The row decoder 108 is configured to send a row selection signal to the memory cell array 101 to select the memory cell row in the memory cell array 101 that performs a write operation or a read operation.

[0125] Exemplarily, reference Figure 4 and Figure 6 , the row decoder 108 may decode the input row address and may generate a row selection signal based on the decoding result. The row decoder 108 may send the row selection signal in the third direction (such as Figure 4 or Figure 6 the negative Y-axis direction in) through the word line, and may select the memory cell row corresponding to the input row address. The target memory cell is determined by selecting the memory cell column corresponding to the input column address and the memory cell row corresponding to the input row address.

[0126] Reference Figure 4 and Figure 6 , the row decoder 108 and the memory cell array 101 are arranged in sequence in the third direction (such as Figure 6 the negative Y-axis direction in). It should be noted that, Figure 4 and Figure 6 provide an internal layout manner of the memory. However, this is only an example, and the row decoder 108 of the present disclosure is not limited to the layout manner as shown in Figure 4 and Figure 6 .

[0127] As shown in Figure 9 shown, Figure 9 FIG. Figure 9 is a schematic flowchart of an operation method of a memory according to an embodiment of the present disclosure. The memory includes a memory cell array, a write driver, a first column decoder, and a first column selection line. The first column selection line includes a dummy line and a landing line. The first column decoder is coupled to the memory cell array through the dummy line and the landing line;

[0128] The operation method includes:

[0129] S10: The write driver sends the data signal to be written to the first memory cell area of the memory cell array according to the received write operation command;

[0130] S20: The first column decoder transmits a first column selection signal to the landing line through the dummy line;

[0131] S30: The landing line transmits the first column selection signal to the first memory cell area; the first column selection signal is used to select the memory cell columns that perform the write operation in the first memory cell area;

[0132] Wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the landing line.

[0133] It should be noted that the memory includes a memory cell array, a write driver, a first column decoder, and a second column decoder. In this embodiment, Figure 4 as shown, the write driver 102, the second column decoder 105, the memory cell array 101, and the first column decoder 103 are arranged in sequence in the first direction, and the right area of the memory cell array 101 is taken as an example of the first memory cell area 101a for illustration. However, the device arrangement manner of the present invention is not limited thereto. The setting order of the write driver 102, the second column decoder 105, the memory cell array 101, and the first column decoder 103 can be changed, and this embodiment does not limit this. The second column decoder 105, the write driver 102, the memory cell array 101, and the first column decoder 103 are arranged in sequence along the positive X-axis direction, or arranged in other directions, and the present invention can also be implemented.

[0134] Exemplarily, referring to Figure 4 , the write driver 102 and the first column decoder 103 are respectively located on opposite sides of the memory cell array 101. The first column decoder 103 is coupled to the memory cell array 101 through the first column selection line 104. The first column selection line 104 includes a dummy routing 141 and a landing line 142.

[0135] Step S10 is executed. When a write operation instruction is received, the write driver 102 can send the data signal to be written to the first memory cell area 101a of the memory cell array 101 through the data input line (GIO). Steps S20 to S30 are executed. The input column address obtained by decoding the write operation instruction is transmitted to the first column decoder. The first column decoder can decode the input column address and can generate a first column selection signal based on the decoding result. The first column decoder can send the first column selection signal along the negative X-axis direction through the virtual line and then send the first column selection signal along the negative X-axis direction through the mounting line, so as to select the memory cell column corresponding to the input column address to perform the write operation.

[0136] Exemplarily, as Figure 4 shown, the write driver 102 drives the memory cell array 101 along the positive X-axis direction. The virtual line 141 transmits the first column selection signal to the mounting line 142 in the first memory cell area 101a along the negative X-axis direction. The mounting line 142 drives the first memory cell area 101a of the memory cell array 101 along the positive X-axis direction according to the first column selection signal. Specifically, the write driver 102 transmits the data signal to be written to the first memory cell area 101a along the positive X-axis direction. The virtual line 141 transmits the first column selection signal to the mounting line 142 in the first memory cell area 101a along the negative X-axis direction. The write driver 102 continues to transmit the data signal to be written to the first memory cell area 101a along the positive X-axis direction. The mounting line 142 transmits the first column selection signal to the first memory cell area 101a along the positive X-axis direction. Thus, as Figure 4 shown, in the first memory cell area 101a, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, both along the positive X-axis direction.

[0137] Figure 5 For Figure 4 the partial schematic diagram of, refer to Figure 5, the first column selection line 104 includes a virtual line 141 and a mounting line 142. Among them, the virtual line 141 is located in the right region of the memory cell array 101 and is not coupled to the memory cells, and the mounting line 142 is located in the right region of the memory cell array 101 and is coupled to each memory cell in the right region of the memory cell array 101. In one example, the first column selection line 104 is divided into two equal-length selection lines, and the length of the virtual line 141 is equal to the length of the mounting line 142. In another example, the first column selection line 104 is divided into the virtual line 141 and the mounting line 142 according to the number of memory cells. Among them, the virtual line 141 passes through M1 memory cells, and the mounting line 142 is coupled to N1 memory cells, and M1 is equal to N1. In yet another example, the first column selection line 104 is divided into the virtual line 141 and the mounting line 142 according to the transmission speed. Among them, the transmission speed of the first column selection signal on the virtual line 141 is M2, and the transmission speed of the first column selection signal on the mounting line 142 is N2. For example, when the transmission times of the first column selection signal passing through the virtual line 141 and the mounting line 142 respectively remain unchanged, when the transmission speed M2 is greater than the transmission speed N2, the length of the virtual line 141 can be set to be greater than the length of the mounting line 142. When the transmission speed M2 is less than the transmission speed N2, the length of the virtual line 141 can be set to be less than the length of the mounting line 142. It should be noted that this is only an example of the division of the virtual line 141 and the mounting line 142, and the present disclosure is not limited to the above division method.

[0138] When performing a write operation on the memory cell array 101 through the write driver 102 and the first column decoder 103 respectively located on opposite sides of the memory cell array 101, since the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, both are along the positive X-axis direction, as Figure 4During the writing process shown, in the first memory cell region 101a, the transmission directions of the data signal to be written and the first column selection signal are both along the positive X-axis direction, which can improve the consistency of the write operation. Compared with the problem of poor timing performance of the write operation caused by the opposite transmission directions of the data signal to be written and the column selection signal, in the embodiments of the present disclosure, the write driver sends the data signal to be written to the memory cell array according to the received write operation command; the first column decoder transmits the first column selection signal to the mounting line through the virtual line; the mounting line transmits the first column selection signal to the memory cell array; wherein, the first column selection signal is used to select the memory cell column in the memory cell array that performs the write operation; wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line. Since the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, and the transmission timing can also be regulated through the virtual line, the consistency of the write operation can be improved, the time margin of the write operation can be increased, the problem of write error during high-speed write operation can be avoided, and thus the memory performance can be improved.

[0139] In some embodiments, the memory cell array includes a second memory cell region and a first memory cell region arranged side by side along a first direction, and the first direction is the direction in which the write driver, the memory cell array, and the first column decoder are arranged in sequence; the method includes:

[0140] The first column decoder transmits the first column selection signal to the mounting line through the virtual line in a second direction opposite to the first direction; wherein, the virtual line is located in the first memory cell region;

[0141] The mounting line transmits the first column selection signal to the first memory cell region in the first direction; wherein, the mounting line is coupled to the first memory cell region, and the first column selection signal is used to select the memory cell column in the first memory cell region that performs the write operation.

[0142] As Figure 4 shown, the memory cell array 101 is divided into a first memory cell region 101a and a second memory cell region 101b that are symmetric about the central dotted line (as Figure 4 shown). The first memory cell region 101a is the right region of the memory cell array 101, and the second memory cell region 101b is the left region of the memory cell array 101. It should be noted that this is only an example of the division of the memory cell array 101, and the present disclosure is not limited to the above division method. For example, it can also be divided according to the signal transmission speeds on the virtual line and the load line.

[0143] Exemplarily, the first column selection signal can be generated by the first column decoder 103. In one example, referring to Figure 4, the first column decoder 103 can decode the input column address and generate a first column selection signal based on the decoding result. The first column decoder 103 can transmit the first column selection signal in the first memory cell region 101a through the first column selection line 104, so as to select the memory cell column corresponding to the input column address. The first column decoder 103 can drive, select, or activate the virtual line 141 in the negative X-axis direction and drive, select, or activate the mounting line 142 in the positive X-axis direction.

[0144] Specifically, the write driver 102, the memory cell array 101, and the first column decoder 103 are arranged in sequence in the positive X-axis direction. The virtual line 141 is located in the first memory cell region 101a but is not coupled to the memory cells of the first memory cell region 101a, and the mounting line 142 is located in the first memory cell region 101a and is coupled to the memory cells of the first memory cell region 101a.

[0145] The write driver 102 transmits the data signal to be written in the first memory cell region 101a in the positive X-axis direction, and the virtual line 141 transmits the first column selection signal in the first memory cell region 101a in the negative X-axis direction. The data signal to be written continues to be transmitted in the first memory cell region 101a in the positive X-axis direction, and the first column selection signal is transmitted in the first memory cell region 101a in the positive X-axis direction through the mounting line 142. Thus, in the first memory cell region 101a, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the mounting line 142, both being in the positive X-axis direction. Therefore, the consistency of the write operation in the first memory cell region 101a can be improved, thereby avoiding write errors during high-speed write operations.

[0146] In some embodiments, the memory further includes: a second column decoder, which is located on opposite sides of the memory cell array from the first column decoder and on the same side of the memory cell array as the write driver;

[0147] The method further includes:

[0148] The second column decoder performs a write operation on the second memory cell region.

[0149] As Figure 4 shown, the write driver 102, the second column decoder 105, the memory cell array 101, and the first column decoder 103 are arranged in sequence in the positive X-axis direction. In addition, the arrangement order of the write driver 102, the second column decoder 105, the memory cell array 101, and the first column decoder 103 can be changed, and this embodiment does not limit this.

[0150] Specifically, the second column selection signal can be generated by the second column decoder 105. In one example, referring to Figure 4, the second column decoder 105 can decode the input column address and generate a second column selection signal based on the decoding result. The second column decoder 105 can transmit the second column selection signal in the first memory cell region 101a to select the memory cell column corresponding to the input column address. The write driver 102 drives the second memory cell region 101b in the positive X-axis direction, and the second column decoder 105 transmits the second column selection signal in the positive X-axis direction in the second memory cell region 101b. In this way, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the second column selection signal sent by the second column decoder 105, both being in the positive X-axis direction. Therefore, the consistency of the write operation in the second memory cell region 101b can be improved, thereby avoiding write errors during high-speed write operations.

[0151] In some embodiments, a memory cell array includes a second memory cell region and a first memory cell region arranged side by side in a first direction; wherein, the first direction is the direction in which the write driver, the first column decoder, and the memory cell array are arranged in sequence; the method includes:

[0152] The first column decoder transmits a first column selection signal to the mounting line in the first direction through a virtual line; wherein, the virtual line is located in the second memory cell region;

[0153] The mounting line transmits the first column selection signal to the first memory cell region in the first direction; wherein, the mounting line is coupled to the first memory cell region, and the first column selection signal is used to select the memory cell column in the first memory cell region where the write operation is performed.

[0154] It should be noted that in this embodiment, Figure 6 the illustrated write driver 102, second column decoder 105, first column decoder 103, and memory cell array 101 are arranged in sequence in the positive X-axis direction as an example for illustration. In addition, the arrangement order of the write driver 102, second column decoder 105, first column decoder 103, and memory cell array 101 can be changed, and this embodiment does not limit this. As Figure 6 shown, the memory cell array 101 is divided into a first memory cell region 101a and a second memory cell region 101b that are symmetric about a central dotted line (as Figure 6 shown). The first memory cell region 101a is the right region of the memory cell array 101, and the second memory cell region 101b is the left region of the memory cell array 101. It should be noted that this is only an example of the division of the memory cell array 101, and the present disclosure is not limited to the above division method.

[0155] In one example, as Figure 6As shown, the first column decoder 103 drives the memory cell array through the first column selection lines 104. The first column selection lines 104 include virtual lines 141 and attachment lines 142. Among them, the virtual lines 141 are located in the second memory cell area 101b and are not coupled to the memory cells, and the attachment lines 142 are located in the first memory cell area 101a and are coupled to the respective memory cells in the first memory cell area 101a. The second column decoder 105 drives the memory cell array through the second column selection lines 106. The second column selection lines 106 include second virtual lines and second attachment lines. Among them, the second attachment lines are located in the second memory cell area 101b and are coupled to the respective memory cells in the second memory cell area 101b, and the second virtual lines are located in the first memory cell area 101a and are not coupled to the memory cells. In another example, the first column decoder 103 drives the memory cell array through the first column selection lines 104, where the attachment lines 142 are located in the second memory cell area 101b and are coupled to the respective memory cells in the second memory cell area 101b, and the virtual lines 141 are located in the first memory cell area 101a and are not coupled to the memory cells. The second column decoder 105 drives the memory cell array through the second column selection lines 106. The second column selection lines 106 include second virtual lines and second attachment lines. Among them, the second virtual lines are located in the second memory cell area 101b and are not coupled to the memory cells, and the second attachment lines are located in the first memory cell area 101a and are coupled to the respective memory cells in the first memory cell area 101a.

[0156] In practical applications, when a write operation instruction is received, the write driver 102 and the first column decoder 103 perform a write operation on the memory cell array 101. As Figure 6 shown, the write driver 102 drives the memory cell array 101 along the positive X-axis direction, and the virtual lines 141 and the attachment lines 142 drive the memory cell array 101 along the positive X-axis direction. Specifically, the write driver 102 transmits the data signal to be written along the positive X-axis direction, and the virtual lines 141 transmit the first column selection signal along the positive X-axis direction. The write driver 102 continues to transmit the data signal to be written in the first memory cell area 101a along the positive X-axis direction, and the attachment lines 142 transmit the first column selection signal in the first memory cell area 101a along the positive X-axis direction. In this way, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the first column selection signal sent by the attachment lines 142, both along the positive X-axis direction. Therefore, when the write driver 102 and the first column decoder 103 are on the same side of the memory cell array 101, through the write driver 102 and the first column decoder 103 to perform the write operation, the transmission direction of the data signal to be written and the first column selection signal is the same, both along the positive X-axis direction. Therefore, the consistency of the write operation can be improved, thereby avoiding write errors during high-speed write operations.

[0157] In some embodiments, the memory further includes: a second column decoder, located on the same side of the memory cell array as the first column decoder and the write driver;

[0158] The method further includes:

[0159] The second column decoder performs a write operation on the second memory cell region.

[0160] As Figure 6 shown, the write driver 102, the second column decoder 105, the first column decoder 103, and the memory cell array 101 are arranged in sequence in the positive X-axis direction. In addition, the arrangement order of the write driver 102, the second column decoder 105, the first column decoder 103, and the memory cell array 101 can be changed, and this embodiment does not limit this.

[0161] Specifically, the second column selection signal can be generated by the second column decoder 105. In one example, referring to Figure 6 , the second column decoder 105 can decode the input column address and can generate a second column selection signal based on the decoding result. The second column decoder 105 can transmit the second column selection signal in the first memory cell region 101a to select the memory cell column corresponding to the input column address.

[0162] The write driver 102 drives the second memory cell region 101b in the positive X-axis direction, and the second column decoder 105 transmits the second column selection signal in the second memory cell region 101b in the positive X-axis direction. In this way, the transmission direction of the data signal to be written sent by the write driver 102 is the same as the transmission direction of the second column selection signal sent by the second column decoder 105, both in the positive X-axis direction. Therefore, in the second memory cell region 101b, when performing a write operation through the write driver 102 and the second column decoder 105, the transmission direction of the data signal to be written is the same as the transmission direction of the second column selection signal, both in the positive X-axis direction. Therefore, the consistency of the write operation in the second memory cell region 101b can be improved, thereby avoiding write errors during high-speed write operations.

[0163] In some embodiments, the memory further includes: a second column selection line;

[0164] The second column decoder performs a write operation on the second memory cell region, including:

[0165] Transmitting a second column selection signal to the second memory cell region through the second column selection line; wherein, the second column selection signal is used to select the memory cell column in the second memory cell region where the write operation is performed.

[0166] As Figure 4 or Figure 6As shown, the column selection signals can be generated by the first column decoder 103 and the second column decoder 105. Exemplarily, the second column decoder 105 can decode the input column address and generate a second column selection signal based on the decoding result. The second column decoder 103 can send the second column selection signal in the first direction (such as Figure 4 or Figure 6 the positive X-axis direction as shown) through the second column selection line 106 to select the column of memory cells corresponding to the input column address. The second column decoder 103 can drive, select, or activate the second column selection line 106 in the positive X-axis direction. Each of the second column selection lines 106 can be connected to at least one bit line. It should be noted that the mounting line 142 in the second column selection line 106 and the first column selection line 104 that couple the same column of memory cells is the same horizontal line.

[0167] In an exemplary embodiment, the column selection signals can be generated by a command decoder. For example, the command decoder can generate a first column selection line signal and a second column selection signal in response to a write operation command, send the first column selection signal to the first column decoder 103, and send the second column selection signal to the second column decoder 105.

[0168] It should be noted that referring to Figure 5 and Figure 7 , the write driver 102 drives the memory cell 101A in the positive X-axis direction. The write driver 102 can send the data signal to be written (such as Figure 7 Data in Figure 7 ) to the memory cell 101A through the data input line (GIO). The second column decoder 105 transmits the second column selection signal to the memory cell 101A in the positive X-axis direction (such as Figure 7 Ysel_A in Figure 7 ). After the second column decoder 103 sends the second column selection signal, after a time t1, the memory cell 101A almost simultaneously receives the data signal to be written (such as Figure 7 Data_A in Figure 7 ) and the second column selection signal (such as Figure 7 Ysel_A in Figure 7 ). The data signal to be written and the second column selection signal have the same transmission direction and arrive at the memory cell 101A almost simultaneously. Therefore, the consistency of the write operation in the left region of the memory cell array 101 can be improved, thereby avoiding write errors during high-speed write operations.

[0169] Referring to Figure 5 and Figure 8 , the write driver 102 drives the memory cell 101B in the positive X-axis direction. The write driver 102 can send the data signal to be written (such as Figure 8The first column decoder 103 transmits the first column selection signal along the negative X-axis direction through the virtual line 141. When the first column selection signal reaches the boundary between the virtual line 141 and the mounting line 142, it turns back, and then transmits the first column selection signal to the storage unit 101B along the positive X-axis direction through the mounting line 142 (such as Figure 8 Ysel_B in the figure). After a time t2, the storage unit 101B almost simultaneously receives the data signal to be written (such as Figure 8 Data_B in the figure) and the first column selection signal (such as Figure 8 Ysel_B in the figure). The data signal to be written has the same transmission direction as the first column selection signal and arrives at the storage unit 101B almost simultaneously. Therefore, the consistency of the write operation in the right region of the storage cell array 101 can be improved, thereby avoiding write errors during high-speed write operations.

[0170] In some embodiments, the memory further includes a command decoder; the operation method further includes:

[0171] The command decoder controls the first column decoder to perform a write operation according to the received write operation command.

[0172] Exemplarily, the command (CMD) decoder can control the first column decoder 103, the second column decoder 105, and the row decoder 108 in response to a command (CMD) and an address (ADD) received from outside the memory 100.

[0173] In one example, the command decoder can control the first column decoder 103 and the second column decoder 105 in response to a write operation command or a read operation command, and can send the input column address to the first column decoder 103 and the second column decoder 105.

[0174] In an exemplary embodiment, the command decoder can also control the row decoder 108 in response to a write operation command, a read operation command, an activation command, a precharge command, a refresh command, etc., and can send the input row address to the row decoder 108.

[0175] It should be noted that the memory further includes: a sense amplifier and a row decoder. For the specific operation method, reference can be made to the embodiments of the above memory, which will not be elaborated here.

[0176] It should be understood that the "one embodiment" or "some embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in some embodiments" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitude of the serial numbers of the above processes does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0177] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure.

Claims

1. A memory, characterized in that, Comprising: A memory cell array; A write driver, coupled to the memory cell array, configured to send data signals to be written to the memory cell array according to received write operation commands; A first column decoder, coupled to a first memory cell region of the memory cell array through a first column selection line, configured to perform a write operation on the first memory cell region; The first column selection line includes a virtual line and a mounting line; The virtual line, coupled to the first column decoder and the mounting line, is used to transmit a first column selection signal to the mounting line; The mounting line, coupled to the first memory cell region, is used to transmit the first column selection signal to the first memory cell region; the first column selection signal is used to select a memory cell column in the first memory cell region that performs the write operation; Wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line; The memory cell array includes a second memory cell region and the first memory cell region arranged side by side in a first direction; wherein, the first direction is the direction in which the write driver, the memory cell array, and the first column decoder are arranged in sequence; The virtual line, located in the first memory cell region, is used to transmit a first column selection signal to the mounting line in a second direction opposite to the first direction; The mounting line, coupled to the first memory cell region, is used to transmit the first column selection signal to the first memory cell region in the first direction; wherein, the first column selection signal is used to select a memory cell column in the first memory cell region that performs the write operation.

2. The memory according to claim 1, wherein The memory further includes: a second column decoder, located on opposite sides of the memory cell array from the first column decoder, and on the same side of the memory cell array as the write driver; The second column decoder, coupled to the second memory cell region, is configured to perform a write operation on the second memory cell region.

3. A memory, characterized in that, Comprising: A memory cell array; A write driver, coupled to the memory cell array, configured to send data signals to be written to the memory cell array according to received write operation commands; A first column decoder, coupled to a first memory cell region of the memory cell array through a first column selection line, configured to perform a write operation on the first memory cell region; The first column selection line includes a virtual line and a mounting line; The virtual line, coupled to the first column decoder and the mounting line, is used to transmit a first column selection signal to the mounting line; The mounting line, coupled to the first memory cell region, is used to transmit the first column selection signal to the first memory cell region; the first column selection signal is used to select a memory cell column in the first memory cell region that performs the write operation; Wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line; The memory cell array includes a second memory cell region and the first memory cell region arranged side by side in a first direction; wherein, the first direction is the direction in which the write driver, the first column decoder, and the memory cell array are arranged in sequence. The virtual line is located in the second memory cell region and is used to transmit a first column selection signal to the mounting line in the first direction. The mounting line is coupled to the first memory cell region and is used to transmit the first column selection signal to the first memory cell region in the first direction; wherein, the first column selection signal is used to select the memory cell column in the first memory cell region that performs the write operation.

4. The memory according to claim 3, characterized in that, The memory further includes: a second column decoder, located on the same side of the memory cell array as the first column decoder and the write driver. The second column decoder is coupled to the second memory cell region and is configured to perform a write operation on the second memory cell region.

5. The memory according to claim 2 or 4, characterized in that, The memory further includes: a second column selection line, coupled to the second column decoder and the second memory cell region, and is used to transmit a second column selection signal to the second memory cell region; wherein, the second column selection signal is used to select the memory cell column in the second memory cell region that performs the write operation.

6. The memory according to claim 1, characterized in that, The memory further includes: A command decoder, coupled to the first column decoder, and is configured to control the first column decoder to perform a write operation according to the received write operation command.

7. The memory according to claim 1, wherein The memory includes a dynamic random access memory.

8. A method for operating a memory, characterized in that, The memory includes a memory cell array, a write driver, a first column decoder, and a first column selection line. The first column selection line includes a virtual line and a mounting line. The first column decoder is coupled to the memory cell array through the virtual line and the mounting line. The operation method includes: The write driver sends the data signal to be written to the first memory cell region of the memory cell array according to the received write operation command. The first column decoder transmits a first column selection signal to the mounting line through the virtual line. The mounting line transmits the first column selection signal to the first memory cell region; the first column selection signal is used to select the memory cell column in the first memory cell region that performs the write operation. Wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line. Wherein, the memory cell array includes a second memory cell region and the first memory cell region arranged side by side in a first direction. The first direction is the direction in which the write driver, the memory cell array, and the first column decoder are arranged in sequence; the method includes: The first column decoder transmits a first column selection signal to the mounting line through the virtual line in a second direction opposite to the first direction; wherein, the virtual line is located in the first memory cell region. The mounting line transmits the first column selection signal to the first memory cell region in the first direction; wherein, the mounting line is coupled to the first memory cell region, and the first column selection signal is used to select the memory cell columns in the first memory cell region that perform the write operation.

9. The method for operating a memory according to claim 8, wherein The memory further includes: a second column decoder, located on opposite sides of the memory cell array from the first column decoder, and on the same side of the memory cell array as the write driver; The method further includes: The second column decoder performs a write operation on the second memory cell region.

10. A method for operating a memory, characterized in that, The memory includes a memory cell array, a write driver, a first column decoder, and a first column selection line, the first column selection line includes a virtual line and a mounting line, and the first column decoder is coupled to the memory cell array through the virtual line and the mounting line; The operation method includes: The write driver sends the data signal to be written to the first memory cell region of the memory cell array according to the received write operation command; The first column decoder transmits a first column selection signal to the mounting line through the virtual line; The mounting line transmits the first column selection signal to the first memory cell region; the first column selection signal is used to select the memory cell columns in the first memory cell region that perform the write operation; Wherein, the transmission direction of the data signal to be written sent by the write driver is the same as the transmission direction of the first column selection signal transmitted by the mounting line; Wherein, the memory cell array includes a second memory cell region and the first memory cell region arranged side by side in the first direction; wherein, the first direction is the direction in which the write driver, the first column decoder, and the memory cell array are arranged in sequence; the method includes: The first column decoder transmits a first column selection signal to the mounting line in the first direction through the virtual line; wherein, the virtual line is located in the second memory cell region; The mounting line transmits the first column selection signal to the first memory cell region in the first direction; wherein, the mounting line is coupled to the first memory cell region, and the first column selection signal is used to select the memory cell columns in the first memory cell region that perform the write operation.

11. The method for operating a memory according to claim 10, characterized in that, The memory further includes: a second column decoder, located on the same side of the memory cell array as the first column decoder and the write driver; The method further includes: The second column decoder performs a write operation on the second memory cell region.

12. The method for operating a memory according to claim 9 or 11, characterized in that, The memory further includes: a second column selection line; The second column decoder performing a write operation on the second memory cell region includes: Transmitting a second column selection signal to the second memory cell region through the second column selection line; wherein, the second column selection signal is used to select the memory cell columns in the second memory cell region that perform the write operation.

13. The method for operating a memory according to claim 8, wherein The memory further includes a command decoder; the operation method further includes: The command decoder controls the first column decoder to perform the write operation according to the received write operation command.

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