Failure test method, test device, test apparatus, and readable storage medium

Abstract

The disclosure provides a failure test method, a test device, a test equipment and a readable storage medium, and relates to the technical field of semiconductors. The failure test method comprises the following steps: periodically writing cyclically sequentially shifted test data into a storage unit in a storage array, wherein, in one test period, for an active word line in the storage array, the test data is written in a write unit of a specified burst length of storage units until the storage array is written, in the next test period, the test data is sequentially shifted, and the shifted test data is written into the storage array until the failure test is completed. Through the technical scheme of the disclosure, the test efficiency can be improved by writing test data in a write unit of a specified burst length of storage units.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory chip failure test method, a memory chip failure test device, a memory chip failure test equipment and a computer readable storage medium. BACKGROUND

[0002] DRAM (Dynamic Random Access Memory) is a semiconductor memory widely used in computer systems. The structure of DRAM includes transistors, word lines, bit lines, capacitors, metal interconnections, and outer edge areas. With the advancement of process technology, problems such as structural or functional abnormalities may occur. These abnormal particles need to be screened out during yield testing, so an effective testing method is very important.

[0003] In related technologies, a corresponding AC test scheme is needed for different failure test items, and for some test items, such as short circuit test between storage units, several thousand times of test frequency are needed to complete, resulting in the defects of long test period and high test cost of the current test scheme.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a memory chip failure test method, a test device, a test equipment and a readable storage medium, which can solve the problem of long test period and high test cost of the memory chip in related technologies.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a memory chip failure test method is provided, the memory chip including a storage array, the failure test method comprising: periodically writing cyclically shifted test data to storage units in the storage array, wherein in one test period, for an active word line in the storage array, the test data is written in a write unit of a specified burst length until the storage array is written, in the next test period, the test data is sequentially shifted, and the shifted test data is written to the storage array until the failure test is completed.

[0008] In an exemplary embodiment of the present disclosure, the test data includes two groups of identical 4-bit data, and each group of 4-bit data includes 1-bit first data and 3-bit second data.

[0009] In an exemplary embodiment of the present disclosure, the method further includes: during the process of writing the test data, releasing the timing control of the delay time tRCD for transmitting the row address to the column address of the memory cell.

[0010] In an exemplary embodiment of the present disclosure, the memory chip further includes a sensitive amplifier, wherein both ends of the sensitive amplifier are respectively connected to a bit line and a reference bit line, and the bit line is electrically connected to the memory cell. In one of the test cycles, after writing the test data each time with the memory cell of a specified burst length as the write unit, the test chip further includes: performing an inversion operation on the test data, and writing the inverted test data in the memory cell of the specified burst length, wherein, based on the operation of writing the inverted test data, the voltage across the two ends of the sensitive amplifier changes in the opposite direction to test the inversion capability of the sensitive amplifier.

[0011] In an exemplary embodiment of the present disclosure, after writing the inverted test data into the storage cell of the specified burst length, it also includes: performing a pre-charging operation on the activation word line to turn off the activation word line, and the pre-charging operation is used to change the current direction in the activation word line to accelerate the aging of the high-resistance position in the activation word line.

[0012] In an exemplary embodiment of the present disclosure, during the process of performing the precharge operation on the activated word line that is turned off, the timing control of the precharge effective period tRP is released.

[0013] In an exemplary embodiment of the present disclosure, the test data is written to the activation word line in the storage array with the storage cell of the specified burst length as the write unit until the storage array is written, which includes: after performing the pre-charging operation, performing the activation operation again on the closed activation word line to write the test data and the inverted test data to the next group of storage cells of the specified burst length on the activation word line, and performing the pre-charging operation on the closed activation word line until the write operation on all storage cells on the activation word line is completed.

[0014] In an exemplary embodiment of the present disclosure, the re-performing the activation operation on the turned-off activated word line includes: performing the activation operation on each word line 64 times or 128 times in one test cycle.

[0015] In an exemplary embodiment of the present disclosure, after writing the test data with a storage unit of a specified burst length as a write unit, it also includes: reading the test data written between two adjacent storage units; detecting whether the read result is consistent with the write result; and detecting whether a short circuit occurs between the two adjacent storage units based on the detection result.

[0016] In an exemplary embodiment of the present disclosure, after writing the inverted test data into the storage unit of the specified burst length, it also includes: reading the inverted test data written between two adjacent storage units; detecting whether the read result is consistent with the write result; and detecting whether a short circuit occurs between the two adjacent storage units based on the detection result.

[0017] In an exemplary embodiment of the present disclosure, the two adjacent storage units include any one of two diagonally adjacent storage units, two transversely or longitudinally adjacent storage units, and two storage units diagonally spaced apart by one storage unit.

[0018] In an exemplary embodiment of the present disclosure, the periodic writing of cyclically sequentially shifted test data into the memory cells in the memory array further includes: in the periodic writing of the cyclically sequentially shifted test data into the memory cells in the memory array, detecting a column failure phenomenon based on a signal transmission path, wherein the column failure phenomenon includes at least one of a bit line failure, a sense amplifier failure, and an equalizer failure.

[0019] In an exemplary embodiment of the present disclosure, before periodically writing the cyclically sequentially shifted test data into the memory cells in the memory array, the method further includes: performing an initialization operation on the memory chip.

[0020] According to another aspect of the present disclosure, a failure test device for a memory chip is provided, wherein the memory chip includes a memory array, and the failure test device includes: a write module for periodically writing cyclically sequentially shifted test data to memory cells in the memory array, wherein, in one test cycle, the test data is written to an activated word line in the memory array using memory cells of a specified burst length as write units until the memory array is completed, and in the next test cycle, the test data is sequentially shifted, and the shifted test data is written to the memory array until the failure test is completed.

[0021] According to another aspect of the present disclosure, a failure testing device for a memory chip is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the failure testing method for a memory chip described in any one of the technical solutions of the first aspect above by executing the executable instructions.

[0022] According to yet another aspect of the present disclosure, a computer readable medium is provided, having stored thereon a computer program which, when executed by a processor, implements the memory chip failure test method as described in the above embodiments.

[0023] The memory chip failure test scheme provided by the embodiments of the present disclosure improves the failure test efficiency by performing the write operation of the cyclically sequentially shifted test data on the storage units of the memory chip for periodic failure detection. Specifically, in one test period, first, one word line in the storage array is activated, the intersection of the activated word line and each bit line in the storage array corresponds to one storage unit, for the storage units on the activated word line, the storage units with the specified burst length are taken as the write unit, and the corresponding test data are sequentially written, until the write of the storage units of the complete word line is completed, then the other word lines are sequentially activated, until the write operation on the entire storage array is completed, to complete one test period. After the sequential test data, the test data used in the next test period are obtained, and the storage array is written again, until the failure test is completed. By using the above test method, the test efficiency can be improved by writing the test data with the specified burst length as the write unit, and by reasonably setting the test data and combining the sequential shift update method, the voltage difference can be generated between the adjacent same type devices connected to the storage units, to achieve the test of multiple failure types based on the voltage difference. Further, the above test method can also have a lower impact on the performance of the memory chip.

[0024] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor based on these drawings.

[0026] Figure 1 A schematic block diagram of a memory structure according to an embodiment of the present disclosure;

[0027] Figure 2 A flowchart of a memory chip failure test method according to an embodiment of the present disclosure;

[0028] Figure 3 A partial structure schematic diagram of a memory according to an embodiment of the present disclosure;

[0029] Figure 4 A flowchart of a failure test method of a memory chip according to another embodiment of the present disclosure is provided;

[0030] Figure 5 A potential change diagram for writing data 0 to a memory chip according to an embodiment of the present disclosure;

[0031] Figure 6 A flowchart of a failure test method of a memory chip according to another embodiment of the present disclosure is provided;

[0032] Figure 7 A schematic diagram of a partial memory cell according to an embodiment of the present disclosure;

[0033] Figure 8 A flowchart of a failure test method of a memory chip according to another embodiment of the present disclosure is provided;

[0034] Figure 9 A schematic block diagram of a failure test apparatus of a memory chip according to an embodiment of the present disclosure is provided;

[0035] Figure 10 A structural schematic diagram of a computer system of an electronic device suitable for implementing an embodiment of the present disclosure is provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0037] Moreover, the drawings represent a simplified schematic illustration of the disclosed embodiments and are not necessarily to scale. Like reference numerals in different illustrations denote like or similar elements, and so a repeated description thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities that do not necessarily have to correspond to physically or logically independent entities. These functional entities can be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0038] The flowchart shown in the drawing is only an exemplary illustration, not necessarily including all contents and steps, and not necessarily executed in the order described. For example, some steps can be further decomposed, and some steps can be combined or partially combined, so the actual execution order can be changed according to actual conditions. The terms “one”, “a”, and “the” are used to indicate the presence of one or more elements / components / etc. The terms “include”, “comprise”, and “have” are used to indicate an open-ended inclusion and refer to the presence of additional elements / components / etc. in addition to the listed elements / components / etc.

[0039] As shown in Figure 1 The memory chip includes a memory array 110, a word line driver 120, a bit line selector 130, and a sense amplifier 140. The memory array 110 can include MxN memory cells, where M and N are positive integers. The memory cells are arranged in rows and columns to form the memory array 110. The rows and columns are word lines and bit lines, respectively. Each memory cell corresponds to a unique address. Memory cells in the same row (e.g., C(M,1) to C(M,N)) can be connected to the same word line (e.g., word line WLM). The word lines (WL1 to WLM) can be connected to the word line driver 120. The memory cells in a memory string are selected by controlling the bit line transistor Tb and / or the source line transistor Ts through the bit line selector 130. The memory cells in the memory string are selected by applying a word line read voltage on the word line through the word line driver 120.

[0040] The memory chip also includes a plurality of sense amplifiers 140. Each sense amplifier is electrically connected to a corresponding bit line BL and a reference bit line / BL (not shown in the drawing). During a data read operation, the voltages of the bit line BL and the reference bit line / BL are amplified so that the side with a higher voltage becomes higher and the side with a lower voltage becomes lower to output a recognizable signal.

[0041] Referring to Figure 2 Embodiments of the present disclosure first provide a failure test method for a memory chip, comprising:

[0042] In step S202, cyclically write test data that is sequentially shifted to the memory cells in the memory array. In one test period, for the active word line in the memory array, write the test data in units of memory cells with a specified burst length until the memory array is written. In the next test period, sequentially shift the test data and write the shifted test data to the memory array until the failure test is completed.

[0043] Specifically, the test data is 8-bit data, and each bit of data is used to indicate a high level or a low level.

[0044] The periodically writing cyclically shifting test data means that in two adjacent test periods, the data on each bit of the test data used in the next test period is sequentially shifted forward by one bit, and the data at the last bit is moved to the first bit. Based on the writing mode, it is beneficial to generate a high-low voltage difference between the bit line connected to the storage unit and the signal end of the bit line control signal and control the layout position of the signal, generate a high-low voltage difference, and perform a failure test on the memory chip based on the high-low voltage difference.

[0045] The storage unit is connected with a word line and a bit line, respectively. The word line is used to control the communication between the storage unit and the bit line, and the bit line is used to read and write the storage unit.

[0046] For the activated word line in the storage array, the corresponding word line enters the preparation read / write state by receiving a row activation command, and further performs a failure detection operation based on read / write for each column by receiving a write data instruction and a corresponding column address signal.

[0047] Burst refers to a mode of continuous data transmission of adjacent storage units in the same row. The specified burst length can be at least one burst length of storage units, that is, the number of storage units (columns) involved in continuous transmission. The transmission efficiency is improved based on the burst operation to improve the failure detection efficiency.

[0048] In addition, completing the failure test can be understood as detecting the failure of the memory chip.

[0049] In the embodiment, the periodic failure detection is performed by executing the write operation of the test data of the cyclic sequence shift on the storage units of the memory chip, so as to improve the failure test efficiency. Specifically, in one test period, first, one word line in the storage array is activated, the intersection of the activated word line and each bit line in the storage array corresponds to one storage unit, for the storage unit on the activated word line, the storage unit with the specified burst length is taken as the write unit, and the corresponding test data is sequentially written, until the write of the storage unit of the complete word line is completed, then other word lines are sequentially activated, until the write operation on the entire storage array is completed, so as to complete one test period. After the test data is sequentially shifted, the test data used in the next test period is obtained, and the test data is written to the storage array again, until the failure test is completed. By using the above test method, the test efficiency can be improved by writing the test data with the specified burst length of the storage unit as the write unit. By reasonably setting the test data and combining the update mode of the cyclic sequence shift, a voltage difference can be generated between the adjacent same devices connected to the storage unit, so as to realize the test of multiple failure types based on the voltage difference. Further, the above test method can also have a lower impact on the performance of the memory chip, so as to effectively and efficiently screen out the unstable memory chip products.

[0050] In an exemplary embodiment of the present disclosure, the test data includes two groups of same 4-bit data, and each group of 4-bit data includes 1-bit first data and 3-bit second data.

[0051] In the 4-bit data, the first data is 1 and the second data is 0, or the first data is 0 and the second data is 1.

[0052] Tables 1 to 4 show the test data obtained by cyclic sequence shift based on different test periods.

[0053] As shown in Table 1, in the first test period, first, the word line WL0 is activated, and then one burst length of 8-bit data 10001000 is written, the 8-bit data is composed of two groups of same 4-bit data, 1-bit first data is 1, and 3-bit second data is 0.

[0054] Table 1

[0055] WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 BL0 1 1 1 1 1 1 1 1 BL1 0 0 0 0 0 0 0 0 BL2 0 0 0 0 0 0 0 0 BL3 0 0 0 0 0 0 0 0 BL4 1 1 1 1 1 1 1 1 BL5 0 0 0 0 0 0 0 0 BL6 0 0 0 0 0 0 0 0 BL7 0 0 0 0 0 0 0 0

[0056] As shown in Table 2, in the second test period, 10001000 is sequentially shifted to obtain 01000100, and 01000100 is used as the test data for re-writing.

[0057] Table 2

[0058] WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 BL0 0 0 0 0 0 0 0 0 BL1 1 1 1 1 1 1 1 1 BL2 0 0 0 0 0 0 0 0 BL3 0 0 0 0 0 0 0 0 BL4 0 0 0 0 0 0 0 0 BL5 1 1 1 1 1 1 1 1 BL6 0 0 0 0 0 0 0 0 BL7 0 0 0 0 0 0 0 0

[0059] As shown in Table 3, in the third test cycle, 01000100 is sequentially shifted to obtain 00100010.

[0060] Table 3

[0061] WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 BL0 0 0 0 0 0 0 0 0 BL1 0 0 0 0 0 0 0 0 BL2 1 1 1 1 1 1 1 1 BL3 0 0 0 0 0 0 0 0 BL4 0 0 0 0 0 0 0 0 BL5 0 0 0 0 0 0 0 0 BL6 1 1 1 1 1 1 1 1 BL7 0 0 0 0 0 0 0 0

[0062] As shown in Table 4, in the fourth test cycle, 00100010 is sequentially shifted to obtain 00010001.

[0063] Table 4

[0064] WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 BL0 0 0 0 0 0 0 0 0 BL1 0 0 0 0 0 0 0 0 BL2 0 0 0 0 0 0 0 0 BL3 1 1 1 1 1 1 1 1 BL4 0 0 0 0 0 0 0 0 BL5 0 0 0 0 0 0 0 0 BL6 0 0 0 0 0 0 0 0 BL7 1 1 1 1 1 1 1 1

[0065] In this embodiment, by reasonably setting the test data and combining it with the writing method of Burst length, regular write testing is achieved, and during the write test process, multiple column failure types in the memory chip are tested and corresponding failure results are obtained to shorten the test cycle and improve test efficiency.

[0066] In an exemplary embodiment of the present disclosure, periodically writing cyclically shifted test data into memory cells in a memory array further includes:

[0067] When cyclically writing test data that is shifted in a circular sequence into memory cells in a memory array, column failure phenomena are detected based on signal transmission paths, wherein the column failure phenomena include at least one of bit line failure, sense amplifier failure, and equalizer failure.

[0068] like Figure 3 As shown, the memory chip further includes a sense amplifier 304 . Two ends of the sense amplifier 304 are respectively connected to a bit line BL and a reference bit line / BL. The bit line BL is electrically connected to the memory cell 302 .

[0069] Specifically, if Figure 3 As shown, based on the test data read and write operation, the bit line selector 308 selects the corresponding bit line BL, and the corresponding signal transmission path is: storage unit 302 - bit line BL - sense amplifier 304 - equalizer 306, and is output through the LIO terminal.

[0070] Among them, the memory cell 302 is located at the intersection of the word line WL and the bit line BL and is used to store data. The sense amplifier 304 operates using the bit line BL and the reference bit line / BL to detect and amplify the voltage difference between the bit line BL and the reference bit line / BL. The equalizer 306 is located between the bit line BL and the reference bit line / BL and is used to provide an equalization voltage VEQ (Voltage of Equalizer) to restore the bit line BL and the reference bit line / BL to the same potential. The bit line selector 308 is used to select the bit line BL for read and write operations and control whether the bit line BL is turned on or off, that is, whether the memory cell 302 is read or written through the bit line, and output the read data through the LIO terminal.

[0071] By reading and writing test data, the failure types of columns such as bit lines, sense amplifiers and equalizers can be detected.

[0072] In an exemplary embodiment of the present disclosure, the method further includes: during the process of writing test data, releasing the timing control of the delay time tRCD for transmitting the row address of the memory cell to the column address.

[0073] Among them, tRCD is specifically the delay from RAS (row address signal) to CAS (column address signal). The row corresponds to the word line and the column corresponds to the bit line, that is, the delay from the activation of the word line to finding the corresponding bit line address to complete the addressing.

[0074] In this embodiment, since tRCD has a significant impact on the frequency of the memory chip, not limiting tRCD is beneficial for achieving high-frequency operation of the memory chip, thereby improving test efficiency.

[0075] like Figure 4 As shown, in one test cycle, a failure test method for a memory chip is performed, including:

[0076] Step S402 : writing test data into a storage unit with a designated burst length as a write unit.

[0077] Step S404: performing a negation operation on the test data.

[0078] Step S406 , writing inverted test data into the memory cell of the specified burst length. Based on the operation of writing the inverted test data, the voltage across the sense amplifier changes inversely to test the inversion capability of the sense amplifier.

[0079] After completing step S406 , the process returns to step S402 , and for the next write unit, the original test data is written first, and then the inverted test data is written.

[0080] Specifically, if Figure 5As shown, for any memory cell, if "0" is written based on the test data, VEQ is turned off, WL and SA are turned on, then the potential of the reference bit line / BL is pulled high, while the potential of the bit line BL is pulled low. The test data is inverted, that is, "1" is written. At this time, the potential of the bit line BL is pulled high, while the potential of the reference bit line / BL is pulled low. Based on the sensing of the voltage change at both ends of the sense amplifier, the inversion capability of the sense amplifier can be detected.

[0081] In this embodiment, for a group of memory cells of a burst length, a group of test data and a group of inverted test data are continuously written to cause the voltage across the sense amplifier to change in the opposite direction. Based on the reversely changed voltage, the inversion capability of the sense amplifier can be detected synchronously.

[0082] In addition, the operation of writing "1" corresponds to the charging operation of the capacitor in the storage cell, and the operation of writing "0" corresponds to the discharging operation of the capacitor in the storage cell. Therefore, what is reflected on the word line WL is the charging and discharging operation of the word line WL. Therefore, by writing the inverted detection data, the damage to weak positions such as those prone to breakage in the word line can also be accelerated to accelerate failure detection.

[0083] Tables 5 to 8 show inverted test data obtained by inverting the test data in Tables 1 to 4 and then performing cyclic shifting based on different test cycles.

[0084] Table 5

[0085]

[0086]

[0087] As shown in Table 6, in the second test cycle, 01110111 is sequentially shifted to obtain 10111011, and 10111011 is rewritten using it as the test data.

[0088] Table 6

[0089] WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 BL0 1 1 1 1 1 1 1 1 BL1 0 0 0 0 0 0 0 0 BL2 1 1 1 1 1 1 1 1 BL3 1 1 1 1 1 1 1 1 BL4 1 1 1 1 1 1 1 1 BL5 0 0 0 0 0 0 0 0 BL6 1 1 1 1 1 1 1 1 BL7 1 1 1 1 1 1 1 1

[0090] As shown in Table 7, in the third test cycle, 10111011 is sequentially shifted to obtain 11011101.

[0091] Table 7

[0092]

[0093]

[0094] As shown in Table 8, in the fourth test cycle, 11011101 is sequentially shifted to obtain 11101110.

[0095] Table 8

[0096] WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 BL0 1 1 1 1 1 1 1 1 BL1 1 1 1 1 1 1 1 1 BL2 1 1 1 1 1 1 1 1 BL3 0 0 0 0 0 0 0 0 BL4 1 1 1 1 1 1 1 1 BL5 1 1 1 1 1 1 1 1 BL6 1 1 1 1 1 1 1 1 BL7 0 0 0 0 0 0 0 0

[0097] like Figure 6 As shown, in one test cycle, a failure test method for a memory chip is performed, including:

[0098] Step S602 : writing test data into a memory cell with a designated burst length as a write unit.

[0099] Step S604: perform a negation operation on the test data.

[0100] Step S606 , writing the inverted test data into the storage unit of the specified burst length.

[0101] Step S608 , performing a pre-charging operation on the active word line to turn off the active word line. The pre-charging operation is used to change the direction of current in the active word line to accelerate aging of high-resistance locations in the active word line.

[0102] Specifically, the precharge command is used to precharge the activated row to end the active state. After the precharge is completed, it returns to the idle state and can be activated again. At this time, operation commands such as entering low power consumption, automatic refresh, self-refresh and mode setting can also be input.

[0103] Since DRAM addressing is exclusive, after completing the read and write operations, if you want to address another row in the same bank (a bare chip contains 8 banks, and a row in each bank has shared active and precharge circuits), you must close the original working row, resend the row / column address, close the existing working row, and prepare to open a new row. This operation is called precharging. Precharging can be controlled by commands, or the chip can be automatically precharged after each read and write operation through auxiliary settings.

[0104] In this embodiment, after completing the write operation of a group of detection data and the inverted detection data, the activated row, that is, the activated word line, is precharged to turn off the word line, and the word line is reactivated before the write operation is performed on the next group of memory cells, and precharged again after writing. By repeatedly alternating the precharging and activation operations, the word line can alternately generate forward current and reverse current, which is beneficial to accelerate the aging of the high-resistance position in the word line, thereby realizing the reliability detection of the high-resistance position in the word line while detecting multiple devices connected to the memory cells.

[0105] In an exemplary embodiment of the present disclosure, during the pre-charge operation performed on the closed activation word line, the timing control on the pre-charge effective period tRP is released.

[0106] In this embodiment, the pre-charge effective period tRP (DRAM Row Cycle Time) refers to the minimum time interval between two row activation commands in the same bank, i.e. the time interval from the end of one row access to the restart. By releasing the limitation on the pre-charge effective period, the stability of the invalid detection execution process is ensured.

[0107] In an exemplary embodiment of the present disclosure, for the activated word line in the storage array, the test data is written in the storage unit of the specified burst length as a write unit until the writing of the storage array is completed, including:

[0108] After the pre-charge operation is performed, the activation operation is performed again on the closed activation word line to perform the writing of the test data and the inverted test data on the next group of storage units of the specified burst length on the activated word line, and the pre-charge operation is performed on the closed activation word line until the writing operation on all the storage units on the activated word line is completed.

[0109] In an exemplary embodiment of the present disclosure, the activation operation performed again on the closed activation word line includes: performing 64 or 128 activation operations on each word line in one test period.

[0110] In this embodiment, since each word line is connected with a plurality of storage units, the test operation of one word line in one test period is completed by performing the operation on the plurality of write units respectively, and the reliable detection of the related plurality of invalid positions on one word line is ensured.

[0111] In an exemplary embodiment of the present disclosure, after the test data is written in the storage unit of the specified burst length as a write unit, it further includes: reading the test data written between the adjacent two storage units; detecting whether the reading result is consistent with the writing result; and detecting whether a short circuit occurs between the adjacent two storage units based on the detection result.

[0112] In an exemplary embodiment of the present disclosure, after the inverted test data is written in the storage unit of the specified burst length, it further includes: reading the inverted test data written between the adjacent two storage units; detecting whether the reading result is consistent with the writing result; and detecting whether a short circuit occurs between the adjacent two storage units based on the detection result.

[0113] In this embodiment, after the writing of the test data is completed, whether a short circuit phenomenon occurs between two adjacent memory cells is determined based on a detection result by performing a data reading operation on the memory cells and detecting whether the reading result is consistent with the written test data. By performing the reading operation after the writing, the purpose of failure testing can be achieved under the premise of reducing the number of test items and the test period.

[0114] In an exemplary embodiment of the present disclosure, the two adjacent memory cells include any one of diagonally adjacent two memory cells, two memory cells horizontally or vertically adjacent, and two memory cells diagonally spaced one memory cell.

[0115] Specifically, as shown in Figure 7 Based on the failure detection scheme of the present disclosure, taking C22 as an example, the short circuit failure between C22 and C23 can be detected, and the short circuit failure between C22 and C11, the short circuit failure between C22 and C31, the short circuit failure between C22 and C32, the short circuit failure between C22 and C34, and the short circuit failure between C22 and C43 can also be detected.

[0116] As shown in Figure 8 In an exemplary embodiment of the present disclosure, before the periodically written test data in the memory array is cyclically shifted, it further includes:

[0117] Step S802, performing an initialization operation on the memory chip.

[0118] Step S804, activating a word line and writing test data as a writing unit of memory cells with a specified burst length in a detection period.

[0119] Step S806, performing an inversion operation on the test data and writing the inverted test data in the memory cells with the specified burst length.

[0120] Step S808, performing a pre-charge operation on the activated word line to turn off the activated word line.

[0121] Steps S804 to S808 are repeatedly executed to perform the writing of test data, the writing of inverted test data, and the pre-charge operation of the activated word line on the second group of memory cells with the specified burst length.

[0122] Step S810, detecting that the number of step repetitions is 64 or 128, and completing the detection of a word line in a detection period.

[0123] The next word line is activated, and steps S804 to S810 are repeatedly executed until the detection of all word lines on the memory array is completed.

[0124] Step S812 , after detecting that one test cycle is completed, the test data is sequentially shifted to obtain test data corresponding to the next test cycle, so as to complete the test operation of the next test cycle.

[0125] Step S814: It is detected that the number of completed detection cycles reaches a cycle threshold, and the failure detection is completed.

[0126] Refer to the following Figure 9 A memory chip failure test device 900 according to an embodiment of the present invention is described. The memory chip includes a memory array. Figure 9 The memory chip failure test device 900 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0127] Expressed in the form of hardware modules, the components of the failure testing device 900 may include but are not limited to: a write module 902, which is used to periodically write cyclically shifted test data to the storage cells in the storage array, wherein in one test cycle, the test data is written to the activated word lines in the storage array with the storage cells of the specified burst length as the write unit until the storage array is completed. In the next test cycle, the test data is sequentially shifted and the shifted test data is written to the storage array until the failure test is completed.

[0128] Reference below Figure 10 , which shows a structural diagram of a computer system 1000 suitable for implementing an electronic device of an embodiment of the present disclosure. Figure 10 The computer system 1000 of the electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0129] like Figure 10 As shown, computer system 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage unit 1008 into a random access memory (RAM) 1003. Various programs and data required for system operation are also stored in RAM 1003. CPU 1001, ROM 1002, and RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.

[0130] The following components are connected to the I / O interface 1005: an input part 1006 including a keyboard, a mouse, etc.; an output part 1007 including a display such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage part 1008 including a hard disk, etc.; and a communication part 1009 including a network interface card such as a LAN card, a modem, etc. The communication part 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as necessary. A removable media 1011 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is attached to the drive 1010 as necessary, so that a computer program read out therefrom is installed in the storage part 1008 as necessary.

[0131] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for executing the methods illustrated by the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by the communication part 1009, and / or installed from the removable media 1011. When the computer program is executed by the central processing unit (CPU) 1001, the above-described functions defined in the system of the present application are executed.

[0132] Note that the computer-readable medium shown in the disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination thereof. The computer-readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any combination thereof. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device. In the disclosure, the computer-readable signal medium can include a data signal that propagates in a baseband or as part of a carrier wave, in which the computer-readable program code is carried. Such a propagated data signal can take a variety of forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium that is not a storage medium and that can be used to carry or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any suitable medium, including, but not limited to, wireless, wireline, optical fiber, RF, etc., or any suitable combination of the above.

[0133] The flow diagrams and block diagrams in the drawings are illustrations of possible architectures, functions, and operations of systems, methods, and computer program products in accordance with various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may

[0134] The units described in the embodiments of the present disclosure can be implemented in the form of software, or can be implemented in the form of hardware, and the described units can also be arranged in a processor. In some cases, the names of these units do not constitute a limitation on the units themselves.

[0135] As another aspect, the present application also provides a computer readable medium, which can be included in the electronic device described in the above embodiments, or can exist independently without being assembled into the electronic device. The computer readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to implement the failure test method of the memory chip as described in the above embodiments.

[0136] For example, the electronic device can implement the steps shown in Figure 2 S202, periodically writing cyclically shifted test data to the memory cells in the memory array, wherein in one test period, for an active word line in the memory array, writing the test data as a writing unit of a specified burst length of memory cells until the memory array is written, in the next test period, sequentially shifting the test data, and writing the shifted test data to the memory array until the failure test is completed.

[0137] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, such division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units.

[0138] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. In addition or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0139] Those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or by software in combination with necessary hardware, through the above description of the embodiments. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash disk, a mobile hard disk, or the like) or a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the methods according to the embodiments of the present disclosure.

[0140] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including such departures from the present disclosure that come within known use or custom in the art to which the present disclosure pertains. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for testing failure of a memory chip, characterized in that: The memory chip includes a memory array, and the failure testing method includes: Periodically write cyclically shifted test data to the memory cells in the memory array. In one test cycle, the test data is written into the activated word lines in the memory array using memory cells of a specified burst length as write units until the memory array is completely written. In the next test cycle, the test data is sequentially shifted and the shifted test data is written into the memory array until the failure test is completed.

2. The memory chip failure test method according to claim 1, wherein: The test data includes two groups of identical 4-bit data, and each group of 4-bit data includes 1-bit first data and 3-bit second data.

3. The memory chip failure test method according to claim 1, wherein: Also includes: During the process of writing the test data, the timing control of the delay time tRCD for transmitting the row address to the column address of the memory cell is released.

4. The memory chip failure test method according to claim 1, wherein: The memory chip further includes a sense amplifier, wherein two ends of the sense amplifier are respectively connected to a bit line and a reference bit line, and the bit line is electrically connected to the memory cell. In a test cycle, after writing the test data in memory cells of a specified burst length as a write unit each time, the memory chip further includes: Performing an inversion operation on the test data and writing the inverted test data into the storage unit of the specified burst length, Wherein, based on the operation of writing the inverted test data, the voltage across the sense amplifier changes in the opposite direction, so as to test the inversion capability of the sense amplifier.

5. The memory chip failure test method according to claim 4, wherein: After writing the inverted test data into the storage unit of the specified burst length, the method further includes: A precharge operation is performed on the active word line to turn off the active word line, wherein the precharge operation is used to change the direction of current in the active word line to accelerate aging of a high-resistance position in the active word line.

6. The memory chip failure test method according to claim 5, wherein: In the process of performing the precharge operation on the activated word line that is turned off, the timing control of the precharge effective period tRP is released.

7. The memory chip failure test method according to claim 5, wherein: The step of writing the test data into the activated word lines in the memory array using memory cells of a specified burst length as write units until the memory array is completely written comprises: After performing the precharge operation, the activation operation is performed again on the closed activation word line to write the test data and the inverted test data to the next group of storage cells of the specified burst length on the activation word line, and the precharge operation is performed on the closed activation word line until the write operation on all storage cells on the activation word line is completed.

8. The memory chip failure test method according to claim 7, wherein: The performing the activation operation again on the activated word line that is turned off includes: In one test cycle, the activation operation is performed 64 or 128 times on each word line.

9. The memory chip failure test method according to claim 1, wherein: After writing the test data in a storage unit of a specified burst length as a write unit, the method further includes: reading the test data written between two adjacent storage units; Check whether the read result is consistent with the write result; Based on the detection result, it is detected whether a short circuit occurs between two adjacent memory cells.

10. The memory chip failure test method according to claim 4, wherein: After writing the inverted test data into the storage unit of the specified burst length, the method further includes: reading the inverted test data written between two adjacent storage cells; Check whether the read result is consistent with the write result; Based on the detection result, it is detected whether a short circuit occurs between two adjacent memory cells.

11. The memory chip failure test method according to claim 9 or 10, characterized in that: The two adjacent storage units include any one of two diagonally adjacent storage units, two transversely or longitudinally adjacent storage units, and two storage units that are diagonally spaced apart by one storage unit.

12. The memory chip failure test method according to claim 1, wherein: The step of periodically writing the cyclically shifted test data into the storage cells in the storage array further includes: In periodically writing the cyclically shifted test data into the memory cells in the memory array, a column failure phenomenon is detected based on the signal transmission path. The column failure phenomenon includes at least one of a bit line failure, a sense amplifier failure and an equalizer failure.

13. The memory chip failure testing method according to any one of claims 1 to 10, characterized in that: Before periodically writing the cyclically shifted test data into the memory cells in the memory array, the method further includes: An initialization operation is performed on the memory chip.

14. A failure test device for a memory chip, characterized in that: The memory chip includes a memory array, and the failure testing device includes: The writing module is used to periodically write the test data of the cyclic sequence shift into the storage cells in the storage array. In one test cycle, the test data is written into the activated word lines in the memory array using memory cells of a specified burst length as write units until the memory array is completely written. In the next test cycle, the test data is sequentially shifted and the shifted test data is written into the memory array until the failure test is completed.

15. A failure test device for a memory chip, characterized in that: include: processor; as well as a memory for storing executable instructions of the processor; The processor is configured to execute the memory chip failure testing method according to any one of claims 1 to 13 by executing the executable instructions.

16. A computer-readable medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the failure testing method for a memory chip according to any one of claims 1 to 13 is implemented.

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