Pixel

Abstract

A pixel includes: an organic light emitting diode; a first transistor including a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second transistor including a gate connected to a corresponding scan line, the second transistor being connected between a data line and a second node; a storage capacitor being connected between the first node and a first voltage; a third transistor including a gate connected to a corresponding scan line, the third transistor being connected between the first node and a third node; a fourth transistor including a gate, a source directly connected to a source of the first transistor or a drain of the first transistor, and a drain connected to a second voltage; a fifth transistor including a gate connected to an emission control line, the fifth transistor being connected between the first voltage and the second node; and a sixth transistor including a gate connected to the emission control line, the sixth transistor being connected between the third node and an anode of the organic light emitting diode.

Description

[0001] This application is a divisional application of the invention patent application with application date of March 7, 2019, application number 201910172178.7, and invention name “Pixel and display device including the pixel”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0027043 filed on March 7, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates to a pixel and a display device using the same, and particularly, the present disclosure relates to a pixel for improving crosstalk and a display device using the same. Background Art

[0005] Among various flat panel displays, organic light emitting diode displays use organic light emitting diodes (OLEDs) as light emitting elements that generate light through recombination of electrons and holes for displaying images. OLED displays have fast response speed, low power consumption, and excellent luminous efficiency, brightness, and viewing angle.

[0006] Recently, multiple pixels are integrated in a narrow area of ​​a high-resolution display device requiring very small transistors. The reduction in the size of transistors means a reduction in the length of the channel region, and as the length of the channel region decreases, a problem of current leakage through the turned-off transistor occurs.

[0007] Specifically, when the display device operates at a high temperature, a threshold voltage of a transistor shifts, and thus a relatively large current leaks through a channel region of a transistor that is turned off.

[0008] The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore it may contain information that may not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0009] The present disclosure is made in order to remove leakage current generated by operating at high temperature.

[0010] The present disclosure is made in order to prevent the crosstalk phenomenon of a display device.

[0011] An exemplary embodiment of the present disclosure provides a pixel, which includes: an organic light emitting diode; a first transistor, the first transistor including a gate connected to a first node, wherein the first transistor is connected between a second node and a third node; a second transistor, the second transistor including a gate connected to a corresponding scan line, wherein the second transistor is connected between a data line and the second node; a storage capacitor, the storage capacitor is connected between the first node and a first voltage; a third transistor, the third transistor including a gate connected to the corresponding scan line, wherein the third transistor is connected between the first node and the third node; and a fourth transistor, the fourth transistor is connected between a first end of the first transistor and a second voltage.

[0012] The fourth transistor may be connected between the second node and the second voltage, and a leakage current applied from the second transistor may flow through the fourth transistor.

[0013] The fourth transistor may include a gate and a source connected to the second node, and a drain connected to the second voltage.

[0014] The fourth transistor may include a source connected to the second node, a drain connected to the second voltage, and a gate connected to a DC voltage source having a voltage value of a gate-off level of the fourth transistor.

[0015] The fourth transistor may be connected between the third node and the second voltage, and a leakage current applied from the second transistor may flow through the fourth transistor in an off state.

[0016] The fourth transistor may include a gate and a source connected to the third node, and a drain connected to the second voltage.

[0017] The fourth transistor may include a source connected to the third node, a drain connected to the second voltage, and a gate connected to a DC voltage source having a voltage value of a gate-off level of the fourth transistor.

[0018] The pixel may further include: a fifth transistor, the fifth transistor including a gate connected to an emission control line, wherein the fifth transistor is connected between the first voltage and the second node; a sixth transistor, the sixth transistor including a gate connected to the emission control line, wherein the sixth transistor is connected between the third node and the anode of the organic light emitting diode; a seventh transistor, the seventh transistor including a gate connected to a previous scan line of the corresponding scan line, wherein the seventh transistor is connected between the first node and the second voltage; and an eighth transistor, the eighth transistor including a gate connected to the previous scan line, wherein the eighth transistor is connected between the anode of the organic light emitting diode and the second voltage.

[0019] The period during which the second transistor is turned off may correspond to a period after the second transistor is turned off until the organic light emitting diode emits light.

[0020] Another embodiment of the present disclosure provides a display device, the display device comprising: a scan driver, the scan driver is used to transmit a plurality of scan signals to a plurality of scan lines; a data driver, the data driver is used to transmit a plurality of data signals to a plurality of data lines; a display unit, the display unit comprising a plurality of pixels, the plurality of pixels are respectively connected to corresponding scan lines among the plurality of scan lines and corresponding data lines among the plurality of data lines, the pixels respectively emit light according to corresponding data signals and display images; and a controller, the controller is used to control the scan driver and the data driver, generate the data signal and supply the data signal to the data driver, wherein the plurality of pixels The pixel includes: an organic light emitting diode; a first transistor, the first transistor including a gate connected to a first node, wherein the first transistor is connected between a second node and a third node; a second transistor, the second transistor including a gate connected to a corresponding scan line, wherein the second transistor is connected between a data line and the second node; a storage capacitor, the storage capacitor is connected between the first node and a first voltage; a third transistor, the third transistor including a gate connected to the corresponding scan line, wherein the third transistor is connected between the first node and the third node; and a fourth transistor, the fourth transistor is connected between a first end of the first transistor and a second voltage.

[0021] The fourth transistor may be connected between the second node and the second voltage, and a leakage current applied from the second transistor may flow through the fourth transistor.

[0022] The fourth transistor may include a gate and a source connected to the second node, and a drain connected to the second voltage.

[0023] The fourth transistor may include a source connected to the second node, a drain connected to the second voltage, and a gate connected to a DC voltage source having a voltage value of a gate-off level of the fourth transistor.

[0024] The fourth transistor is connected between the third node and the second voltage, and a drain current applied from the second transistor flows through the fourth transistor in an off state.

[0025] The fourth transistor may include a gate and a source connected to the third node, and a drain connected to the second voltage.

[0026] The fourth transistor may include a source connected to the third node, a drain connected to the second voltage, and a gate connected to a DC voltage source having a voltage value of a gate-off level of the fourth transistor.

[0027] The display device may also include an emission control driver for transmitting multiple emission control signals to multiple emission control lines, wherein the controller generates a control signal for controlling the emission control driver, and the pixel also includes: a fifth transistor, the fifth transistor including a gate connected to a corresponding emission control line among the multiple emission control lines, wherein the fifth transistor is connected between the first voltage and the second node; a sixth transistor, the sixth transistor including a gate connected to the corresponding emission control line, wherein the sixth transistor is connected between the third node and the anode of the organic light emitting diode; a seventh transistor, the seventh transistor including a gate connected to a previous scan line of the corresponding scan line, wherein the seventh transistor is connected between the first node and the second voltage; and an eighth transistor, the eighth transistor including a gate connected to the previous scan line, wherein the eighth transistor is connected between the anode of the organic light emitting diode and the second voltage.

[0028] The period during which the second transistor is turned off may correspond to a period after the second transistor is turned off until the organic light emitting diode emits light.

[0029] Another embodiment of the present disclosure provides a pixel, which includes: a storage capacitor, which is used to store a data voltage corresponding to a data signal transmitted from a corresponding data line when a scan signal transmitted from a corresponding scan line has an enable level; a first transistor, which is used to generate a driving current corresponding to the data voltage; and a second transistor, which is connected between a first end of the first transistor and an initialization voltage.

[0030] During a period in which the second transistor is turned off, a leakage current flows through the second transistor, wherein the leakage current is caused by another data signal applied to the corresponding data line when the scan signal has a de-enabling level.

[0031] According to exemplary embodiments, when the display device operates at a high temperature, the leakage current caused by the black voltage may be removed.

[0032] According to exemplary embodiments, a crosstalk phenomenon of the display device may be prevented.

[0033] According to exemplary embodiments, a high-quality organic light-emitting device may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A block diagram illustrating a display device according to an exemplary embodiment is shown.

[0035] Figure 2 The first exemplary embodiment is shown Figure 1 Circuit diagram of a pixel of a display device shown in .

[0036] Figure 3 Shown for drive Figure 1 0 is a timing diagram of the signals of the pixel shown in .

[0037] Figure 4 Shown by Figure 3 A portion of a pixel driven by the signal shown in FIG.

[0038] Figure 5A A display unit of a comparative display device showing a crosstalk phenomenon is shown.

[0039] Figure 5B A display unit of a display device according to an exemplary embodiment is illustrated.

[0040] Figure 6 According to the second exemplary embodiment, Figure 1 Circuit diagram of a pixel of a display device shown in .

[0041] Figure 7 The third exemplary embodiment is shown. Figure 1 Circuit diagram of a pixel of a display device shown in .

[0042] Figure 8 The fourth exemplary embodiment is shown. Figure 1 Circuit diagram of a pixel of a display device shown in . DETAILED DESCRIPTION

[0043] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. As those skilled in the art will realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0044] The drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals refer to like elements throughout the specification.

[0045] Unless explicitly described to the contrary, the word “comprise” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0046] Figure 1 A block diagram of a display device according to an exemplary embodiment is shown. As shown, the display device includes a display unit 10 including a plurality of pixels PX1 to PXn, a scan driver 20, a data driver 30, an emission control driver 40, a power supply 50, and a controller 60.

[0047] Each of the pixels PX1 to PXn is connected to two corresponding scan lines among the plurality of scan lines S1 to Sn, one corresponding emission control line among the plurality of emission control lines EM1 to EMn, and one corresponding data line among the plurality of data lines D1 to Dm. Figure 1 Although not directly shown in the display unit 10 , the plurality of pixels PX1 to PXn are connected to a plurality of power lines to receive a first power voltage ELVDD, a second power voltage ELVSS, and an initialization voltage Vint from a power source 50 .

[0048] A plurality of pixels PX1 to PXn included in the display unit 10 are arranged substantially in a matrix form. Although not particularly limited, a plurality of scan lines S1 to Sn and a plurality of emission control lines EM1 to EMn extend substantially in a row direction of the pixels, and a plurality of data lines D1 to Dm extend substantially in a column direction of the pixels, and the scan lines are disposed substantially in parallel with each other, the emission control lines are disposed substantially in parallel with each other, and the data lines are disposed substantially in parallel with each other.

[0049] Each of the plurality of pixels PX1 to PXn is connected to two corresponding scan lines. That is, each of the pixels PX1 to PXn is connected to a first scan line corresponding to a pixel row including the corresponding pixel and a second scan line corresponding to a previous pixel row. A group of pixels included in the first pixel row may be connected to a first scan line S1 and a dummy scan line S0. A group of pixels included in an n-th pixel row (n is greater than 1) is respectively connected to an n-th scan line Sn corresponding to an n-th pixel row as a corresponding pixel row and an n-1-th scan line Sn-1 corresponding to an n-1-th pixel row as a previous pixel row.

[0050] Each of the plurality of pixels PX1 to PXn emits light having a predetermined brightness by a driving current supplied to the organic light emitting diode according to a corresponding data signal transmitted through the plurality of data lines D1 to Dm.

[0051] The scan driver 20 generates a scan signal corresponding to each pixel through a plurality of scan lines S1 to Sn and transmits the scan signal. That is, the scan driver 20 transmits the scan signal through the scan lines corresponding to the respective plurality of pixels included in each pixel row.

[0052] The scan driver 20 receives the scan driving control signal SCS from the controller 60 to generate a scan signal, and sequentially supplies the scan signal to a plurality of scan lines S1 to Sn respectively connected to a group of pixels included in each pixel row.

[0053] The data driver 30 transmits data signals to respective pixels through a plurality of data lines D1 to Dm.

[0054] The data driver 30 receives a data driving control signal DCS from the controller 60 and supplies data signals corresponding to a plurality of data lines D1 to Dm respectively connected to a group of pixels included in each pixel column.

[0055] The emission control driver 40 is connected to a plurality of emission control lines EM1 to EMn connected to the plurality of pixels PX1 to PXn. That is, the plurality of emission control lines EM1 to EMn extend substantially parallel to each other in a row direction and connect the plurality of pixels and the emission control driver 40 .

[0056] The emission control driver 40 generates an emission control signal corresponding to each pixel through a plurality of emission control lines EM1 to EMn. Each pixel is controlled to emit light corresponding to a data signal in response to control by the emission control signal. That is, the operation of the emission control transistor included in the pixel is controlled in response to the emission control signal transmitted through the corresponding emission control line, so that the organic light emitting diode connected to the emission control transistor may or may not emit light having a brightness based on the driving current corresponding to the data signal.

[0057] The power supply 50 supplies a first power voltage ELVDD, a second power voltage ELVSS, and an initialization voltage Vint to each pixel of the display unit 10. The first power voltage ELVDD may be a predetermined high level voltage, and the second power voltage ELVSS may be less than the first power voltage ELVDD or may be a ground voltage. The initialization voltage Vint may be set to a voltage value equal to or less than the second power voltage ELVSS.

[0058] The voltage values ​​of the first power voltage ELVDD, the second power voltage ELVSS, and the initialization voltage Vint are not limited to specific voltage values, but the voltage values ​​may be set or controlled according to the control of the power control signal PCS transmitted by the controller 60 .

[0059] The controller 60 transforms the plurality of image signals into a plurality of image data signals DATA and transmits the plurality of image data signals DATA to the data driver 30. The controller 60 receives a vertical synchronization signal, a horizontal synchronization signal, and a clock signal (not shown), generates a control signal for controlling the scan driver 20, the emission control driver 40, and the data driver 30, and transmits the control signal to the scan driver 20, the emission control driver 40, and the data driver 30. That is, the controller 60 generates a scan driving control signal SCS for controlling the scan driver 20, an emission driving control signal ECS for controlling the emission control driver 40, and a data driving control signal DCS for controlling the data driver 30, and transmits the scan driving control signal SCS for controlling the scan driver 20, the emission driving control signal ECS for controlling the emission control driver 40, and the data driving control signal DCS for controlling the data driver 30.

[0060] Furthermore, the controller 60 generates a power control signal PCS for controlling the power source 50 and transmits the power control signal PCS for controlling the power source 50 to the power source 50 .

[0061] Figure 2 and Figures 6 to 8 A circuit diagram of a pixel according to an exemplary embodiment of the present disclosure is shown. Specifically, Figure 2 and Figures 6 to 8 According to various exemplary embodiments, the Figure 2 1 is a circuit diagram of a pixel (PXn) 100 in an area defined by an n-th pixel row and an m-th pixel column among a plurality of pixels PX1 to PXn of a display unit 10 shown in FIG. In these exemplary embodiments, for ease of description, each transistor is exemplified as a p-channel metal oxide semiconductor field effect transistor (MOSFET) (PMOS transistor).

[0062] Figure 3 Shown for drive Figure 2 and Figures 6 to 8 The timing diagram of the pixel signal will be described according to Figure 2 and Figures 6 to 8 A process of driving pixels of an exemplary embodiment.

[0063] Figure 2The pixel 100 - 1 shown in FIG. 1 includes an organic light emitting diode OLED, a storage capacitor Cst, and first to eighth transistors T1 to T8 .

[0064] The first transistor T1 includes a gate connected to a first node N1, a source connected to a second node N2, and a drain connected to a third node N3, wherein the second node N2 is also connected to a drain of a fifth transistor T5. A driving current flows through the first transistor T1 according to a corresponding data signal D[i]. The gate, source, and drain of a transistor may also be referred to as a gate electrode, a source electrode, and a drain electrode in the text.

[0065] The driving current represents a current corresponding to a voltage difference between a source and a gate of the first transistor T1 , and may be a variable current corresponding to a data voltage of the data signal D[i].

[0066] The second transistor T2 includes a gate connected to the j-th scan line Sj, a source connected to the i-th data line Di, and a drain connected to the second node N2, and the source of the first transistor T1 and the drain of the fifth transistor T5 are commonly connected to the second node N2. The second transistor T2 transmits a data voltage corresponding to the data signal D[i] through the i-th data line Di to the second node N2 in response to the corresponding scan signal S[j] transmitted through the j-th scan line Sj.

[0067] The third transistor T3 includes a gate connected to the j-th scan line Sj and a drain and a source connected to the gate and drain of the first transistor T1, respectively. The third transistor T3 operates in response to a corresponding scan signal S[j] transmitted through the j-th scan line Sj. When turned on, the third transistor T3 connects the gate and the drain of the first transistor T1 to connect the first transistor T1 in a diode manner.

[0068] When the first transistor T1 is connected in a diode manner, a voltage compensated by the threshold voltage of the first transistor T1 from the data voltage applied to the source of the first transistor T1 is applied to the gate of the first transistor T1. The gate of the first transistor T1 is connected to the first electrode of the storage capacitor Cst, so the voltage is maintained by the storage capacitor Cst. The data voltage compensated by the threshold voltage of the first transistor T1 is applied to the gate and maintained by the storage capacitor Cst, so the driving current flowing through the first transistor T1 may not be affected by the threshold voltage of the first transistor T1.

[0069] The fourth transistor T4 includes a gate connected to the j-1th scan line Sj-1, a source connected to the initialization voltage supply line, and a drain connected to the first node N1. The fourth transistor T4 transmits the initialization voltage Vint applied through the initialization voltage supply line to the first node N1 in response to the j-1th scan signal S[j-1] transmitted through the j-1th scan line Sj-1. The fourth transistor T4 may transmit the initialization voltage Vint to the first node N1 before applying the data signal D[i] in response to the j-1th scan signal S[j-1] transmitted through the j-1th scan line Sj-1 corresponding to the previous j-1th pixel row. The j-1th scan signal S[j-1] transmitted through the j-1th scan line Sj-1 is transmitted to the j-1th pixel row before the scan signal S[j] transmitted through the j-1th scan line Sj-1 is transmitted to the j-1th pixel row.

[0070] In this case, the voltage value of the initialization voltage Vint is not limited, but the voltage value of the initialization voltage Vint can be set to a low level voltage value that can reduce the gate voltage of the first transistor T1 to initialize. That is, during the period in which the j-1th scan signal S[j-1] is transmitted to the gate of the fourth transistor T4 at the gate-on voltage level, the gate of the first transistor T1 is initialized to have the initialization voltage Vint.

[0071] The fifth transistor T5 includes a gate connected to the j-th emission control line EMj, a source connected to the first power voltage ELVDD supply line, and a drain connected to the second node N2.

[0072] The sixth transistor T6 includes a gate electrode connected to the j-th emission control line EMj, a source electrode connected to the third node N3, and a drain electrode connected to the anode electrode of the organic light emitting diode OLED.

[0073] The fifth transistor T5 and the sixth transistor T6 operate in response to the j-th emission control signal EM[j] transmitted through the j-th emission control line EMj. When the fifth transistor T5 and the sixth transistor T6 are turned on in response to the j-th emission control signal EM[j], a current path is formed in a direction from the first power supply voltage ELVDD toward the organic light emitting diode OLED. The driving current flowing through the organic light emitting diode OLED causes the organic light emitting diode OLED to emit light according to the driving current, thereby displaying an image corresponding to the data signal through the pixel 100-1.

[0074] A first electrode of the storage capacitor Cst is connected to the first node N1, and a second electrode of the storage capacitor Cst is connected to the first power voltage ELVDD supply line. As described above, the storage capacitor Cst is connected between the gate of the first transistor T1 and the first power voltage ELVDD supply line, thereby maintaining the voltage applied to the gate of the first transistor T1.

[0075] The seventh transistor T7 includes a gate electrode connected to the j-1th scan line Sj-1, a source electrode connected to the anode electrode of the organic light emitting diode OLED, and a drain electrode connected to the initialization voltage Vint.

[0076] The seventh transistor T7 can transmit the initialization voltage Vint to the anode of the organic light emitting diode OLED in response to the j-1th scan signal S[j-1] transmitted through the j-1th scan line Sj-1 corresponding to the previous j-1th pixel row, and reset the anode of the organic light emitting diode OLED to a sufficiently low voltage according to the transmitted initialization voltage Vint.

[0077] The eighth transistor T8 includes a source and a gate connected to the second node N2 and a drain connected to the initialization voltage Vint. The gate and the source of the eighth transistor T8 are commonly connected to the second node N2, so the eighth transistor T8 is diode-connected at the second node N2.

[0078] Relative to Figure 1 The block diagram of the display device shown in Figure 2 The circuit diagram of the pixel 100-1 shown in FIG. Figure 3 The timing diagram details the drive operation.

[0079] Figure 3 Shown for drive Figure 1 100 is a timing diagram of the signals of the pixel 100 shown in FIG. Figure 3 It is described that some pixels display a black image, for example, pixels connected to the n-1th scan line Sn-1 and the i-th data line Di and pixels connected to the n-th scan line Sn and the same i-th data line Di.

[0080] Other pixels connected to the same i-th data line Di may be affected by the data signal Black corresponding to the black grayscale applied to the pixel displaying the black image. After the data signal is transmitted to some pixels until the emission control signal having the low level voltage L is applied, a leakage current Ib may be generated by the data signal Black applied to the i-th data line Di. In this case, the voltage stored in the first node N1 may be reduced by the leakage current Ib. With the reduced voltage, each pixel may display an image darker than the image according to the corresponding data signal, thereby generating a crosstalk phenomenon.

[0081] Therefore, a crosstalk phenomenon may be generated by pixels connected to the same data line Di as the pixel displaying the black image.

[0082] Reference Figure 2 and Figure 3 During the period between t11 and t12, the fourth transistor T4 and the seventh transistor T7 are turned on by the low level voltage L of the j-1th scan signal S[j-1] transmitted through the j-1th scan line Sj-1. The initialization voltage Vint for initializing the voltage at the gate electrode of the first transistor T1 is transmitted to the first node N1 through the fourth transistor T4.

[0083] During the period between t12 and t13, the second transistor T2 and the third transistor T3 are turned on by the low level voltage L of the j-th scan signal S[j] transmitted through the j-th scan line Sj. The corresponding data signal GR2 on the data line Di is transmitted to the second node N2 through the turned-on second transistor T2, and the first transistor T1 is diode-connected through the turned-on third transistor T3.

[0084] During the period between t14 and t15, a data signal Black corresponding to a black grayscale is applied to the i-th data line Di. Figure 4 Describes the period between t14 and t15.

[0085] Figure 4 Shown by Figure 3 A portion of a pixel connected to the j-th scan line Sj and the i-th data line Di driven by the signal shown in Figure 4 As shown in , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , and the sixth transistor T6 are turned off.

[0086] However, when the transistors T1 to T8 included in the pixel 100 - 1 operate at a high temperature, leakage current may flow through the transistors when a voltage difference between a gate and a source is small or zero according to a forward shift of a threshold voltage of the transistors.

[0087] When a black voltage Vblack corresponding to a data signal Black of a black grayscale is applied to the i-th data line Di, a leakage current Ib1 may flow through the turned-off second transistor T2 by a voltage difference between the black voltage Vblack and the second node N2.

[0088] The eighth transistor T8 is reversely connected to the second node N2 in a diode manner, and the initialization voltage supply line is connected to the drain of the eighth transistor T8. By means of the positive shift of the threshold voltage and the voltage difference between the initialization voltage Vint and the second node N2, the leakage current Ib1 drops to the initialization voltage Vint through the eighth transistor T8. Therefore, applying the black voltage Vblack to the i-th data line Di before the pixel 100-1 emits light does not affect the voltage Vdata-Vth maintained at the first node N1 in the pixel 100-1.

[0089] During a period between t18 and t20, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EM[j] having the low level voltage L. A driving current caused by the voltage stored in the storage capacitor Cst is transmitted to the organic light emitting diode OLED, and the organic light emitting diode OLED emits light.

[0090] In a conventional pixel configuration without the eighth transistor T8, the drain current Ib0 is transmitted to the first node N1 through the first transistor T1 and the turned-off third transistor T3 to reduce the voltage. Therefore, the pixel displays a grayscale less than the grayscale according to the data voltage applied to the data line Di, thereby generating a crosstalk phenomenon.

[0091] Figure 5A A display unit of a comparative display device showing a crosstalk phenomenon is shown, and Figure 5B FIG. 2 shows a display unit of a display device according to an exemplary embodiment. Figure 5A and Figure 5B , it will be assumed that the first area 150 of the display unit 10 displays a black image, and the adjacent areas 151 and 152 display white images.

[0092] like Figure 5A As shown in , when the first area 150 in the display unit 10 displays a black image, the adjacent areas 151 and 152 including pixels connected to the same data line as the pixels in the first area 150 display images darker than the white image, thereby exhibiting a crosstalk phenomenon.

[0093] However, in the case of a display device including the pixel 100-1 according to an exemplary embodiment, as shown in FIG. Figure 5B As shown in FIG. 1 , when the first region 150 displays a black image, the adjacent regions 151 and 152 including pixels connected to the same data line as the pixels in the first region 150 display a white image without exhibiting a crosstalk phenomenon.

[0094] That is, according to the exemplary embodiment, even when the display device operates at a high temperature, the use of the eighth transistor T8 can remove the leakage current caused by the black voltage, thereby preventing the crosstalk phenomenon of the display device.

[0095] Now refer to Figures 6 to 8 Pixels according to other exemplary embodiments are described.

[0096] Figure 6 Shows what can be included Figure 1 Pixel 100-2 in the display device.

[0097] In addition to alternative Figure 2 In addition to the eighth transistor T18 of the eighth transistor T8 of the pixel 100-1 shown in FIG. Figure 6 The pixel 100-2 shown in FIG. Figure 2 The pixel 100-1 is the same.

[0098] The eighth transistor T18 includes a source and a gate connected to the third node N3 and a drain connected to the initialization voltage Vint. The gate and the source of the eighth transistor T18 are commonly connected to the third node N3, so the eighth transistor T18 is diode-connected to the third node N3.

[0099] About reference Figure 3 In the operation process of the pixel 100-2, during the period between t11 and t12, the fourth transistor T4 and the seventh transistor T7 are turned on by the low level voltage L of the j-1th scan signal S[j-1] transmitted through the j-1th scan line Sj-1. The initialization voltage Vint for initializing the voltage of the gate electrode of the first transistor T1 is transmitted to the first node N1 through the fourth transistor T4.

[0100] During the period between t12 and t13, the second transistor T2 and the third transistor T3 are turned on by the low level voltage L of the j-th scan signal S[j] transmitted through the j-th scan line Sj. The corresponding data signal GR2 on the data line Di is transmitted to the second node N2 through the turned-on second transistor T2, and the first transistor T1 is diode-connected through the turned-on third transistor T3.

[0101] During a period between t14 and t15, a data signal Black corresponding to a black grayscale is applied to the i-th data line Di.

[0102] Due to the voltage difference between the black voltage Vblack and the second node N2 , the leakage current Ib may flow to the second node N2 through the turned-off second transistor T2 and further flow to the third node N3 through the first transistor T1 .

[0103] The eighth transistor T18 is reversely connected to the third node N3 in a diode manner, and the initialization voltage Vint is connected to the drain of the eighth transistor T18. By means of the positive shift of the threshold voltage and the voltage difference between the initialization voltage Vint and the third node N3, the drain current Ib drops to the initialization voltage Vint through the eighth transistor T18. Therefore, applying the black voltage Vblack to the i-th data line Di before the pixel 100-2 emits light does not affect the voltage maintained at the first node N1 of the pixel 100-2.

[0104] During a period between t18 and t20, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EM[j] having the low level voltage L. A driving current is transmitted to the organic light emitting diode OLED by the voltage charged in the storage capacitor Cst, and the organic light emitting diode OLED emits light.

[0105] That is, according to an exemplary embodiment, when the display device operates at a high temperature, a crosstalk phenomenon of the display device may be prevented by removing a leakage current that may be caused by a black voltage using the eighth transistor T18.

[0106] Figure 7 1 shows a pixel 100-3 according to an exemplary embodiment. In addition, the gate of the eighth transistor T28 replacing the eighth transistor T8 is connected to a DC voltage source. Figure 7 The pixel 100-3 shown in FIG. Figure 2 The pixel 100-1 shown in FIG.

[0107] Right now, Figure 7 The eighth transistor T28 shown in FIG. 1 includes a source connected to the second node N2, a drain connected to the initialization voltage Vint, and a gate connected to the DC voltage source. Therefore, the eighth transistor T28 receives a predetermined DC voltage from the DC voltage source, and the element of the pixel 100-3 is connected according to Figure 3 In this case, the DC voltage is a predetermined voltage for turning off the eighth transistor T28, and Figure 7 In the exemplary embodiment of FIG. 1 , the pixel 100 - 3 is configured as a PMOS transistor, and thus the DC voltage may be a predetermined high-level voltage.

[0108] Therefore, a direct current voltage having a transistor-off level is transmitted to the gate, and thus the eighth transistor T28 is turned off, and a drain current Ib caused by the black voltage Vblack applied to the i-th data line Di drops to the initialization voltage Vint.

[0109] Figure 8 1 shows a pixel 100-4 according to an exemplary embodiment. In addition, the eighth transistor T38 replacing the eighth transistor T18 is connected to a DC voltage source. Figure 8 The pixel 100-4 shown in FIG. Figure 6 The pixel 100 - 2 shown in FIG. 1 is the same.

[0110] Right now, Figure 8 The eighth transistor T38 shown in FIG. 1 includes a source connected to the third node N3, a drain connected to the initialization voltage Vint, and a gate connected to the DC voltage source. Therefore, the eighth transistor T38 receives a predetermined DC voltage from the DC voltage source, and the element of the pixel 100-4 is connected according to Figure 3 The operation of the drive timing diagram is irrelevant.

[0111] The eighth transistor T38 is turned off by applying a direct current voltage of a transistor-off level to the gate, and thus a leakage current Ib caused by the black voltage Vblack applied to the i-th data line Di drops to the initialization voltage Vint.

[0112] Including according to Figure 2 and Figures 6 to 8 In the display device of the pixels 100-1, 100-2, 100-3, and 100-4 of the exemplary embodiment, when the display device operates at a high temperature, a leakage current that may be caused by a black voltage is removed to suppress a crosstalk phenomenon, thereby improving image quality characteristics.

[0113] Regarding pixels 100-1, 100-2, 100-3 and 100-4, it is described that the eighth transistors T8, T18, T28 and T38 are connected to the second node N2 or the third node N3, respectively, however, the eighth transistor T8 may be connected to the second node N2 of one pixel, and the eighth transistor T18 may be connected to the third node N3 of the pixel.

[0114] While the disclosure has been described in conjunction with what are presently considered to be practical exemplary embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the disclosure.

Claims

1. A pixel, wherein The pixels include: Organic light-emitting diodes; a first transistor including a gate connected to the first node, a source connected to the second node, and a drain connected to the third node; a second transistor including a gate connected to a corresponding scan line, wherein the second transistor is connected between the data line and the second node; a storage capacitor connected between the first node and a first voltage; a third transistor comprising a gate connected to the corresponding scan line, wherein the third transistor is connected between the first node and the third node; a fourth transistor including a gate, a source directly connected to the source of the first transistor or the drain of the first transistor, and a drain connected to a second voltage; a fifth transistor including a gate connected to an emission control line, wherein the fifth transistor is connected between the first voltage and the second node; and A sixth transistor includes a gate connected to the emission control line, wherein the sixth transistor is connected between the third node and an anode of the organic light emitting diode.

2. The pixel according to claim 1, wherein: The fourth transistor is connected between the second node and the second voltage, and a leakage current applied from the second transistor flows through the fourth transistor.

3. The pixel according to claim 2, wherein: The fourth transistor includes a gate and a source connected to the second node and a drain connected to the second voltage.

4. The pixel according to claim 1, wherein: The fourth transistor includes a source connected to the second node, a drain connected to the second voltage, and a gate connected to a direct current voltage source having a voltage value of a gate-off level of the fourth transistor.

5. The pixel according to claim 1, wherein: The fourth transistor is connected between the third node and the second voltage, and a drain current applied from the second transistor flows through the fourth transistor in an off state.

6. The pixel according to claim 5, wherein: The fourth transistor includes a gate and a source connected to the third node, and a drain connected to the second voltage.

7. The pixel according to claim 5, wherein: The fourth transistor includes a source connected to the third node, a drain connected to the second voltage, and a gate connected to a direct current voltage source having a voltage value of a gate-off level of the fourth transistor.

8. The pixel according to claim 1, wherein: The pixel also includes: a seventh transistor including a gate connected to a previous scan line of the corresponding scan line, wherein the seventh transistor is connected between the first node and the second voltage; and an eighth transistor, comprising a gate connected to the previous scan line, wherein the eighth transistor is connected between the anode of the organic light emitting diode and the second voltage, The period during which the second transistor is turned off corresponds to a period after the second transistor is turned off until the organic light emitting diode emits light.

9. The pixel according to claim 1, wherein: The period during which the second transistor is turned off corresponds to a period after the second transistor is turned off until the organic light emitting diode emits light.

10. A pixel, wherein The pixels include: Organic light-emitting diodes; a first transistor including a gate connected to the first node, a source connected to the second node, and a drain connected to the third node; a second transistor including a gate connected to a corresponding scan line, wherein the second transistor is connected between the data line and the second node; a storage capacitor connected between the first node and a first voltage; a third transistor including a gate connected to the corresponding scan line, wherein the third transistor is connected between the first node and the third node; and a fourth transistor including a DC voltage source connected to a voltage value having a gate-off level of the fourth transistor, a source directly connected to the source of the first transistor or the drain of the first transistor, and a drain connected to a second voltage, The period during which the second transistor is turned off corresponds to a period after the second transistor is turned off until the organic light emitting diode emits light.

Images