Integrated Refrigeration Device Based on Peltier Effect and Its Fabrication Method

Abstract

This application discloses an integrated cooling device based on the Peltier effect and its fabrication method. The device includes one or more heat dissipation structures located around a device region. The first heat dissipation structure includes several alternating first N-type deep-doped regions and several first P-type deep-doped regions, several first vias, and a first metal interconnect layer. The several first vias are located at both ends of each of the first N-type deep-doped regions and each of the first P-type deep-doped regions. The first metal interconnect layer connects the several first vias, causing the first heat dissipation structure to form a first S-shaped structure. When the first S-shaped structure is conductive, heat flow in the first N-type deep-doped regions and the first P-type deep-doped regions flows from the side closer to the device region to the side farther away from the device region, thereby achieving heat dissipation of the device region.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor technology, and in particular to an integrated cooling device based on the Peltier effect and its fabrication method. Background Technology

[0002] Chips are often referred to as the "food" of modern industry, serving as crucial foundational components for the information technology sector. The development of fields such as mobile phones, computers, automobiles, industrial control, the Internet of Things, big data, and artificial intelligence all rely heavily on chips. Besides performing their designed functions, chips inevitably generate heat during use. Efficiently dissipating this heat to maintain the internal components of the chip within safe operating temperatures is a critical issue for ensuring product safety and reliability. As chip scale and speed increase, this challenge becomes increasingly apparent, requiring the introduction of innovative ideas and methods.

[0003] The Peltier effect refers to the phenomenon where heat is absorbed or released at the junctions of different conductors when current flows through a circuit composed of different conductors. Existing metal-based Peltier effect designs suffer from weak cooling performance, incompatibility with current semiconductor CMOS processes, and the need for additional cooling modes, causing inconvenience in applications. Therefore, there is a need for a Peltier effect-based cooling device to achieve better process compatibility and cooling performance. Summary of the Invention

[0004] The purpose of this invention is to provide an integrated cooling device based on the Peltier effect and its manufacturing method, which can be applied to chip circuits, is compatible with existing CMOS processes, and improves heat dissipation.

[0005] This application discloses an integrated refrigeration device based on the Peltier effect, comprising:

[0006] One or more first heat dissipation structures are located around the device region, and the first heat dissipation structures include:

[0007] Alternating arrangement of several first N-type deep doped regions and several first P-type deep doped regions;

[0008] A plurality of first vias, wherein the plurality of first vias are respectively located at both ends of each of the first N-type deep doped regions and each of the first P-type deep doped regions; and

[0009] A first metal interconnect layer is provided, which connects the plurality of first vias and causes the first heat dissipation structure to be connected into a first S-shaped structure.

[0010] When the first S-shaped structure is turned on, the heat flow in the first N-type deep doped region and the first P-type deep doped region flows from the side closer to the device region to the side farther away from the device region.

[0011] In a preferred embodiment, both the plurality of first N-type deep doped regions and the plurality of first P-type deep doped regions are rectangular, wherein the side of the rectangle that is not adjacent to the device region is larger than the other side that is adjacent to the device region.

[0012] In a preferred embodiment, the distance between the device region and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

[0013] In a preferred embodiment, a shallow trench is formed between the device region and the first heat dissipation structure for isolation.

[0014] In a preferred embodiment, one or more second heat dissipation structures are further included, the second heat dissipation structures being located on the side of the first heat dissipation structure away from the first heat dissipation structure, the second heat dissipation structures comprising:

[0015] A plurality of second N-type deep doped regions and a plurality of second P-type deep doped regions are arranged alternately in the row and column directions.

[0016] A first polysilicon gate located on each of the second N-type deep doped regions, wherein the first polysilicon gate is N-type deep doped and has no gate insulating layer between it and the second N-type deep doped region;

[0017] A second polysilicon gate located on each of the second P-type deep doped regions, wherein the second polysilicon gate is P-type deep doped and has no gate insulating layer between it and the second P-type deep doped region;

[0018] A plurality of second vias, wherein the plurality of second vias are respectively located above each of the first polysilicon gate and each of the second polysilicon gate; and

[0019] A second metal interconnect layer is provided, which connects the plurality of second vias and causes the second heat dissipation structure to be connected in an S-shaped structure.

[0020] When the second S-shaped structure is turned on, the heat flow in the second N-type deep doped region flows to the first polysilicon gate, and the heat flow in the second P-type deep doped region flows to the second polysilicon gate.

[0021] In a preferred embodiment, the distance between the second heat dissipation structure and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

[0022] This application also discloses a method for manufacturing an integrated refrigeration device based on the Peltier effect, including:

[0023] A plurality of first N-type well regions and a plurality of first P-type well regions are formed alternately on one side of the device region in the semiconductor substrate;

[0024] A first N-type deep-doped region is formed in the first N-type well region;

[0025] A first P-type deep-doped region is formed in the first P-type well region;

[0026] A first via is formed at both ends of each of the first N-type deep doped regions and each of the first P-type deep doped regions; and

[0027] A first metal interconnect layer is formed, the first metal interconnect layer connects the plurality of first vias and connects the plurality of first N-type deep doped regions and the plurality of first P-type deep doped regions into an S-shaped first heat dissipation structure;

[0028] When the first heat dissipation structure is turned on, the heat flow in the first N-type deep doped region and the first P-type deep doped region flows from the side closer to the device region to the side farther away from the device region.

[0029] In a preferred embodiment, the distance between the device region and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

[0030] In a preferred embodiment, the manufacturing method further includes:

[0031] In the semiconductor substrate, a plurality of second N-type well regions and a plurality of second P-type well regions are formed on the side of the first heat dissipation structure away from the first heat dissipation structure, and the plurality of N-type well regions and the plurality of P-type well regions are arranged alternately in the row direction and the column direction.

[0032] A polysilicon gate is formed on each of the second N-type well regions and each of the second P-type well regions, wherein the polysilicon gate has no gate insulating layer between it and the semiconductor substrate;

[0033] A second N-type deep-doped region is formed in each of the second N-type well regions, and the polysilicon gate on each of the second N-type well regions is doped with a first polysilicon gate that is deeply doped with N-type;

[0034] A second P-type deep-doped region is formed in each of the second P-type well regions, and the polysilicon gate on each of the second P-type well regions is doped with a second polysilicon gate that is deeply doped with P-type.

[0035] A second via is formed above each of the first polysilicon gate and each of the second polysilicon gate; and

[0036] A second metal interconnect layer is formed, which connects the plurality of vias and connects the plurality of second N-type deep doped regions and the plurality of second P-type deep doped regions to form an S-shaped second heat dissipation structure.

[0037] When the second heat dissipation structure is turned on, the heat flow in the second N-type deep doped region flows to the first polysilicon gate, and the heat flow in the second P-type deep doped region flows to the second polysilicon gate.

[0038] In a preferred embodiment, the distance between the second heat dissipation structure and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

[0039] In this embodiment, the heat flow in the first heat dissipation structure is horizontal outward from the high-temperature working module to reduce the junction temperature of the high-temperature working module and ensure its normal operation and reliability. The optional second heat dissipation module further dissipates the heat conducted from the first heat dissipation module vertically, improving the overall heat dissipation efficiency. Because the Seebeck coefficient of N+ / P+ in semiconductor materials is relatively large, about 30 times greater than that of metal materials, only 1 / 30 of the current is needed to achieve the same effect as metal-based Peltier devices.

[0040] When this application uses only the first heat dissipation structure, compared to existing CMOS processes, only the design of the pattern in the polysilicon patterning process and P-type and N-type ion implantation processes needs to be modified, without adding additional photolithography processes. Therefore, the implementation method of this application is fully compatible with existing CMOS processes, without introducing special materials and processes, and is sufficiently feasible. When both the first and second heat dissipation structures are used, this application only requires one additional photolithography and etching process to remove the gate insulating layer between the polysilicon gate and the semiconductor substrate, which can further improve the overall heat dissipation effect. Attached Figure Description

[0041] Figure 1 A schematic diagram of an integrated refrigeration device based on the Peltier effect in one embodiment of this application is shown.

[0042] Figure 2 A top view of a first heat dissipation structure according to an embodiment of this application is shown.

[0043] Figure 3 An embodiment of this application is shown. Figure 2 A cross-sectional view of the first heat dissipation structure along the AA' direction.

[0044] Figure 4 An embodiment of this application is shown. Figure 2 A cross-sectional view of the first heat dissipation structure along the BB' direction.

[0045] Figure 5 A top view of a second heat dissipation structure in one embodiment of this application is shown.

[0046] Figure 6 An embodiment of this application is shown. Figure 5 A cross-sectional view of the first heat dissipation structure along the CC' direction.

[0047] Figure 7 An embodiment of this application is shown. Figure 5 A cross-sectional view of the second heat dissipation structure along the DD' direction.

[0048] Figure 8 A flowchart illustrating a method for manufacturing an integrated refrigeration device based on the Peltier effect according to an embodiment of this application is shown.

[0049] Figure 9 A flowchart illustrating a method for manufacturing a second heat dissipation structure according to an embodiment of this application is shown. Detailed Implementation

[0050] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0051] Several different embodiments are given below according to different features of the present invention. Specific elements and arrangements in the present invention are for simplification, but the present invention is not limited to these embodiments. For example, the description of forming a first element on a second element may include embodiments where the first element and the second element are in direct contact, as well as embodiments where additional elements are formed between the first element and the second element, such that the first element and the second element are not in direct contact. Furthermore, for the sake of brevity, the present invention uses repeated element symbols and / or letters in different examples, but this does not imply a specific relationship between the various embodiments and / or structures. It should be understood that when a layer is "on" other layers or substrates, it may mean directly on other layers or substrates, or that other layers are sandwiched between other layers or substrates.

[0052] The first embodiment of this application discloses an integrated refrigeration device based on the Peltier effect. Figure 1A schematic diagram of an integrated cooling device is shown, comprising one or more first heat dissipation structures 100 and one or more second heat dissipation structures 200. The one or more first heat dissipation structures 100 are located around a device region 300 and are used to horizontally transfer heat from the device region 300 outwards. The device region 300 includes high-speed operating devices, and it should be understood that the device region typically generates a large amount of heat due to high-speed operation, causing the device region temperature to rise rapidly. The one or more second heat dissipation structures 200 are located on the side of the first heat dissipation structures 100 away from the device region 300 and are used to vertically transfer heat from the device region 300 outwards. It should be understood that in other embodiments of this application, the cooling device may only have the first heat dissipation structure 100 and not the second heat dissipation structure 200. Similarly, in some embodiments of this application, the cooling device may only have the second heat dissipation structure 200 and not the first heat dissipation structure 100.

[0053] In one embodiment, the distance between the device region 300 and the first heat dissipation structure 100 ranges from 10 micrometers to 20 micrometers, for example, 15 micrometers, 18 micrometers, etc.

[0054] In one embodiment, a shallow trench isolation (STI) is formed between the device region 300 and the first heat dissipation structure 100.

[0055] In one embodiment, the distance between the second heat dissipation structure 200 and the first heat dissipation structure 100 ranges from 10 micrometers to 20 micrometers, for example, 12 micrometers, 16 micrometers, etc.

[0056] Figure 2 A top view of the first heat dissipation structure 100 in one embodiment of this application is shown. Figure 3 yes Figure 2 Cross-sectional view along the AA' direction. Figure 4 yes Figure 2 Cross-sectional view along the BB' direction. (Combined with...) Figures 2 to 4 As shown, the first heat dissipation structure 100 includes: a plurality of first N-type deep doped regions 101, a plurality of first P-type deep doped regions 102, a plurality of first vias 103, and a first metal interconnect layer 104. The plurality of first N-type deep doped regions 101 and the plurality of first P-type deep doped regions 102 are arranged alternately. The plurality of first vias 103 are located at both ends of each of the first N-type deep doped regions 101 and each of the first P-type deep doped regions 102. The first metal interconnect layer 104 connects the plurality of first vias 103, thereby forming a first S-shaped structure with the first heat dissipation structure 100 connected. When the first S-shaped structure is conductive, heat flow within the first N-type deep doped regions 101 and the first P-type deep doped regions 102 flows from the side closer to the device region 300 to the side farther away from the device region 300.

[0057] It should be understood that the first heat dissipation structure 100 is formed in a semiconductor substrate, which also has an N-type well region and a P-type well region. Ion implantation is performed on the N-type well region to form an N-type deep doped region 101, and ion implantation is performed on the P-type well region to form a P-type deep doped region 102.

[0058] In one embodiment, the plurality of first N-type deep doped regions 101 and the plurality of first P-type deep doped regions 102 are both rectangular, and the length of the side of the rectangle that is not adjacent to the device region 300 is greater than the length of the other side that is adjacent to the device region 300.

[0059] refer to Figure 1 As shown, in this embodiment, when the first heat dissipation structure 100 is working, the through-hole 103 is connected to the power supply voltage. Current flows sequentially through the N-type deep doped region 101, the P-type deep doped region 102, and then to the next N-type deep doped region 101, and this cycle repeats. The N-type deep doped region 101 is N-type doped, and the charge carrier is electron (e). - carrier e - The current flows from the side closest to the device region 300 to the side furthest from the device region 300. Next, the current flows from the N-type deep-doped region 101 to the P-type deep-doped region 102. The P-type deep-doped region 102 is P-type doped, and the charge carrier is a hole h. + carrier h + The heat flows from the side closer to the device region 300 to the side farther away from the device region 300. Inside the heat dissipation structure 100, the direction of heat flow is the same as the direction of charge carrier flow. Therefore, the direction of heat flow is from the side closer to the device region 300 to the side farther away from the device region 300, thereby achieving heat dissipation and cooling.

[0060] Figure 5 A top view of the second heat dissipation structure 200 in one embodiment of this application is shown. Figure 6 yes Figure 5 Cross-sectional view along the CC' direction. Figure 7 yes Figure 5 Cross-sectional view along the DD' direction. (Combined with...) Figures 5 to 7 As shown, the second heat dissipation structure 200 includes: a plurality of second N-type deep doped regions 201, a plurality of second P-type deep doped regions 202, a first polysilicon gate 203 located on each of the second N-type deep doped regions 201, a second polysilicon gate 204 located on each of the second P-type deep doped regions 202, a plurality of second vias 205, and a second metal interconnect layer 206.

[0061] The plurality of second N-type deep-doped regions 201 and the plurality of second P-type deep-doped regions 202 are arranged alternately in the row and column directions. The first polysilicon gate 203 is N-type deep-doped and has no gate insulating layer between it and the second N-type deep-doped region 201. The second polysilicon gate 204 is P-type deep-doped and has no gate insulating layer between it and the second P-type deep-doped region 202. The plurality of second vias 205 are respectively located above each of the first polysilicon gate 203 and each of the second polysilicon gate 204. The second metal interconnect layer 206 connects the plurality of second vias 205 and makes the second heat dissipation structure 200 connected into an S-shaped structure. When the second S-shaped structure is turned on, the heat flow in the second N-type deep-doped region flows to the first polysilicon gate, and the heat flow in the second P-type deep-doped region flows to the second polysilicon gate.

[0062] refer to Figure 7 As shown, in this embodiment, when the second heat dissipation structure 200 is working, the through-hole 205 is connected to the power supply voltage. Current flows sequentially through the first polysilicon gate 203, the N-type deep-doped region 201, the P-type deep-doped region 202, and the second polysilicon gate 204, and then to the next first polysilicon gate 203, cycling in this manner. Both the first polysilicon gate 203 and the N-type deep-doped region 201 are N-type doped, and the charge carriers are electrons (e). - carrier e - The current flows from the N-type deep-doped region 201 to the first polysilicon gate 203. Next, the current flows from the N-type deep-doped region 201 to the P-type deep-doped region 202, and then from the P-type deep-doped region 202 to the second polysilicon gate 204. Both the P-type deep-doped region 202 and the second polysilicon gate 204 are P-type doped, and the charge carrier is the hole h. + carrier h + The heat flows from the P-type deep doped region 202 to the second polysilicon gate 204. Inside the heat dissipation structure 200, the direction of heat flow is the same as the direction of carrier flow. Therefore, the direction of heat flow is from the N-type deep doped region 201 to the first polysilicon gate 203, and from the P-type deep doped region 202 to the second polysilicon gate 204, that is, from the inside of the heat dissipation structure to the surface, thereby achieving heat dissipation and cooling.

[0063] According to data from commercial semiconductor cooling chips, a cooling chip with an area of ​​approximately 8mm x 8mm can achieve a temperature difference of 67℃ at its two ends under a current of 2.5A and a voltage of 0.85V. In this application, if the first heat dissipation structure has a cross-sectional length of 1000µm and a thickness of 0.3µm, based on the area, only 0.011mA of current is needed to achieve the cooling effect, requiring less than 0.01mW of power. This negligible power consumption effectively reduces the junction temperature of a critical module.

[0064] The second embodiment of this application discloses a method for manufacturing an integrated refrigeration device based on the Peltier effect. Figure 8 A flowchart illustrating a method for fabricating an integrated refrigeration device based on the Peltier effect is shown, comprising the following steps:

[0065] Step 801, refer to Figure 2 As shown, a plurality of alternating first N-type well regions (not shown) and a plurality of first P-type well regions (not shown) are formed on one side of device region 200 in a semiconductor substrate (not shown). It should be understood that device region 200 may include CMOS devices, and the CMOS devices and the well regions may be formed using standard CMOS processes.

[0066] Step 802, forming in the first N-type well region as follows Figure 2 The first N-type deep doped region 101 is shown.

[0067] Step 803, forming in the first P-type well region as follows Figure 2 The first P-type deep-doped region 102 is shown.

[0068] Step 804: Form a first via 103 at both ends of each of the first N-type deep doped regions 101 and each of the first P-type deep doped regions 102.

[0069] Step 805: A first metal interconnect layer 104 is formed. The first metal interconnect layer 104 connects the plurality of first vias 103 and connects the plurality of first N-type deep doped regions 101 and the plurality of first P-type deep doped regions 102 to form an S-shaped first heat dissipation structure 100.

[0070] In one embodiment, the integrated cooling device based on the Peltier effect further includes a second heat dissipation structure, and the manufacturing method further includes fabricating the second heat dissipation structure 200, as shown in the reference. Figure 9 As shown, the method includes the following steps:

[0071] Step 901, refer to Figure 5As shown, a plurality of second N-type well regions (not shown) and a plurality of second P-type well regions (not shown) are formed on the side of the semiconductor substrate (not shown) away from the first heat dissipation structure. The plurality of N-type well regions and the plurality of P-type well regions are arranged alternately in the row and column directions. It should be understood that both the first and second heat dissipation structures can be fabricated using standard CMOS processes; that is, the second N-type well regions can be formed in the same step as the first N-type well regions, and the second P-type well regions can be formed in the same step as the first P-type well regions.

[0072] Step 902: Forming a polysilicon gate on each of the second N-type well regions and each of the second P-type well regions, wherein the polysilicon gate does not have a gate insulating layer between it and the semiconductor substrate. It should be understood that the polysilicon gate and the polysilicon gate of the device region are formed in this step, and a gate insulating layer is present between the polysilicon gate and the semiconductor substrate.

[0073] Step 903: A second N-type deep doped region is formed in each of the second N-type well regions, and the polysilicon gate on each of the second N-type well regions is doped with a first polysilicon gate 203 that is N-type deep doped.

[0074] Step 904: A second P-type deep doped region is formed in each of the second P-type well regions, and the polysilicon gate on each of the second P-type well regions is doped with a first polysilicon gate 204 that is deeply doped with P-type.

[0075] Step 905: A second via 205 is formed above each of the first polysilicon gate 203 and each of the second polysilicon gate 204.

[0076] Step 906: Form a second metal interconnect layer 206. The second metal interconnect layer 206 connects the plurality of vias 205 and connects the plurality of second N-type deep doped regions and the plurality of second P-type deep doped regions into an S-shaped second heat dissipation structure.

[0077] When the second heat dissipation structure is turned on, the heat flow in the second N-type deep doped region flows to the first polysilicon gate, and the heat flow in the second P-type deep doped region flows to the second polysilicon gate.

[0078] The first embodiment is a product embodiment corresponding to this embodiment. The technical details in the first embodiment can be applied to this embodiment, and the technical details in this embodiment can also be applied to the first embodiment.

[0079] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0080] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

[0081] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result.

Claims

1. An integrated refrigeration device based on the Peltier effect, characterized in that, include: One or more first heat dissipation structures and one or more second heat dissipation structures, wherein the one or more first heat dissipation structures are located around the device area, and the second heat dissipation structures are located on the side of the first heat dissipation structures away from the device area; The first heat dissipation structure includes: Alternating arrangement of several first N-type deep doped regions and several first P-type deep doped regions; A plurality of first vias, wherein the plurality of first vias are respectively located at both ends of each of the first N-type deep doped regions and each of the first P-type deep doped regions; and A first metal interconnect layer is provided, which connects the plurality of first vias and causes the first heat dissipation structure to be connected into a first S-shaped structure. When the first S-shaped structure is turned on, the heat flow in the first N-type deep doped region and the first P-type deep doped region flows from the side closer to the device region to the side farther away from the device region. The second heat dissipation structure includes: A plurality of second N-type deep doped regions and a plurality of second P-type deep doped regions are arranged alternately in the row and column directions. A first polysilicon gate located on each of the second N-type deep doped regions, wherein the first polysilicon gate is N-type deep doped and has no gate insulating layer between it and the second N-type deep doped region; A second polysilicon gate located on each of the second P-type deep doped regions, wherein the second polysilicon gate is P-type deep doped and has no gate insulating layer between it and the second P-type deep doped region; A plurality of second vias, said plurality of second vias being located above each of the first polysilicon gate and each of the second polysilicon gate; and A second metal interconnect layer is provided, which connects the plurality of second vias and causes the second heat dissipation structure to be connected into a second S-shaped structure. When the second S-shaped structure is turned on, the heat flow in the second N-type deep doped region flows to the first polysilicon gate, and the heat flow in the second P-type deep doped region flows to the second polysilicon gate.

2. The integrated refrigeration device based on the Peltier effect according to claim 1, characterized in that, The first N-type deep doped region and the first P-type deep doped region are rectangular, and the side of the rectangle that is not adjacent to the device region is larger than the other side that is adjacent to the device region.

3. The integrated refrigeration device based on the Peltier effect according to claim 1, characterized in that, The distance between the device area and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

4. The integrated refrigeration device based on the Peltier effect according to claim 1, characterized in that, A shallow trench is formed between the device area and the first heat dissipation structure for isolation.

5. The integrated refrigeration device based on the Peltier effect according to claim 1, characterized in that, The distance between the second heat dissipation structure and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

6. A method for manufacturing an integrated refrigeration device based on the Peltier effect, characterized in that, include: A plurality of first N-type well regions and a plurality of first P-type well regions are formed alternately on one side of the device region in the semiconductor substrate; A first N-type deep-doped region is formed in the first N-type well region; A first P-type deep-doped region is formed in the first P-type well region; A first via is formed at both ends of each of the first N-type deep doped regions and each of the first P-type deep doped regions; A first metal interconnect layer is formed, the first metal interconnect layer connects the plurality of first vias and connects the plurality of first N-type deep doped regions and the plurality of first P-type deep doped regions into an S-shaped first heat dissipation structure; wherein, when the first heat dissipation structure is turned on, the heat flow in the first N-type deep doped region and the first P-type deep doped region flows from the side closer to the device region to the side farther away from the device region. In the semiconductor substrate, a plurality of second N-type well regions and a plurality of second P-type well regions are formed on the side of the first heat dissipation structure away from the device region, and the plurality of N-type well regions and the plurality of P-type well regions are arranged alternately in the row direction and the column direction. A polysilicon gate is formed on each of the second N-type well regions and each of the second P-type well regions, wherein the polysilicon gate has no gate insulating layer between it and the semiconductor substrate; A second N-type deep-doped region is formed in each of the second N-type well regions, and the polysilicon gate on each of the second N-type well regions is doped with a first polysilicon gate that is deeply doped with N-type; A second P-type deep-doped region is formed in each of the second P-type well regions, and the polysilicon gate on each of the second P-type well regions is doped with a second polysilicon gate that is deeply doped with P-type. A second via is formed above each of the first polysilicon gate and each of the second polysilicon gate; and A second metal interconnect layer is formed, which connects the plurality of vias and connects the plurality of second N-type deep doped regions and the plurality of second P-type deep doped regions to form an S-shaped second heat dissipation structure; wherein, when the second heat dissipation structure is turned on, the heat flow in the second N-type deep doped region flows to the first polysilicon gate, and the heat flow in the second P-type deep doped region flows to the second polysilicon gate.

7. The manufacturing method according to claim 6, characterized in that, The distance between the device area and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

8. The manufacturing method according to claim 6, characterized in that, The distance between the second heat dissipation structure and the first heat dissipation structure ranges from 10 micrometers to 20 micrometers.

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