Variable resistance memory device and method of forming the same

Abstract

A variable resistance memory device and a method of forming the same are disclosed. The variable resistance memory (RRAM) device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask, and a high work function sidewall portion. The bottom electrode, the resistive material layer, the high work function layer, the top electrode, and the hard mask are sequentially stacked on a substrate. The high work function sidewall portion covers sidewalls of the top electrode and sidewalls of the hard mask, thereby forming a variable resistance memory cell.

Description

TECHNICAL FIELD

[0001] The present invention relates to a resistive random-access memory device and a method of forming the same, and more particularly to a resistive random-access memory device with a high work function sidewall portion and a method of forming the same. BACKGROUND

[0002] In a circuit of a semiconductor manufacturing process, a basic resistive random-access memory is composed of a bottom electrode, a top electrode, and a transition metal oxide (TMO) layer between the bottom electrode and the top electrode. The main operating principle is that the resistance of the TMO layer changes with the applied bias voltage. The stored value is determined by the resistance of the TMO layer. SUMMARY

[0003] The present invention provides a resistive random-access memory device and a method of forming the same. A high work function sidewall portion is formed on the sidewall of a top electrode and the sidewall of a hard mask to directly connect a via above and prevent open circuit.

[0004] The present invention provides a resistive random-access memory device. The device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask, and a high work function sidewall portion. The bottom electrode, the resistive material layer, the high work function layer, the top electrode, and the hard mask are sequentially stacked on a substrate. The high work function sidewall portion covers the sidewall of the top electrode and the sidewall of the hard mask, thereby forming a resistive random-access memory cell.

[0005] The present invention provides a method of forming a resistive random-access memory device. The method includes the following steps. First, a bottom electrode layer, a resistive layer, a high work function material layer, a top electrode layer, and a hard mask layer are sequentially deposited on a substrate. Then, the hard mask layer and the top electrode layer are patterned to form a top electrode and a hard mask, and expose the high work function material layer. Next, the high work function material layer is patterned to form a high work function layer and a high work function sidewall portion covering the sidewall of the top electrode and the sidewall of the hard mask. Finally, the resistive layer and the bottom electrode layer are patterned to form a resistive material layer and a bottom electrode, thereby forming a resistive random-access memory cell.

[0006] Based on the above, the present application provides a variable resistance memory device and a forming method thereof, which sequentially stacks a bottom electrode, a resistance material layer, a high work function layer, a top electrode and a hard mask on a substrate, and forms a high work function sidewall portion on the sidewall of the top electrode and the sidewall of the hard mask, so that when a via hole above the hard mask fails to directly contact the top electrode, the high work function sidewall portion can be physically contacted through the via hole to prevent open circuit from occurring. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A cross-sectional schematic diagram of a method for forming a variable resistance memory device in a preferred embodiment of the present application;

[0008] Figure 2 A cross-sectional schematic diagram of a method for forming a variable resistance memory device in a preferred embodiment of the present application;

[0009] Figure 3 A cross-sectional schematic diagram of a method for forming a variable resistance memory device in a preferred embodiment of the present application;

[0010] Figure 4 A cross-sectional schematic diagram of a method for forming a variable resistance memory device in a preferred embodiment of the present application;

[0011] Figure 5 A cross-sectional schematic diagram of a method for forming a variable resistance memory device in a preferred embodiment of the present application;

[0012] Figure 6 A cross-sectional schematic diagram of a method for forming a variable resistance memory device in a preferred embodiment of the present application.

[0013] Figure 7 A cross-sectional schematic diagram of a method for forming a variable resistance memory device in a preferred embodiment of the present application;

[0014] Figure 8 A cross-sectional schematic diagram of a variable resistance memory device in another preferred embodiment of the present application.

[0015] Explanation of main element symbols

[0016] 10: conductive structure

[0017] 110: dielectric layer

[0018] 120: bottom electrode layer

[0019] 120a: bottom electrode

[0020] 130: resistance layer

[0021] 130a: resistance material layer

[0022] 140: High work function material layer

[0023] 140a: High-power function layer

[0024] 140b, 240: Sidewall portion of high work function

[0025] 140ba: Bottom

[0026] 150: Top electrode layer

[0027] 150a: Top electrode

[0028] 160: Hard mask layer

[0029] 160a: Hard mask

[0030] 160AA, 170AA: Top

[0031] 170: Interstitial wall

[0032] 180: Through hole

[0033] P: Photoresist

[0034] S1, S2, S3, S4, S5, S6: Sidewall

[0035] U: Variable resistive memory unit

[0036] t: thickness Detailed Implementation

[0037] Figures 1-7 A cross-sectional schematic diagram illustrating a method for forming a variable resistive memory device according to a preferred embodiment of the present invention is shown. Figure 1 As shown, a dielectric layer 110 is located on a substrate (not shown). In this embodiment, the dielectric layer 110 is an oxide layer, but the invention is not limited thereto. The substrate (not shown) is, for example, a silicon substrate, a silicon-containing substrate (e.g., SiC), a group III-V substrate (e.g., GaN), a group III-V silicon-coated substrate (e.g., GaN-on-silicon), a graphene-on-silicon substrate, a silicon-on-insulator (SOI) substrate, or a substrate containing an epitaxial layer, etc., such semiconductor substrates. In the illustration of this embodiment, only the variable resistive memory region is shown. A conductive structure 10 is located in the dielectric layer 110, wherein the conductive structure 10 may be, for example, tungsten or copper, for electrically connecting the variable resistive memory cell above.

[0038] like Figure 1As shown, a bottom electrode layer 120, a resistive layer 130, a high work function material layer 140, a top electrode layer 150 and a hard mask layer 160 are sequentially deposited on the dielectric layer 110. A photoresist P is formed to pattern the underlying material layers. In this embodiment, the bottom electrode layer 120 and the top electrode layer 150 comprise tantalum nitride or titanium nitride, while the resistive layer 130 comprises a metal oxide layer, and the metal oxide layer preferably can comprise hafnium oxide or tantalum oxide, but the present application is not limited thereto. In a preferred embodiment, the high work function material layer 140 comprises iridium, for subsequent direct sputtering to form a high work function sidewall portion, but the present application is not limited thereto. In this embodiment, the hard mask layer 160 can comprise an oxide hard mask.

[0039] As shown, the hard mask layer 160 and the top electrode layer 150 are patterned to form a top electrode 150a and a hard mask 160a, and expose the high work function material layer 140. In detail, the hard mask layer 160 can be first patterned with the photoresist P to form the hard mask 160a, and expose the top electrode layer 150, as shown. Figures 1-3 As shown, the hard mask layer 160 and the top electrode layer 150 are patterned to form a top electrode 150a and a hard mask 160a, and expose the high work function material layer 140. In detail, the hard mask layer 160 can be first patterned with the photoresist P to form the hard mask 160a, and expose the top electrode layer 150, as shown. Figure 2 As shown, the hard mask layer 160 and the top electrode layer 150 are patterned to form a top electrode 150a and a hard mask 160a, and expose the high work function material layer 140. In detail, the hard mask layer 160 can be first patterned with the photoresist P to form the hard mask 160a, and expose the top electrode layer 150, as shown. Figure 3 As shown, the hard mask layer 160 and the top electrode layer 150 are patterned to form a top electrode 150a and a hard mask 160a, and expose the high work function material layer 140. In detail, the hard mask layer 160 can be first patterned with the photoresist P to form the hard mask 160a, and expose the top electrode layer 150, as shown.

[0040] As shown, the hard mask layer 160 and the top electrode layer 150 are patterned to form a top electrode 150a and a hard mask 160a, and expose the high work function material layer 140. In detail, the hard mask layer 160 can be first patterned with the photoresist P to form the hard mask 160a, and expose the top electrode layer 150, as shown. Figure 4As shown, a high work function material layer 140 is patterned to form a high work function layer 140a, and a high work function sidewall portion 140b is formed to cover the sidewall S1 of the top electrode 150a and the sidewall S2 of the hard mask 160a. In this embodiment, when patterning the high work function material layer 140, it is simultaneously re-sputtered to form the high work function sidewall portion 140b. Therefore, the high work function sidewall portion 140b and the high work function layer 140a contain the same material. In a preferred embodiment, the high work function sidewall portion 140b and the high work function layer 140a contain iridium, which simultaneously functions as a barrier and an electrode. Since in this embodiment, the high work function sidewall portion 140b is formed by re-sputtering the high work function material layer 140 during etching, the high work function sidewall portion 140b and the high work function layer 140a are integrally formed. Furthermore, the high work function sidewall portion 140b is directly located on the high work function material layer 140 due to re-sputtering, and in this embodiment, the high work function sidewall portion 140b and the high work function layer 140a form a U-shaped cross-sectional structure, but the present invention is not limited thereto. The high work function sidewall portion 140b is attached to the sidewall S1 of the top electrode 150a and the sidewall S2 of the hard mask 160a, so the cross-sectional structure of the formed high work function sidewall portion 140b and the high work function layer 140a depends on the cross-sectional structure of the top electrode 150a and the hard mask 160a.

[0041] like Figures 4-5 As shown, the resistive layer 130 and the bottom electrode layer 120 are further patterned to form a resistive material layer 130a and a bottom electrode 120a, thereby constituting a variable resistive memory cell U. In this embodiment, the sidewalls S3 of the resistive material layer 130a and S4 of the bottom electrode 120a are etched to align with the sidewalls S5 of the high work function layer 140a and S6 of the high work function sidewall portion 140b.

[0042] In the preferred embodiments described above, Figures 1-5 The process is performed in-situ, meaning that the hard mask layer 160, top electrode layer 150, high work function material layer 140, resistive layer 130, and bottom electrode layer 120 are patterned in-situ to simplify the fabrication process and reduce contamination. In the patterned fabrication process, process parameters such as cavity pressure and machine bias can be individually adjusted within the same fabrication cavity according to the fabrication process sequence to achieve the preset requirements of each layer.

[0043] In the fabrication process of etching the high work function material layer 140 and re-sputtering the high work function material layer 140 to form the high work function sidewall portion 140b, the thickness of the formed high work function sidewall portion 140b can be changed by adjusting the sputtering angle and power. For example, Figure 8 A cross-sectional schematic diagram of a variable resistive memory device according to another preferred embodiment of the present invention is shown. Figure 8 As shown, the present invention can increase the thickness t of the high work function sidewall portion 240 by adjusting the sputtering angle and power, thereby increasing the contact area with the subsequent through hole formed above and reducing the contact resistance, but the present invention is not limited thereto.

[0044] The following is a simplified description of the invention; the explanation continues below. Figure 5 The steps described in this embodiment are as follows. Figure 6 As shown, a spacer wall 170 is formed, covering the sidewall S4 of the bottom electrode 120a, the sidewall S3 of the resistive material layer 130a, the sidewall S5 of the high work function layer 140a, and the sidewall S6 of the high work function sidewall portion 140b. In this embodiment, the spacer wall 170 comprises a silicon nitride spacer wall, but the spacer wall 170 can be other single-layer or multi-layer structures. In a preferred embodiment, the top 170a of the spacer wall 170 overlaps the bottom 140ba of the high work function sidewall portion 140b to avoid leakage.

[0045] like Figure 7 As shown, a through-hole 180 is formed, physically contacting the high work function sidewall portion 140b. This invention prevents the through-hole 180 from physically contacting the hard mask 160a but not penetrating through the hard mask 160a to contact the top electrode 150a. Instead, it allows for electrical connection to the top electrode 150a via the high work function sidewall portion 140b, thus preventing open circuits in the variable resistive memory cell U. The through-hole 180 penetrates at least a portion of a top portion 160aa of the hard mask 160a.

[0046] In summary, the present invention provides a variable resistivity memory device and a method for forming the same, wherein a bottom electrode, a resistive material layer, a high work function layer, a top electrode, and a hard mask are sequentially stacked on a substrate, and a high work function sidewall portion is formed located on the sidewall of the top electrode and the sidewall of the hard mask. Therefore, when a via above the hard mask fails to directly contact the top electrode, the present invention can prevent open circuits by physically contacting the high work function sidewall portion through the via.

[0047] Preferably, the present application can re-sputter a high work function material layer to form a high work function layer when patterning the high work function material layer. More preferably, the present application can in-situ pattern a hard mask layer, a top electrode layer, a high work function material layer, a resistive layer, and a bottom electrode layer to form a bottom electrode, a resistive material layer, a high work function layer, a top electrode, and a hard mask in sequence. In this way, the manufacturing process can be simplified and the manufacturing process contamination can be reduced.

[0048] The above descriptions are only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be covered by the scope of the present application.

Claims

1. A resistive random-access memory (RRAM) device, comprising: a bottom electrode, a resistive material layer, a high work function layer, a top electrode, and a hard mask sequentially stacked on a substrate; and high work function sidewall portions covering sidewalls of the top electrode and sidewalls of the hard mask, thereby forming a RRAM cell, wherein the high work function sidewall portions and the high work function layer comprise iridium, and the high work function sidewall portions and the high work function layer are monolithic.

2. The RRAM device of claim 1, wherein the bottom electrode and the top electrode comprise tantalum nitride or titanium nitride.

3. The RRAM device of claim 1, wherein the high work function sidewall portions are directly on the high work function layer.

4. The RRAM device of claim 3, wherein the high work function sidewall portions and the high work function layer comprise the same material.

5. The RRAM device of claim 4, wherein the high work function sidewall portions and the high work function layer form a U-shaped cross-section.

6. The RRAM device of claim 1, further comprising: a via physically contacting the high work function sidewall portions, wherein the via physically contacts a top portion of the hard mask.

7. The RRAM device of claim 6, wherein the via passes through at least a portion of the top portion of the hard mask.

8. The RRAM device of claim 1, further comprising: a spacer covering sidewalls of the bottom electrode, the resistive material layer, and the high work function layer.

9. The RRAM device of claim 8, wherein the spacer comprises a silicon nitride spacer.

10. The RRAM device of claim 8, wherein a top portion of the spacer overlaps a bottom portion of the high work function sidewall portions.

11. The RRAM device of claim 1, wherein the resistive material layer comprises a metal oxide layer.

12. The RRAM device of claim 11, wherein the metal oxide layer comprises tantalum oxide or hafnium oxide.

13. The RRAM device of claim 1, wherein the hard mask comprises an oxide hard mask.

14. A method of forming a resistive random-access memory (RRAM) device, comprising: sequentially depositing a bottom electrode layer, a resistive layer, a high work function material layer, a top electrode layer, and a hard mask layer on a substrate; patterning the hard mask layer and the top electrode layer to form a top electrode and a hard mask, and to expose the high work function material layer; patterning the high work function material layer to form a high work function layer, and to form high work function sidewall portions covering sidewalls of the top electrode and sidewalls of the hard mask; and patterning the resistive layer and the bottom electrode layer to form a resistive material layer and a bottom electrode, thereby forming a RRAM cell, wherein the high work function sidewall portions and the high work function layer comprise iridium.

15. The method of claim 14, wherein the hard mask layer, the top electrode layer, the high work function material layer, the resistive layer, and the bottom electrode layer are patterned in-situ.

16. The method of claim 14, wherein upon patterning the high work function material layer, the high work function material layer is re-sputtered to form the high work function sidewall portions.

17. The method of claim 14, further comprising: forming a spacer covering sidewalls of the bottom electrode, the resistive material layer, and the high work function layer. ​

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