D-band one-dimensional DBF-AIP microsystem architecture

Abstract

The application provides a D-band one-dimensional DBF-AIP microsystem architecture, comprising a quartz substrate, an on-chip antenna arranged on the upper surface of the quartz substrate, an RFIC chip arranged on the lower surface of the quartz substrate, a microwave board arranged below the quartz substrate, and BGA solder balls for connecting the quartz substrate and the microwave board. The D-band one-dimensional DBF-AIP microsystem architecture provided by the application maximally shortens the signal transmission distance, reduces the parasitic parameters, and obtains better performance, and meanwhile, the D-band one-dimensional DBF-AIP microsystem architecture is small in size, light in weight, and suitable for large-scale integration.

Description

Technical Field

[0001] This invention relates to the field of packaged antenna technology, and more specifically to a D-band one-dimensional DBF-AIP microsystem architecture. Background Technology

[0002] Antenna in Package (AIP) technology aligns with the increasing integration of silicon-based CMOS processes, providing excellent antenna solutions for system-on-a-chip (SoC) wireless applications. Digital Beamforming (DBF) technology is widely used in automotive radar, 5G communications, and other fields. A one-dimensional DBF AiP microsystem sits between the electromagnetic wave signal and digital signal processing unit. Its receiver link's RF input port is the packaged antenna, and its output port is an ADC converter. Its transmitter link's input port is the digital signal input to the DAC, playing a crucial role in bridging the processing of received and transmitted signals. When the one-dimensional DBF AiP microsystem's receiver link is active, the electromagnetic wave signal received by the packaged antenna is amplified with low noise, down-converted, and output as an IQ signal to the ADC. The ADC samples the signal and converts the RF analog signal into a digital signal for output. When the one-dimensional DBF AiP microsystem's transmitter link is active, the digital signal received by the DAC is converted into an analog IQ signal and up-converted to a specific frequency band. The amplified RF signal is then radiated through the packaged antenna. One-dimensional DBF AiP with multiple channels, high integration, high performance, and high consistency plays a decisive role in realizing large-scale, miniaturized, and lightweight phased array systems. How to achieve multiple channels, high integration, and high performance in one-dimensional DBF AiP microsystems is of paramount importance. Summary of the Invention

[0003] The present invention aims to overcome the shortcomings of the prior art and provide a D-band one-dimensional DBF AiP microsystem product that supports FMCW system, transmit and receive arrays, and integrates a quadruple frequency multiplier, 8 receive channels and 8 transmit channels. Each transmit channel includes an on-chip antenna, a quadrature modulation upconverter and dual 14-bit DACs, and each receive channel includes an on-chip antenna, a quadrature demodulation downconverter and dual 14-bit ADCs.

[0004] This invention provides a D-band one-dimensional DBF-AIP microsystem architecture, including a quartz substrate, an on-chip antenna disposed on the upper surface of the quartz substrate, an RFIC chip disposed on the lower surface of the quartz substrate, a microwave board disposed below the quartz substrate, and BGA solder balls for connecting the quartz substrate and the microwave board.

[0005] The RFIC chip includes an eight-channel D-band receiver chip, an eight-channel D-band transmitter chip, four ADC chips connected to the eight-channel D-band receiver chip, and four DAC chips connected to the eight-channel D-band transmitter chip.

[0006] The quartz substrate integrates power supply, grounding and signal transmission functions; the quartz substrate includes, from top to bottom, a radiating slit layer, a first GND layer, a power-control layer, a second GND layer, a power divider network layer and a quartz base cavity disposed between the radiating slit layer and the first GND layer.

[0007] The microwave board integrates peripheral circuits, power supply, and control.

[0008] In a preferred embodiment of the D-band one-dimensional DBF-AIP microsystem architecture described in this invention, the RFIC chip further includes ANT1 antenna, ANT2 antenna, ANT3 antenna, ANT4 antenna, ANT5 antenna, ANT6 antenna, ANT7 antenna, and ANT8 antenna connected to the D-band eight-channel receiver chip, and ANT9 antenna, ANT10 antenna, ANT11 antenna, ANT12 antenna, ANT13 antenna, ANT14 antenna, ANT15 antenna, and ANT16 antenna connected to the D-band eight-channel transmitter chip.

[0009] ANT1, ANT2, ANT3, ANT4, ANT5, ANT6, ANT7, and ANT8 antennas are used to receive electromagnetic wave signals.

[0010] The ANT9, ANT10, ANT11, ANT12, ANT13, ANT14, ANT15, and ANT16 antennas are used to radiate D-band radio frequency signals into space.

[0011] The present invention discloses a D-band one-dimensional DBF-AIP microsystem architecture. In a preferred embodiment, the D-band eight-channel receiver chip includes a low-noise amplifier, a quadrature demodulation downconverter, a bandpass filter, and a balun. The D-band eight-channel receiver chip is used to amplify electromagnetic wave signals through the low-noise amplifier, convert them through the quadrature demodulation downconverter, and generate analog signals in the form of IQ signals after filtering through the bandpass filter and balun. The analog signals are then transmitted to the ADC chip.

[0012] In the preferred embodiment of the D-band one-dimensional DBF-AIP microsystem architecture described in this invention, the ADC chip is used to process analog signals into digital signals that meet the SERDES protocol, and then transmits the digital signals to the DAC chip.

[0013] In the preferred embodiment of the D-band one-dimensional DBF-AIP microsystem architecture described in this invention, the DAC chip is used to process digital signals into analog differential signals and transmit the analog differential signals to the D-band eight-channel transmitter chip.

[0014] The present invention discloses a D-band one-dimensional DBF-AIP microsystem architecture. In a preferred embodiment, the D-band eight-channel transmitter chip includes a balun, an image rejection filter, a quadrature demodulation downconverter, and a power amplifier. The D-band eight-channel transmitter chip is used to amplify the analog differential signal through the balun, image rejection filter, quadrature demodulation downconverter, and power amplifier to generate a D-band radio frequency signal, and then radiates the D-band radio frequency signal to the ANT9, ANT10, ANT11, ANT12, ANT13, ANT14, ANT15, and ANT16 antennas.

[0015] In the D-band one-dimensional DBF-AIP microsystem architecture described in this invention, the ADC chip is preferably a four-channel chip.

[0016] The present invention discloses a D-band one-dimensional DBF-AIP microsystem architecture, in which, as a preferred embodiment, the ADC chip includes:

[0017] SERDOUT± interface: indicates the output of digital signals that meet the SERDES protocol;

[0018] SERDIN± interface: indicates the input of digital signals that meet the SERDES protocol;

[0019] SDI interface: Indicates the chip's SPI input;

[0020] SDO interface: Indicates that the chip outputs SPI;

[0021] SCLK interface: Indicates the chip's SPI clock;

[0022] SYNC interface: Indicates SPI chip select for the RF chip;

[0023] CLK interface: Indicates the input clock;

[0024] CSB interface: Indicates digital chip select;

[0025] VREF interface: Indicates the internal / external reference input selection signal.

[0026] In the preferred embodiment of the D-band one-dimensional DBF-AIP microsystem architecture described in this invention, the DAC chip has four channels.

[0027] The present invention discloses a D-band one-dimensional DBF-AIP microsystem architecture, in which, as a preferred embodiment, the DAC chip includes:

[0028] SYNCOUT± interface: indicates the output of analog differential signals;

[0029] SYSCIN± interface: Indicates the input of analog differential signals;

[0030] SYSREF interface: Represents the reference signal for the differential system;

[0031] SDI interface: Indicates the chip's SPI input;

[0032] SDO interface: Indicates that the chip outputs SPI;

[0033] SCLK interface: Indicates the chip's SPI clock;

[0034] SYNC interface: Indicates SPI chip select for the RF chip;

[0035] CLK interface: Indicates the input clock;

[0036] CSB interface: Indicates digital chip select;

[0037] VREF interface: Indicates the internal / external reference input selection signal.

[0038] This invention utilizes a flexible vertical interconnect structure and a well-designed layout of input / output ports and transmission lines. The receiving array antenna, transmitting array antenna, D-band transmitting chip, D-band receiving chip, ADC, and DAC are distributed on both sides of the one-dimensional DBFAiP microsystem. It integrates circuits such as D-band on-chip antenna, D-band low-noise amplifier, quadrupler, downconverter, ADC, DAC, upconverter, D-band power amplifier, and D-band on-chip antenna to achieve functions such as receiving, amplifying, downconverting, high sampling rate sampling and transmission of electromagnetic wave signals, converting digital signals into analog signals, amplifying, and radiating electromagnetic wave signals. Compared with discrete components, the product has a higher degree of integration.

[0039] This invention achieves high integration of a one-dimensional DBF AiP microsystem based on three-dimensional heterogeneous integration technology. The one-dimensional DBF AiP microsystem mainly consists of a quartz substrate integrating an on-chip antenna, power divider network, flip-chip RF chip, digital chip ports, and power supply, control, and data transmission ports for the microsystem and microwave; a D-band eight-channel transmitter chip integrating a quadrature modulation upconverter and power amplifier; a D-band eight-channel receiver chip integrating a low-noise amplifier and a quadrature demodulation downconverter; a 14-bit high sampling rate ADC and DAC; filters; and a differential-to-single-ended balun. The on-chip antenna is located on the front of the quartz substrate, while the D-band eight-channel transmitter chip, D-band eight-channel receiver chip, ADC, and DAC are in flip-chip form, and the balun and filter are in IPD form on the back of the quartz substrate. This solution minimizes signal transmission distance and reduces parasitic parameters in the D-band, achieving superior performance, while also being small in size, lightweight, and suitable for large-scale integration.

[0040] In this invention, all channels (control, power supply, and digital signals) are connected to the microwave board via BGA ball-mounting. This eliminates inconsistencies caused by gold wire length and gold wire arch height in the gold wire bonding process, while also achieving higher integration, shorter transmission paths, and better performance.

[0041] This invention employs a zero-IF (intermediate frequency) scheme, enabling D-band electromagnetic wave signals to be received by an on-chip antenna, amplified by a D-band low-noise amplifier, down-converted via quadrature demodulation, sampled and converted into digital signals by an ADC, and output through a SerDes interface. Simultaneously, digital signals are received via the SerDes interface, converted to analog-to-digital by a DAC, suppressed by a filter, up-converted by quadrature modulation, amplified by a power amplifier, and radiated by the on-chip antenna. The zero-IF scheme is compact, further improving the integration of microsystem products.

[0042] This invention integrates an eight-channel D-band transmitter chip with a quadruple frequency multiplier and eight transmit channels, each channel containing a quadrature modulation upconverter; and an eight-channel D-band receiver chip with a quadruple frequency multiplier and eight receive channels, each channel containing a quadrature demodulation downconverter. A single D-band receiver chip achieves functions such as receiving D-band RF signals, low-noise amplification, and downconversion, while a single D-band transmitter chip achieves functions such as upconversion, power amplification, and radiation of low-frequency RF signals, laying the foundation for three-dimensional heterogeneous integration of microsystem products.

[0043] Due to limitations in system architecture, the size of the RF transceiver module is strictly limited. This invention, based on advanced silicon-based RF integrated circuit processes such as CMOS and microsystem integration technology, mounts a WLCSP-packaged D-band eight-channel transmitter chip, a D-band eight-channel receiver chip, an ADC chip, and a DAC chip onto the back of a multilayer quartz substrate using a flip-chip configuration. An on-chip antenna is placed on the front of the quartz substrate, and TGV vertical interconnect technology enables alternating signal transmission between the front and back sides of the quartz substrate, achieving miniaturization and high integration of the DBF AiP product.

[0044] The advantages of this invention compared to existing technologies are as follows: This invention utilizes three-dimensional heterogeneous integration technology to vertically stack devices, significantly reducing the XY dimensions of the microsystem; TGV vertical interconnect technology is employed to achieve multi-level, multi-channel transmission of RF signals, power supply, and control signals within the quartz substrate; WLCSP-packaged D-band eight-channel transmitter chip, D-band eight-channel receiver chip, four-channel ADC chip, and four-channel DAC chip are assembled onto the quartz substrate using flip-chip technology, significantly reducing the Z-axis dimensions of the microsystem product; TGV vertical interconnect technology shortens the signal transmission path, reduces parasitic parameters, and improves product performance; the D-band eight-channel transmitter chip, D-band eight-channel receiver chip, four-channel ADC chip, and four-channel DAC chip all integrate multiple functions to achieve the reception and transmission of D-band RF signals. Attached Figure Description

[0045] Figure 1 This is a diagram of the architecture of a one-dimensional DBF-AIP microsystem in the D-band.

[0046] Figure 2 A top view of a one-dimensional DBF-AIP microsystem architecture in the D-band;

[0047] Figure 3 This is a block diagram illustrating the principle of a one-dimensional DBF-AIP microsystem architecture in the D-band.

[0048] Figure 4 This is a diagram of a quartz substrate for a one-dimensional DBF-AIP microsystem architecture in the D-band. Detailed Implementation

[0049] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0050] Example 1

[0051] like Figure 1 As shown, a D-band one-dimensional DBF-AIP microsystem architecture includes a quartz substrate, an on-chip antenna disposed on the upper surface of the quartz substrate, an RFIC chip disposed on the lower surface of the quartz substrate, a microwave board disposed below the quartz substrate, and BGA solder balls for connecting the quartz substrate and the microwave board.

[0052] like Figures 2-3As shown, the RFIC chip includes an eight-channel D-band receiver chip, an eight-channel D-band transmitter chip, four ADC chips connected to the eight-channel D-band receiver chip, four DAC chips connected to the eight-channel D-band transmitter chip, and ANT1, ANT2, ANT3, ANT4, ANT5, ANT6, ANT7, and ANT8 antennas connected to the eight-channel D-band receiver chip, and ANT9, ANT10, ANT11, ANT12, ANT13, ANT14, ANT15, and ANT16 antennas connected to the eight-channel D-band transmitter chip. ANT1, ANT2, ANT3, ANT4, ANT5, ANT6, ANT7, and ANT8 antennas are used to receive electromagnetic wave signals. The eight-channel D-band receiver chip includes a low-noise amplifier, a quadrature demodulation downconverter, a bandpass filter, and a balun. The eight-channel D-band receiver chip amplifies the electromagnetic wave signal using the low-noise amplifier, converts it using the quadrature demodulation downconverter, and outputs it as an IQ signal. A bandpass filter and a balun are used to filter and generate an analog signal, which is then transmitted to an ADC chip. The ADC chip processes the analog signal into a digital signal that meets the SERDES protocol and transmits the digital signal to a DAC chip. The DAC chip processes the digital signal into an analog differential signal and transmits the analog differential signal to an eight-channel D-band transmitter chip. The eight-channel D-band transmitter chip includes a balun, an image rejection filter, a quadrature demodulation downconverter, and a power amplifier. It amplifies the analog differential signal through the balun, image rejection filter, quadrature demodulation downconverter, and power amplifier to generate a D-band radio frequency signal, which is then radiated to ANT9, ANT10, ANT11, ANT12, ANT13, ANT14, ANT15, and ANT16 antennas. The ANT9, ANT10, ANT11, ANT12, ANT13, ANT14, ANT15, and ANT16 antennas radiate the D-band radio frequency signal into space.

[0053] The ADC chip is a four-channel chip, including:

[0054] SERDOUT± interface: indicates the output of digital signals that meet the SERDES protocol;

[0055] SERDIN± interface: indicates the input of digital signals that meet the SERDES protocol;

[0056] SDI interface: Indicates the chip's SPI input;

[0057] SDO interface: Indicates that the chip outputs SPI;

[0058] SCLK interface: Indicates the chip's SPI clock;

[0059] SYNC interface: Indicates SPI chip select for the RF chip;

[0060] CLK interface: Indicates the input clock;

[0061] CSB interface: Indicates digital chip select;

[0062] VREF interface: Indicates internal / external reference input selection signal;

[0063] The DAC chip is a four-channel chip, including:

[0064] SYNCOUT± interface: indicates the output of analog differential signals;

[0065] SYSCIN± interface: Indicates the input of analog differential signals;

[0066] SYSREF interface: Represents the reference signal for the differential system;

[0067] SDI interface: Indicates the chip's SPI input;

[0068] SDO interface: Indicates that the chip outputs SPI;

[0069] SCLK interface: Indicates the chip's SPI clock;

[0070] SYNC interface: Indicates SPI chip select for the RF chip;

[0071] CLK interface: Indicates the input clock;

[0072] CSB interface: Indicates digital chip select;

[0073] VREF interface: Indicates internal / external reference input selection signal;

[0074] like Figure 4 As shown, the quartz substrate integrates power supply, grounding and signal transmission functions; the quartz substrate includes, from top to bottom, a radiating slit layer M1, a first GND layer M2, a power-control layer M3, a second GND layer M4, a power divider network layer M5, and a quartz base cavity disposed between the radiating slit layer and the first GND layer.

[0075] The microwave board integrates peripheral circuits, power supply, and control.

[0076] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A one-dimensional DBF-AIP microsystem architecture for the D-band, characterized in that: The system includes a quartz substrate, an on-chip antenna disposed on the upper surface of the quartz substrate, an RFIC chip disposed on the lower surface of the quartz substrate, a microwave board disposed below the quartz substrate, and BGA solder balls for connecting the quartz substrate and the microwave board. The microsystem architecture uses a zero-IF scheme with the RFIC chip. The RFIC chip includes an eight-channel D-band receiver chip, an eight-channel D-band transmitter chip, four ADC chips connected to the eight-channel D-band receiver chip, and four DAC chips connected to the eight-channel D-band transmitter chip. The ADC chips and DAC chips are mounted on the back of the quartz substrate in a flip-chip manner, and the signals are transmitted alternately on both sides of the quartz substrate through TGV vertical interconnection. The control signals, power supply signals, and digital signals of each channel are all connected to the microwave board through BGA ball bearings. The D-band eight-channel receiver chip includes a quadruple frequency multiplier and eight receiving channels. Each receiving channel includes a low-noise amplifier, a quadrature demodulation downconverter, a bandpass filter, and a balun. The D-band eight-channel receiver chip amplifies the electromagnetic wave signal through the low-noise amplifier, converts it through the quadrature demodulation downconverter, and generates an analog signal in IQ signal form after filtering through the bandpass filter and balun. The analog signal is then transmitted to the ADC chip. The D-band eight-channel transmitter chip includes a quadruple frequency multiplier and eight transmitter channels. Each transmitter channel includes a balun, an image rejection filter, a quadrature demodulation downconverter, and a power amplifier. The D-band eight-channel transmitter chip amplifies the analog differential signal through the balun, the image rejection filter, the quadrature demodulation downconverter, and the power amplifier to generate a D-band radio frequency signal. The quartz substrate integrates power supply, grounding and signal transmission functions; the quartz substrate includes, from top to bottom, a radiating slit layer, a first GND layer, a power-control layer, a second GND layer, a power divider network layer and a quartz cavity disposed between the radiating slit layer and the first GND layer.

2. The D-band one-dimensional DBF-AIP microsystem architecture according to claim 1, characterized in that: The RFIC chip also includes ANT1 antenna, ANT2 antenna, ANT3 antenna, ANT4 antenna, ANT5 antenna, ANT6 antenna, ANT7 antenna, and ANT8 antenna connected to the D-band eight-channel receiver chip, and ANT9 antenna, ANT10 antenna, ANT11 antenna, ANT12 antenna, ANT13 antenna, ANT14 antenna, ANT15 antenna, and ANT16 antenna connected to the D-band eight-channel transmitter chip. The ANT1 antenna, ANT2 antenna, ANT3 antenna, ANT4 antenna, ANT5 antenna, ANT6 antenna, ANT7 antenna and ANT8 antenna are used to receive electromagnetic wave signals; The ANT9, ANT10, ANT11, ANT12, ANT13, ANT14, ANT15, and ANT16 antennas are used to radiate D-band radio frequency signals into space. The microwave board integrates peripheral circuits, power supply, and control.

3. The D-band one-dimensional DBF-AIP microsystem architecture according to claim 2, characterized in that: The ADC chip is used to process the analog signal into a digital signal that meets the SERDES protocol, and to transmit the digital signal to the DAC chip.

4. The D-band one-dimensional DBF-AIP microsystem architecture according to claim 3, characterized in that: The DAC chip is used to process the digital signal into an analog differential signal and transmit the analog differential signal to the D-band eight-channel transmitter chip.

5. The D-band one-dimensional DBF-AIP microsystem architecture according to claim 4, characterized in that: The D-band eight-channel transmitter chip radiates and transmits the D-band radio frequency signal to the ANT9 antenna, the ANT10 antenna, the ANT11 antenna, the ANT12 antenna, the ANT13 antenna, the ANT14 antenna, the ANT15 antenna, and the ANT16 antenna.

6. The D-band one-dimensional DBF-AIP microsystem architecture of claim 1, wherein: The ADC chip has four channels.

7. The one-dimensional DBF-AIP microsystem architecture in the D-band according to claim 6, characterized in that: The ADC chip includes: SERDOUT± interface: indicates the output of digital signals that meet the SERDES protocol; SERDIN± interface: indicates the input of digital signals that meet the SERDES protocol; SDI interface: Indicates the chip's SPI input; SDO interface: Indicates that the chip outputs SPI; SCLK interface: Indicates the chip's SPI clock; SYNC interface: Indicates SPI chip select for the RF chip; CLK interface: Indicates the input clock; CSB interface: Indicates digital chip select; VREF interface: Indicates the internal / external reference input selection signal.

8. The one-dimensional DBF-AIP microsystem architecture in the D-band according to claim 1, characterized in that: The DAC chip is a four-channel chip.

9. The one-dimensional DBF-AIP microsystem architecture in the D-band according to claim 8, characterized in that: The DAC chip includes: SYNCOUT± interface: indicates the output of analog differential signals; SYSCIN± interface: Represents the input of analog differential signals; SYSREF interface: Represents the reference signal for the differential system; SDI interface: Indicates the chip's SPI input; SDO interface: Indicates that the chip outputs SPI; SCLK interface: Indicates the chip's SPI clock; SYNC interface: Indicates SPI chip select for the RF chip; CLK interface: Indicates the input clock; CSB interface: Indicates digital chip select; VREF interface: Indicates the internal / external reference input selection signal.

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