A high-efficiency clock data recovery circuit with odd-numbered data rates

Abstract

This invention discloses a high-efficiency odd-rate clock data recovery circuit. It uses switched capacitors to implement the phase detector, effectively reducing the phase detector's power consumption and area. Furthermore, its equivalent resistance and subsequent small-loop filter capacitor achieve a large loop bandwidth independent of PVT, effectively increasing the frequency acquisition range, eliminating the frequency discrimination loop, reducing lock-in time, suppressing the phase noise of the ring oscillator, and improving the jitter tolerance performance of the CDR loop. In addition, the retiming of random data employs an odd-rate demultiplexing structure, reducing the operating frequency of the N-stage ring oscillator, buffer, and retimer to 1 / N of the full-rate structure. This effectively reduces the power consumption and parasitic effects of the CDR circuit. The use of a frequency accumulator cleverly multiplies the odd-rate sub-rate clock by N to a full-rate clock without introducing excessive power consumption and area, where N is an odd number.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design technology, specifically relating to a high-efficiency clock data recovery circuit with odd-numbered data rates. Background Technology

[0002] With the explosive growth in the number of devices connected to the central system, data throughput and communication bandwidth have increased unprecedentedly. However, content-intensive video data accounts for the largest proportion of the total data volume, and the growth rate of data volume far exceeds the growth rate of the number of devices. Therefore, in order to meet the ever-increasing data transmission demands, it is necessary to significantly increase the bandwidth requirements of the input / output interface transceivers supporting the server system. The Clock and Data Recovery (CDR) circuit located at the link receiver is a key module that determines the bit error rate of the high-speed data interface system. Its main function is to recover the required clock signal from the data stream processed by the equalizer and use the recovered clock to retime the equalized data stream.

[0003] Multi-link wired transceivers (CDRs) need to address clock distribution issues on long interconnects due to the large footprint of the chip modules. Therefore, the use of inductors and capacitors should be avoided as much as possible in the circuit design. Energy efficiency is also a crucial performance indicator for wired transceivers. However, CDR circuits typically rely on inductor-capacitor oscillators to achieve low clock jitter and large-area loop filters to limit the bandwidth and peak value of the jitter transfer function. Furthermore, traditional CDR circuit architectures face a trade-off between restoring clock jitter performance and restoring data jitter tolerance. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a high-efficiency clock data recovery circuit with an odd-numbered data rate.

[0005] The present invention provides a high-efficiency clock data recovery circuit with odd-number rate, comprising: a switched capacitor, a filter capacitor, an N-stage ring oscillator and a clock buffer connected in sequence. The output of the clock buffer is connected to a clock duty cycle tuning circuit and a frequency accumulator, respectively. The output of the frequency accumulator is fed back to the switched capacitor. The output of the clock duty cycle tuning circuit is connected to a timer.

[0006] The switched capacitor is used to control the sampling timing based on the input binary random data to sample the clock signal fed back by the frequency accumulator and obtain the sampled voltage output to the filter capacitor.

[0007] The filter capacitor is connected to the switched capacitor and together with the equivalent resistance of the switched capacitor, forms a low-pass filter to filter the input sampling voltage and output a control voltage with smaller ripple to the N-stage ring oscillator.

[0008] The N-stage ring oscillator, connected to the filter capacitor, is used to generate N clocks of corresponding frequencies according to the control voltage.

[0009] The phase difference of each clock is 360° / N, where N is a positive odd number that does not include 1;

[0010] The clock buffer is connected to the N-stage ring oscillator and is used to provide DC bias voltage for the N clocks and adjust the duty cycle of the N clocks to output two N square waves with a duty cycle of 50% and opposite phases. The positive N square waves are output to the clock duty cycle tuning circuit, and the negative N square waves are output to the frequency accumulator.

[0011] The clock duty cycle tuning circuit is connected to the clock buffer and is used to adjust the duty cycle of the N reverse square waves from 50% to M% to obtain two clock signals that are opposite to each other to the timer, and to make the rising edge of the reverse clock signal aligned with the data center to be sampled.

[0012] The re-timer is connected to the clock duty cycle tuning circuit and is used to sample the input binary random data at voltage according to the rising edge of the reverse clock signal and output N channels of recovered data.

[0013] The frequency accumulator, connected to the clock buffer, is used to accumulate N positive square waves into an N-fold frequency output clock and feed it back to the switched capacitor.

[0014] Optionally, the switched capacitor includes: switch S1, switch S2 and sampling capacitor C1, switch S1 and switch S2 are connected in series, one end of sampling capacitor C1 is connected between switch S1 and switch S2, and the other end is connected to power ground; the other end of switch S1 is connected to the output of frequency accumulator; the other end of switch S2 is connected to filter capacitor and N-stage ring oscillator respectively.

[0015] In this circuit, switch S1 is composed of transistors Mp1 and Mn1, and switch S2 is composed of transistors Mp2 and Mn2. The gates of transistors Mp1 and Mp2 serve as the input terminals of the switching capacitor, inputting random data Din. The drains of transistors Mp1, Mp2, Mn1, and Mn2 are connected to one end of sampling capacitor C1, generating a sampling voltage V1. The source and drain of transistors Mp1 and Mn1 serve as the other connection terminals of switch S1, connected to a frequency accumulator to receive the clock CLKBfa fed back from the frequency accumulator. The gates of transistors Mn1 and Mn2 serve as the inverting input terminals of the switching capacitor, inputting inverted random data DinB. The drain and source of transistors Mp2 and Mn2 serve as the other connection terminals of switch S2, outputting a control voltage Vctr1 to the filter capacitor and the N-stage ring oscillator. The other end of sampling capacitor C1 is connected to ground potential GND.

[0016] Optionally, the N-stage ring oscillator includes: inverters Inva1 to InvaN and varactor tubes Var1 to VarN;

[0017] The input terminal of inverter Inva1 is connected to the output terminal of inverter InvaN and the first terminal of varactor VarN. The output terminal of inverter InvaN outputs the Nth clock signal CLK. <n-1>The input terminal of inverter Inva2 is connected to the output terminal of inverter Inva1 and the first terminal of varactor Var1. The output terminal of inverter Inva1 outputs the first clock signal CLK. <0> The input terminal of inverter InvaN is connected to the output terminal of inverter InvaN-1 and the first terminal of varactor VarN-1. The output terminal of inverter InvaN-1 outputs the (N-1)th clock channel CLK. <n-2>The second terminals of the varactors Var1 to VarN are all input with a control voltage Vctrl that has passed through a low-pass filter.

[0018] Optionally, the clock buffer includes N-way buffer circuits. The nth buffer circuit consists of a capacitor Can, an inverter Invbn, and an inverter Pan connected in series. A resistor Rn is connected across the inverter Invbn. One end of the capacitor Can receives the clock signal CLK from the nth channel of the N-stage ring oscillator. <n-1>The inverter Pan outputs the nth positive clock signal, CLKBB. <n-1>The input of the frequency accumulator and the output of the inverter Invbn output the nth reverse clock CLKB. <n-1>To the input terminal of the clock duty cycle tuning circuit;

[0019] Where n takes values ​​from 1 to N.

[0020] Optionally, the frequency accumulator includes inverters Invc1 to InvcN, inverter Pb, capacitor Cx, and resistor Rx, with the clock signal CLKBB input to the input terminal of inverter Invc1. <0> The inverter Invc2 receives the clock signal CLKBB at its input terminal. <1> The inverter Invcn receives the clock signal CLKBB at its input terminal. <n-1>The output terminals of inverters Invc1 to InvcN are connected to one end of capacitor Cx and generate a frequency accumulation clock signal CLKfa. The other end of capacitor Cx is connected to inverter Pb. Inverter Pb outputs a frequency accumulation clock signal CLKBfa, which is fed back to the switched capacitor. Resistor Rx is connected across the two ends of inverter Pb.

[0021] Where n takes values ​​from 1 to N.

[0022] Optionally, the clock duty cycle tuning circuit includes an inverter comprising: N parallel tuning circuits, wherein the nth tuning circuit includes inverters Invd2n-1, Invd2n, Inven, Invfn, Invg2n-1, Invg2n, Invh2n-1, Invh2n, and a transmission gate Transn;

[0023] In this circuit, the input of inverter Invd2n-1 is connected to the inverted clock CLKB of the nth channel of the clock buffer. <n>The outputs of inverter Invd2n-1 and inverter Invd2n are both connected to the input of inverter Invd2n. The output of inverter Invd2n is connected to the input of transmission gate Transn and inverter Invfn, respectively. Inverters Invfn, Invg2n, and Invh2n are connected in sequence. The output of inverter Invh2n is the nth positive square wave CLKBBBB. <n>The output of the transmission gate Transn, inverters Invg2n-1 and Invh2n-1 are connected in sequence. Inverter Invh2n-1 outputs the inverted square wave CLKBBB of the nth channel. <n>The value of n ranges from 1 to N.

[0024] Optionally, the retimer includes: N-channel data recovery circuits, wherein the nth data recovery circuit includes transistors Man, Mbn, Mcn, Mdn, Men, Mfn, Mgn, Mhn, Min, Mjn, Mkn and transistor Mln;

[0025] In this circuit, binary random data is input to the source of transistor Man and the drain of transistor Mbn, while the gates of transistors Man and Mln are connected to the nth positive square wave CLKBBBBB output by the clock duty cycle tuning circuit. <n-1>The gates of transistors Mbn and Mkn are connected to the inverted square wave CLKBBB of the nth path output by the clock duty cycle tuning circuit. <n-1>The drain of transistor Man and the source of Mbn are both connected to the gates of transistors Mcn and Mdn. The drains of transistors Mcn and Mdn are connected together and are both connected to the gates of transistors Men and Mfn. The drain of transistor Men is connected to the source of Mkn, the drain of transistor Mln, and the gate of transistor McGn. The drain of transistor Mfn is connected to the drain of Mkn, the source of transistor Mln, and the gate of transistor Mahn. The drains of transistors Mkn and McGn are connected together and then connected to the gates of transistors Min and Mjn. The drains of transistors Min and Mjn serve as output terminals. The sources of transistors Mcn, Men, McGn, and Min are all connected to the power supply voltage VDD. The sources of transistors Mdn, Mfn, Mahn, and Mjn are all connected to the ground potential GND. The value of n ranges from 1 to N.

[0026] This invention discloses a high-efficiency odd-rate clock data recovery circuit. It uses switched capacitors to implement the phase detector, effectively reducing the phase detector's power consumption and area. Furthermore, its equivalent resistance and subsequent small-loop filter capacitor achieve a large loop bandwidth independent of PVT, effectively increasing the frequency acquisition range, eliminating the frequency discrimination loop, reducing lock-in time, suppressing the phase noise of the ring oscillator, and improving the jitter tolerance performance of the CDR loop. In addition, the retiming of random data employs an odd-rate demultiplexing structure, reducing the operating frequency of the N-stage ring oscillator, buffer, and retimer to 1 / N of the full-rate structure. This effectively reduces the power consumption and parasitic effects of the CDR circuit. The use of a frequency accumulator cleverly multiplies the odd-rate sub-rate clock by N to a full-rate clock without introducing excessive power consumption and area, where N is an odd number.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a high-efficiency clock data recovery circuit with an odd-numbered data rate provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the specific circuit implementation of the switched capacitor in the clock data recovery circuit provided in this embodiment of the invention;

[0030] Figure 3 This is a schematic diagram of the node voltage waveform of the switched capacitor in the clock data recovery circuit provided in this embodiment of the invention;

[0031] Figure 4 This is a schematic diagram of the specific circuit implementation of the N-stage ring oscillator in the clock data recovery circuit provided in this embodiment of the invention;

[0032] Figure 5 This is a schematic diagram of the specific circuit implementation of the clock buffer in the clock data recovery circuit provided in the embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the specific circuit implementation of the frequency accumulator in the clock data recovery circuit provided in this embodiment of the invention;

[0034] Figure 7 This is a schematic diagram of the specific circuit implementation of the duty cycle tuning circuit in the clock data recovery circuit provided in the embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the specific circuit implementation of the timer in the clock data recovery circuit provided in the embodiment of the present invention. Detailed Implementation

[0036] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0037] like Figure 1 As shown, the present invention provides a high-efficiency clock data recovery circuit with odd-numbered data rates, comprising: a switched capacitor, a filter capacitor, an N-stage ring oscillator, and a clock buffer connected in sequence. The output of the clock buffer is connected to a clock duty cycle tuning circuit and a frequency accumulator, respectively. The output of the frequency accumulator is fed back to the switched capacitor, and the output of the clock duty cycle tuning circuit is connected to a timer.

[0038] The switched capacitor is used to control the sampling timing based on the input binary random data to sample the clock signal fed back by the frequency accumulator and obtain the sampled voltage output to the filter capacitor.

[0039] The filter capacitor is connected to the switched capacitor and together with the equivalent resistance of the switched capacitor, forms a low-pass filter to filter the input sampling voltage and output a control voltage with smaller ripple to the N-stage ring oscillator.

[0040] The N-stage ring oscillator, connected to the filter capacitor, is used to generate N clocks of corresponding frequencies according to the control voltage.

[0041] The phase difference of each clock is 360° / N, where N is a positive odd number that does not include 1;

[0042] The clock buffer is connected to the N-stage ring oscillator and is used to provide DC bias voltage for the N clocks and adjust the duty cycle of the N clocks to output two N square waves with a duty cycle of 50% and opposite phases. The positive N square waves are output to the clock duty cycle tuning circuit, and the negative N square waves are output to the frequency accumulator.

[0043] Among them, there are two types of N-way square waves with opposite phases: one is a positive N-way square wave, and the other is a negative N-way square wave.

[0044] The clock duty cycle tuning circuit is connected to the clock buffer and is used to adjust the duty cycle of the N reverse square waves from 50% to M% to obtain two clock signals that are opposite to each other to the timer, and to make the rising edge of the reverse clock signal aligned with the data center to be sampled.

[0045] Where M takes values ​​from 0 to 100, and N is a positive odd number.

[0046] The re-timer is connected to the clock duty cycle tuning circuit and is used to sample the input binary random data at voltage according to the rising edge of the reverse clock signal and output N channels of recovered data.

[0047] The frequency accumulator, connected to the clock buffer, is used to accumulate N positive square waves into an N-fold frequency output clock and feed it back to the switched capacitor.

[0048] refer to Figure 2 The switched capacitor includes: switch S1, switch S2 and sampling capacitor C1. Switch S1 and switch S2 are connected in series. One end of the sampling capacitor C1 is connected between switch S1 and switch S2, and the other end is connected to the power supply ground. The other end of switch S1 is connected to the output of the frequency accumulator. The other end of switch S2 is connected to the filter capacitor and the N-stage ring oscillator respectively.

[0049] In this circuit, switch S1 is composed of transistors Mp1 and Mn1, and switch S2 is composed of transistors Mp2 and Mn2. The gates of transistors Mp1 and Mp2 serve as the input terminals of the switching capacitor, inputting random data Din. The drains of transistors Mp1, Mp2, Mn1, and Mn2 are connected to one end of sampling capacitor C1, generating a sampling voltage V1. The source and drain of transistors Mp1 and Mn1 serve as the other connection terminals of switch S1, connected to a frequency accumulator to receive the clock CLKBfa fed back from the frequency accumulator. The gates of transistors Mn1 and Mn2 serve as the inverting input terminals of the switching capacitor, inputting inverted random data DinB. The drain and source of transistors Mp2 and Mn2 serve as the other connection terminals of switch S2, outputting a control voltage Vctr1 to the filter capacitor and the N-stage ring oscillator. The other end of sampling capacitor C1 is connected to ground potential GND.

[0050] Transistors Mp1 and Mn1 form transmission gate switch S1, and transistors Mp2 and Mn2 form transmission gate switch S2. When the rising edge of random data Din arrives, transmission gate switch S1 closes, transmission gate switch S2 turns off, and the sampling voltage V1 begins to track the frequency accumulation clock CLKBfa. When the falling edge of random data Din arrives, transmission gate switch S1 turns off, transmission gate switch S2 turns on, and sampling capacitor C1 and subsequent filter capacitor C2 share charge to achieve a stable voltage. This cycle repeats. At the instant switch S1 turns off, if the sampling voltage V1 on the sampling capacitor is equal to the control voltage Vctrl on the filter capacitor, the clock frequency output by the ring oscillator no longer changes, and the CDR loop reaches a locked state, as shown in the waveform. Figure 3 As shown. Let the control voltage during CDR loop locking be V0, the RC time constant determined by the on-resistance of switch S1 and the sampling capacitor C1 be τ1, and the random data rate be 1T per second. b The phase difference between the random data Din and the frequency accumulation clock CLKBfa is... The locking control voltage V0 can then be expressed as:

[0051]

[0052] It can be simplified to

[0053]

[0054] Let the gain of the sampling capacitor phase detector be K. PD It can be expressed as the lockout control voltage V0 with respect to the phase difference The derivative, i.e.

[0055]

[0056] From equation (3), it can be seen that the gain K of the sampling capacitor phase detector is... PD It is negatively correlated with the time constant τ1. Due to considerations of small area design, the sampling capacitor is designed to be relatively small; furthermore, to obtain a larger phase detector gain K... PD Therefore, the on-resistance of switch S1 needs to be as small as possible, which contradicts non-ideal factors such as clock feedthrough and charge injection. The value of loop filter capacitor C2 involves a trade-off between loop bandwidth and non-ideal factors such as charge injection, clock feedthrough, and kT / C noise. In this embodiment, sampling capacitor C1 is set equal to filter capacitor C2 to reduce chip area, obtain a large loop bandwidth, increase frequency acquisition range, and save on the cost of the frequency discrimination loop.

[0057] Let the equivalent resistance of the switched capacitor be R. eq Its magnitude is related to the switching frequency f and the sampling capacitor C1.

[0058]

[0059] Assuming the input random data Din is a pseudo-random binary sequence, then f≈1(4T) b At this point, the equivalent resistance of the switched capacitor can be expressed as:

[0060]

[0061] The filter capacitor C2 and the equivalent resistance R of the switched capacitor eq This constitutes a low-pass filter, whose -3dB bandwidth ω0 can be expressed as...

[0062]

[0063] From (6), we can see that this bandwidth is independent of process, voltage, and temperature (PVT). Furthermore, we can obtain the transfer function of the switched-capacitor phase detector as follows:

[0064]

[0065] Compared to traditional Bang-Bang phase detectors based on D flip-flops, switched-capacitor phase detectors, due to their passive nature, consume negligible power only through the gate capacitances of the transistors in transmission gate switches S1 and S2 under locked conditions, significantly reducing power consumption. Let the total gate capacitance of the transistors be C, then the power consumption P of the switched-capacitor phase detector can be expressed as:

[0066]

[0067] refer to Figure 4 The N-stage ring oscillator includes: inverters Inva1 to InvaN and varactor tubes Var1 to VarN;

[0068] The input terminal of inverter Inva1 is connected to the output terminal of inverter InvaN and the first terminal of varactor VarN. The output terminal of inverter InvaN outputs the Nth clock signal CLK. <n-1>The input terminal of inverter Inva2 is connected to the output terminal of inverter Inva1 and the first terminal of varactor Var1. The output terminal of inverter Inva1 outputs the first clock signal CLK. <0> The input terminal of inverter InvaN is connected to the output terminal of inverter InvaN-1 and the first terminal of varactor VarN-1. The output terminal of inverter InvaN-1 outputs the (N-1)th clock channel CLK. <n-2>The second terminals of the varactors Var1 to VarN are all input with a control voltage Vctrl that has passed through a low-pass filter.

[0069] For example, assuming N is 3, the N-stage ring oscillator is a three-stage ring oscillator, including inverters Inv1 to Inv3 and varactors Var1 to Var3. The input terminal of inverter Inv1 is connected to the output terminal of inverter Inv3 and the first terminal of varactor Var3, and outputs a clock signal CLK. <2> The input terminal of inverter Inv2 is connected to the output terminal of inverter Inv1 and the first terminal of varactor Var1, and outputs the clock signal CLK. <0> The input terminal of inverter Inv3 is connected to the output terminal of inverter Inv2 and the first terminal of varactor Var2, and outputs the clock signal CLK. <1> The second terminals of the varactor tubes Var1 to Var3 are all input with a control voltage Vctrl.

[0070] To save chip area and power consumption, the ring oscillator of this invention can be formed by cascading three single-ended inverters end to end, which is used to output three clock signals with a phase difference of 120°, and the frequency of the output clock can be changed by adjusting the size of the varactor tube by controlling the voltage Vctrl.

[0071] refer to Figure 5 The clock buffer includes N buffer circuits. The nth buffer circuit consists of a capacitor Can, an inverter Invbn, and an inverter Pan connected in series. A resistor Rn is connected across the inverter Invbn. One end of the capacitor Can receives the clock signal CLK from the nth channel of the N-stage ring oscillator. <n-1>The inverter Pan outputs the nth positive clock signal, CLKBB. <n-1>The input of the frequency accumulator and the output of the inverter Invbn output the nth reverse clock CLKB. <n-1>To the input terminal of the clock duty cycle tuning circuit;

[0072] Where n takes values ​​from 1 to N.

[0073] It's worth noting that the capacitor Can, inverter Invbn, and inverter Pan are connected in series, with resistor Rn across inverter Invbn, forming the nth self-biased inverter. This provides the nth input clock with DC bias voltage, 50% duty cycle adjustment, and the ability to drive the output clock. For a given AC-coupled self-biased inverter, assume the feedback resistor is R... n The AC coupling capacitor is C. an The small-signal output impedance of the inverter is r on The transconductance of the inverter is g mn The output load capacitance of the inverter is C. Ln Then the small-signal gain can be expressed as

[0074]

[0075] Its frequency response curve can be regarded as a bandpass filter. Inverters Pa1, Pa2, ..., PaN serve as gain amplification stages to further improve the driving capability of the output clock.

[0076] refer to Figure 6 The frequency accumulator includes inverters Invc1 to InvcN, inverter Pb, capacitor Cx, and resistor Rx. The input terminal of inverter Invc1 receives the clock signal CLKBB. <0> The inverter Invc2 receives the clock signal CLKBB at its input terminal. <1> The inverter Invcn receives the clock signal CLKBB at its input terminal. <n-1>The output terminals of inverters Invc1 to InvcN are connected to one end of capacitor Cx and generate a frequency accumulation clock signal CLKfa. The other end of capacitor Cx is connected to inverter Pb. Inverter Pb outputs a frequency accumulation clock signal CLKBfa, which is fed back to the switched capacitor. Resistor Rx is connected across the two ends of inverter Pb.

[0077] Where n takes values ​​from 1 to N.

[0078] For example, assuming N is 3, then CLRBB <0> CLKBB <1> CLKBB <2> These are three square wave clock signals with a phase difference of 120°. After passing through a frequency accumulator, they are synthesized into a single sinusoidal signal CLKfa with a frequency three times that of the original signals. Let the peak-to-peak swing of the square wave clock signal output by the N-stage single-ended ring oscillator be A, and the delay time of each delay unit be TD. Then, the k-th output square wave clock signal can be expressed as the sum of all odd harmonic components, i.e.

[0079]

[0080] By summing the N square wave clock signals output from an N-stage single-ended ring oscillator, an N-fold frequency sine wave signal can be obtained.

[0081]

[0082] As can be seen from (11), the output swing of the frequency accumulation clock signal CLKfa is not rail-to-rail. Therefore, an AC-coupled self-biased inverter is cascaded in the later stage to provide DC bias voltage, 50% duty cycle adjustment and increase driving capability to obtain a frequency accumulation clock signal CLKBfa with a larger swing.

[0083] refer to Figure 7 The clock duty cycle tuning circuit includes: N parallel tuning circuits, the nth tuning circuit including inverters Invd2n-1, Invd2n, Inven, Invfn, Invg2n-1, Invg2n, Invh2n-1, Invh2n and Transn gate;

[0084] In this circuit, the input of inverter Invd2n-1 is connected to the inverted clock CLKB of the nth channel of the clock buffer. <n-1>The outputs of inverters Invd2n-1 and Invd2n are both connected to the input of inverter Inven. The output of inverter Inven is connected to the input of transmission gate Transn and inverter Invfn, respectively. Inverters Invfn, Invg2n, and Invh2n are connected in sequence. The output of inverter Invh2n is the nth positive square wave CLKBBBB. <n-1>The output of the transmission gate Transn, inverters Invg2n-1 and Invh2n-1 are connected in sequence. Inverter Invh2n-1 outputs the inverted square wave CLKBBB of the nth channel. <n-1>The value of n ranges from 1 to N.

[0085] As can be seen from (3), due to the limited gain of the switched capacitor phase detector, the CDR circuit structure proposed in this invention exhibits a type of transfer function, resulting in a certain phase difference between the recovery clock and the random data when the CDR loop is locked. like Figure 3 As shown. According to (2), the phase difference Related to the lockout control voltage V0, and the phase difference It can be represented as

[0086]

[0087] If the random data rate changes, the oscillator output clock frequency during locking changes, which means the lockout control voltage V0 changes, thus altering the phase difference between the recovery clock and the random data, increasing the difficulty of data retiming. Therefore, the CDR circuit structure proposed in this invention cascades a clock duty cycle tuning circuit after the clock buffer to adjust the clock duty cycle, ensuring the retiming clock is aligned with the data center to reduce the bit error rate and increase its driving capability.

[0088] With CLKB <0> Taking the branch circuit as an example, inverters Invd1, Invd2, and Inve1 constitute a duty cycle adjustment unit, which can linearly adjust the clock CLKB according to the control voltage Vdc. <0> The duty cycle is adjusted. The duty cycle tuning unit is essentially an inverter Invd1, whose drive strength is changed by a variable current source Invd2 connected to the inverter's output node. Therefore, the rise or fall time of the clock signal can be adjusted as needed. When the drive strength is decreased to increase the rise or fall time, the clock signal's duty cycle increases; when the drive strength is increased to decrease the rise or fall time, the clock signal's duty cycle decreases. Inverter Invd1 can shape the duty cycle-tuned clock signal into a square wave signal, improving its drive capability. Transmission gate Trans1, inverters Invf1, Invg1, Invg2, Invh1, and Invh2 are used to output a differential clock signal. The delay of transmission gate Trans1 is equivalent to the delay of inverter Invf1, simply making the output clock CLKBBB. <0> With CLRBBBB <0> The phase difference between them is 180°. Similarly, CLKB <1> CLKB <2> The working principle of the branch circuit and CLKB <0> The same applies to outputting a differential clock signal with an adjustable duty cycle.

[0089] Test Figure 8 The re-timer includes: N-channel data recovery circuits, wherein the nth data recovery circuit includes transistors Man, Mbn, Mcn, Mdn, Men, Mfn, Mgn, Mhn, Min, Mjn, Mkn and transistor Mln;

[0090] In this circuit, binary random data is input to the source of transistor Man and the drain of transistor Mbn, while the gates of transistors Man and Mln are connected to the nth positive square wave CLKBBBBB output by the clock duty cycle tuning circuit. <n-1>The gates of transistors Mbn and Mkn are connected to the inverted square wave CLKBBB of the nth path output by the clock duty cycle tuning circuit. <n-1>The drain of transistor Man and the source of Mbn are both connected to the gates of transistors Mcn and Mdn. The drains of transistors Mcn and Mdn are connected together and are both connected to the gates of transistors Men and Mfn. The drain of transistor Men is connected to the source of Mkn, the drain of transistor Mln, and the gate of transistor McGn. The drain of transistor Mfn is connected to the drain of Mkn, the source of transistor Mln, and the gate of transistor Mahn. The drains of transistors Mkn and McGn are connected together and then connected to the gates of transistors Min and Mjn. The drains of transistors Min and Mjn serve as output terminals. The sources of transistors Mcn, Men, McGn, and Min are all connected to the power supply voltage VDD. The sources of transistors Mdn, Mfn, Mahn, and Mjn are all connected to the ground potential GND. The value of n ranges from 1 to N.

[0091] For example, to recover data Dout <0> Taking a branch as an example, transistors Ma1, Mb1, Mc1, Md1, Me1, Mf1, Mg1, Mh1, Mi1, Mj1, Mk1, and Ml1 can be considered as a D flip-flop. Based on TSMC's 45nm process, the highest operating frequency of a traditional true single-phase clock D flip-flop is around 8GHz, while the power consumption of a traditional high-speed current-mode logic D flip-flop that can be used at operating frequencies above 10GHz is only a few milliwatts. Therefore, neither is suitable for the design requirements of high-speed, low-power CDR circuits. The reason why the operating frequency of a traditional true single-phase clock D flip-flop is limited is that the single PMOS or NMOS switch in the linear region, when the input voltage approaches the threshold voltage or the supply voltage minus the threshold voltage, the on-resistance tends to infinity. The node voltage inside the D flip-flop cannot achieve rail-to-rail swing, thus increasing the transition time between high and low levels in the internal node, which affects the phase noise of the circuit. Furthermore, traditional true single-phase clock D flip-flops suffer from a significant difference in the high-low level transition times of the retiming output data, leading to a decrease in jitter tolerance performance during data recovery. The root cause of this problem is the difference between the mobility and threshold voltage of a single PMOS or NMOS switch. To address this issue, this invention proposes a high-speed, low-power D flip-flop that replaces the two single switches in a traditional true single-phase clock D flip-flop with two pairs of switches connected by a differential clock CLKBBB. <0> CLKBBBBB <0> The control transmission gates, where transistors Ma1 and Mb1 form one transmission gate, and transistors Mk1 and Ml1 form another, enable rail-to-rail voltage swing at internal nodes and effectively solve the problem of large differences in high-low level transition times. This significantly increases the operating frequency of the D flip-flop without substantially increasing power consumption or severely degrading jitter tolerance performance. Furthermore, to make the high-speed, low-power D flip-flop suitable for sub-rate data retiming structures, the first transmission gate is placed at the input of the D flip-flop, such as... Figure 8 As shown. After passing through the clock duty cycle tuning circuit, the clock signal CLKBBB <0> The falling edge aligns with the data center of the random data Din, and the clock signal CLKBBB <0> When the signal is high, the transmission gate composed of transistors Ma1 and Mb1 is turned on, completing the sub-rate sampling of random data Din; the clock signal CLKBBB <0> When the signal is low, the transmission gate composed of transistors Mk1 and Ml1 is turned on, allowing the recovered data to be retimed and driven by the inverter in the last stage, composed of transistors Mi1 and Mj1, to output the recovered data Dout. <0> Similarly, Dout <1> Dout <2> The working principle of the branch and Dout <0> Similarly, it is used for retiming and demultiplexing random data. In summary, the D flip-flop proposed in this invention has advantages over traditional true single-phase clock D flip-flops and traditional current-mode logic D flip-flops, including low power consumption, high operating frequency, no significant deterioration of jitter tolerance performance, and suitability for sub-rate retiming structures.

[0092] This invention proposes a high-efficiency odd-rate clock data recovery circuit, eliminating the use of frequency discrimination loops, voltage-to-current converters, and large-area filter capacitors in traditional phase-locked loop (PLL) clock data recovery circuits, significantly reducing the power consumption and area of ​​the CDR circuit. Compared to traditional Bang-Bang phase detectors based on D flip-flops, the phase detector in this invention uses switched capacitors, effectively reducing its power consumption and area. Simultaneously, its equivalent resistance and subsequent small-loop filter capacitor achieve a large loop bandwidth independent of PVT, effectively increasing the frequency acquisition range, eliminating the frequency discrimination loop, reducing lock-in time, suppressing the phase noise of the ring oscillator, and improving the CDR loop jitter tolerance performance, thus alleviating the trade-off between clock jitter recovery performance and data jitter tolerance in traditional PLL CDR circuits. The retiming of random data employs an odd-rate demultiplexing structure, reducing the operating frequency of the N-stage ring oscillator, buffer, and retimer to 1 / N of the full-rate structure, effectively reducing the power consumption and parasitic effects of the CDR circuit. The use of a frequency accumulator can cleverly multiply an odd-rate sub-rate clock by N to a full-rate clock without introducing excessive power consumption and area. Furthermore, the retimer proposed in this invention is a sub-rate data type, which significantly improves the operating frequency compared to traditional true single-phase clock flip-flops; and at the same operating frequency, it significantly reduces power consumption compared to traditional current-mode logic flip-flops.

[0093] In summary, the high-efficiency odd-rate clock data recovery circuit proposed in this invention can significantly reduce power consumption, reduce area, save costs, and has good jitter performance in clock recovery and jitter tolerance performance in data recovery.

[0094] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0095] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0096] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention. < / n> < / n> < / n>

Claims

1. A high-efficiency clock data recovery circuit with an odd-numbered data rate, characterized in that, include: A switched capacitor, a filter capacitor, an N-stage ring oscillator, and a clock buffer are connected in sequence. The output of the clock buffer is connected to a clock duty cycle tuning circuit and a frequency accumulator, respectively. The output of the frequency accumulator is fed back to the switched capacitor. The output of the clock duty cycle tuning circuit is connected to a timer. The switched capacitor is used to control the sampling timing based on the input binary random data to sample the clock signal fed back by the frequency accumulator and obtain the sampled voltage output to the filter capacitor. The filter capacitor is connected to the switched capacitor and together with the equivalent resistance of the switched capacitor, forms a low-pass filter to filter the input sampling voltage and output a control voltage with smaller ripple to the N-stage ring oscillator. The N-stage ring oscillator, connected to the filter capacitor, is used to generate N clocks of corresponding frequencies according to the control voltage. The phase difference of each clock is 360° / N, where N is a positive odd number that does not include 1; The clock buffer is connected to the N-stage ring oscillator and is used to provide DC bias voltage for the N clocks and adjust the duty cycle of the N clocks to output two N square waves with a duty cycle of 50% and opposite phases. The reverse N square waves are output to the clock duty cycle tuning circuit, and the positive N square waves are output to the frequency accumulator. The clock duty cycle tuning circuit is connected to the clock buffer and is used to adjust the duty cycle of the N reverse square waves from 50% to M% to obtain two clock signals that are opposite to each other to the timer, and to make the rising edge of the reverse clock signal aligned with the data center to be sampled. The re-timer is connected to the clock duty cycle tuning circuit and is used to sample the input binary random data at voltage according to the rising edge of the reverse clock signal and output N channels of recovered data. The frequency accumulator, connected to the clock buffer, is used to accumulate N positive square waves into an N-fold frequency output clock and feed it back to the switched capacitor.

2. The high-efficiency odd-rate clock data recovery circuit according to claim 1, characterized in that, The switched capacitor includes: switch S1, switch S2 and sampling capacitor C1. Switch S1 and switch S2 are connected in series. One end of the sampling capacitor C1 is connected between switch S1 and switch S2, and the other end is connected to the power supply ground. The other end of switch S1 is connected to the output of the frequency accumulator. The other end of switch S2 is connected to the filter capacitor and the N-stage ring oscillator respectively. In this circuit, switch S1 is composed of transistors Mp1 and Mn1, and switch S2 is composed of transistors Mp2 and Mn2. The gates of transistors Mn1 and Mp2 serve as the input terminals of the switching capacitor, inputting random data Din. The drains of transistors Mp1, Mp2, Mn1, and Mn2 are connected to one end of sampling capacitor C1, generating a sampling voltage V1. The source and drain of transistors Mp1 and Mn1 serve as the other connection terminals of switch S1, connected to a frequency accumulator to receive the clock CLKBfa fed back from the frequency accumulator. The gates of transistors Mp1 and Mn2 serve as the inverting input terminals of the switching capacitor, inputting inverted random data DinB. The drains of transistors Mp2 and Mn2 serve as the other connection terminals of switch S2, outputting a control voltage Vctr1 to the filter capacitor and the N-stage ring oscillator. The other end of sampling capacitor C1 is connected to ground potential GND.

3. The high-efficiency odd-rate clock data recovery circuit according to claim 1, characterized in that, The N-stage ring oscillator includes: inverters Inva1~InvaN and varactor tubes Var1~VarN; The input terminal of inverter Inva1 is connected to the output terminal of inverter InvaN and the first terminal of varactor VarN. The output terminal of inverter InvaN outputs the Nth clock signal CLK. <n-1>The input terminal of inverter Inva2 is connected to the output terminal of inverter Inva1 and the first terminal of varactor Var1. The output terminal of inverter Inva1 outputs the first clock signal CLK. <0> The input terminal of inverter InvaN is connected to the output terminal of inverter InvaN-1 and the first terminal of varactor VarN-1. The output terminal of inverter InvaN-1 outputs the (N-1)th clock channel CLK. <n-2> The second terminals of the varactors Var1 to VarN are all input with a control voltage Vctrl that has passed through a low-pass filter.

4. The high-efficiency odd-rate clock data recovery circuit according to claim 1, characterized in that, The clock buffer includes N buffer circuits. The nth buffer circuit consists of a capacitor Can, an inverter Invbn, and an inverter Pan connected in series. A resistor Rn is connected across the inverter Invbn. One end of the capacitor Can receives the clock signal CLK from the nth stage of the N-stage ring oscillator. <n-1>The inverter Pan outputs the nth positive clock signal, CLKBB. <n-1>The input of the frequency accumulator and the output of the inverter Invbn output the nth reverse clock CLKB. <n-1> To the input terminal of the clock duty cycle tuning circuit; Where n takes values ​​from 1 to N.

5. The high-efficiency odd-rate clock data recovery circuit according to claim 1, characterized in that, The frequency accumulator includes inverters Invc1~InvcN, inverter Pb, capacitor Cx, and resistor Rx. The input terminal of inverter Invc1 receives the clock signal CLKBB. <0> The inverter Invc2 receives the clock signal CLKBB at its input terminal. <1> The inverter Invcn receives the clock signal CLKBB at its input terminal. <n-1> The output terminals of inverters Invc1~InvcN are connected to one end of capacitor Cx and generate a frequency accumulation clock signal CLKfa. The other end of capacitor Cx is connected to inverter Pb. Inverter Pb outputs a frequency accumulation clock signal CLKBfa, which is fed back to the switched capacitor. Resistor Rx is connected across the two ends of inverter Pb. Where n takes values ​​from 1 to N.

6. The high-efficiency odd-rate clock data recovery circuit according to claim 1, characterized in that, The clock duty cycle tuning circuit includes N parallel tuning circuits. The nth tuning circuit includes inverters Invd2n-1, Invd2n, Inven, Invfn, Invg2n-1, Invg2n, Invh2n-1, Invh2n, and a transmission gate Transn. In this circuit, the input of inverter Invd2n-1 is connected to the inverted clock CLKB of the nth channel of the clock buffer. <n>The outputs of inverters Invd2n-1 and Invd2n are both connected to the input of inverter Inven. The output of inverter Inven is connected to the input of transmission gate Transn and inverter Invfn, respectively. Inverters Invfn, Invg2n, and Invh2n are connected in sequence. The output of inverter Invh2n is the nth positive square wave CLKBBBB. <n>The output of the transmission gate Transn, inverters Invg2n-1 and Invh2n-1 are connected in sequence. Inverter Invh2n-1 outputs the inverted square wave CLKBBB of the nth channel. <n> The value of n ranges from 1 to N.< / n> < / n> < / n> 7. The high-efficiency odd-rate clock data recovery circuit according to claim 1, characterized in that, The re-timer includes: N-channel data recovery circuits, wherein the nth data recovery circuit includes transistors Man, Mbn, Mcn, Mdn, Men, Mfn, Mgn, Mhn, Min, Mjn, Mkn and transistor Mln; In this circuit, binary random data is input to the source of transistor Man and the drain of transistor Mbn, while the gates of transistors Man and Mln are connected to the nth positive square wave CLKBBBBB output by the clock duty cycle tuning circuit. <n-1>The gates of transistors Mbn and Mkn are connected to the inverted square wave CLKBBB of the nth path output by the clock duty cycle tuning circuit. <n-1>The drain of transistor Man and the source of Mbn are both connected to the gates of transistors Mcn and Mdn. The drains of transistors Mcn and Mdn are connected together and are both connected to the gates of transistors Men and Mfn. The drain of transistor Men is connected to the source of transistor Mkn, the drain of transistor Mln, and the gate of transistor Mgn. The drain of transistor Mfn is connected to the drain of transistor Mkn, the source of transistor Mln, and the gate of transistor Mhn. The drain of transistor Mhn is connected to the drain of transistor Mgn and then to the gates of transistors Min and Mjn. The drains of transistors Min and Mjn serve as output terminals. The sources of transistors Mcn, Men, Mgn, and Min are all connected to the power supply voltage VDD. The sources of transistors Mdn, Mfn, Mhn, and Mjn are all connected to the ground potential GND. The value of n ranges from 1 to N.< / n-1>

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