Data sequencing system and method

Abstract

The application discloses a data sorting system and method. In the application, the data sorting system comprises an ADC chip, a sorting multiplexing module and a sorting control module. When the current state is a test mode, the ADC chip is used to transmit data clock and LVDS data to the sorting multiplexing module, then the sorting multiplexing module is used to generate parallel output data according to the data clock and the LVDS data, and then the sorting control module is used to respectively perform data sorting processing on each channel data in the parallel output data. When the current state is the test mode, the ADC chip is used to transmit the data clock and the LVDS data to the sorting multiplexing module, and then the sorting control module is used to respectively perform data sorting processing on each channel data in the parallel output data. The delay condition of the parallel output data can be processed by the sorting control module, so that the calibration between the data and the clock can be realized, and the LVDS data can be accurately sorted.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a data sequence system and method. BACKGROUND

[0002] With the continuous development of ultrasonic technology, we have higher requirements for the refresh rate (image frame rate) of the image, which requires the probe to scan at a faster speed, and the data obtained by scanning needs to be returned faster. In order to meet the demand of high-speed transmission, most of the schemes on the market use ADC chips to transmit echo data back to the FPGA in parallel through multiple channels of LVDS. In this process, since the ADC sampling rate and data transmission rate are increased to the level of megahertz, even if the circuit is processed equally in length on the hardware level, the ADC sampling clock and the LVDS sampling data channel will easily appear data distortion, which is unacceptable. Not to mention that the physical length of the data channel with the same function on the hardware is often not the same, and the data transmission time is not the same at the same transmission speed, which will also cause the sampling data to be distorted. In view of this situation, calibration between the sampling data and the sampling clock needs to be carried out in the FPGA, that is, the receiving end, also known as sequence. Therefore, how to accurately sequence the LVDS data has become a problem to be solved.

[0003] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0004] The main purpose of the present application is to provide a data sequence system and method, which aims to solve the technical problem of how to accurately sequence the LVDS data.

[0005] To achieve the above purpose, the present application provides a data sequence system, which comprises: an ADC chip, a sequence multiplexing module, and a sequence control module.

[0006] The ADC chip is used to transmit data clock and LVDS data to the sequence multiplexing module when the current state is in test mode.

[0007] The sequence multiplexing module is used to generate parallel output data according to the data clock and the LVDS data.

[0008] The sequence control module is used to perform data sequence processing on each channel data in the parallel output data respectively.

[0009] Optionally, the sequence control module is also used to obtain the current delay value from the sequence multiplexing module.

[0010] The whole sequence control module is further configured to determine an ideal delay value according to the current delay value and each channel data in the parallel output data.

[0011] The whole sequence control module is further configured to perform whole sequence processing on each channel data in the parallel output data according to the ideal delay value.

[0012] Optionally, the whole sequence control module is further configured to compare each channel data in the parallel output data with a preset check value to obtain a comparison result.

[0013] The whole sequence control module is further configured to perform plus one processing on the current delay value to obtain a processed delay value.

[0014] The whole sequence control module is further configured to return to perform the step of comparing each channel data in the parallel output data with a preset check value to obtain a comparison result until the processed delay value is equal to the preset delay upper limit value and an effective interval is obtained when the processed delay value is smaller than the preset delay upper limit value.

[0015] The whole sequence control module is further configured to determine an ideal delay value according to the effective interval.

[0016] Optionally, the whole sequence control module is further configured to return to perform the step of comparing each channel data in the parallel output data with a preset check value to obtain a comparison result until the processed delay value is equal to the preset delay upper limit value when the processed delay value is smaller than the preset delay upper limit value.

[0017] The whole sequence control module is further configured to obtain all comparison results when the processed delay value is equal to the preset delay upper limit value.

[0018] The whole sequence control module is further configured to determine an effective interval according to all effective data in the all comparison results.

[0019] Optionally, the whole sequence control module is further configured to select a target effective interval with the largest range from the effective interval.

[0020] The whole sequence control module is further configured to compare the target effective interval with a preset delay value effective interval.

[0021] The whole sequence control module is further configured to take a middle value of the target effective interval as an ideal delay value when the target effective interval is larger than the preset delay value effective interval.

[0022] Optionally, the whole sequence control module is further configured to subtract the ideal delay value from the processed delay value to obtain a delay value difference.

[0023] The whole sequence control module is further configured to subtract the preset threshold from the processed delay value to obtain a target delay value when the delay value difference is greater than the preset threshold.

[0024] The whole sequence control module is further configured to determine that data whole sequence is completed when the target delay value is equal to the ideal delay value.

[0025] Optionally, the whole sequence multiplexing module comprises a preset primitive unit and a primitive control unit.

[0026] The whole sequence control module is further configured to transmit the target delay value to the primitive control unit.

[0027] The primitive control unit is configured to transmit the target delay value to the preset primitive unit.

[0028] The preset primitive unit is configured to determine that data whole sequence is completed when the target delay value is received.

[0029] Optionally, the whole sequence multiplexing module further comprises a frequency divider and a buffer.

[0030] The frequency divider is configured to perform frequency division processing on the data clock to obtain a frequency division clock.

[0031] The buffer is configured to perform differential serial processing on the LVDS data to obtain single-ended data.

[0032] The preset primitive unit is further configured to generate parallel output data according to the frequency division clock and the single-ended data.

[0033] Optionally, the data whole sequence system further comprises a top layer control module.

[0034] The top layer control module is configured to perform reset control on the ADC chip and the whole sequence control module.

[0035] In addition, in order to achieve the above-mentioned purpose, the application further provides a data whole sequence method applied to the data whole sequence system as described above.

[0036] The data whole sequence method comprises the following steps.

[0037] The ADC chip transmits data clock and LVDS data to the whole sequence multiplexing module when the current state is a test mode.

[0038] The whole sequence multiplexing module generates parallel output data according to the data clock and the LVDS data.

[0039] The sorting control module performs data sorting processing on the data of each channel in the parallel output data.

[0040] In this invention, the data reordering system includes: an ADC chip, a reordering and multiplexing module, and a reordering control module. First, when the ADC chip is in test mode, it transmits the data clock and LVDS data to the reordering and multiplexing module. Then, the reordering and multiplexing module generates parallel output data based on the data clock and LVDS data. Finally, the reordering control module performs data reordering processing on each channel of the parallel output data. This invention, by transmitting the data clock and LVDS data to the reordering and multiplexing module when the ADC chip is in test mode, and then performing data reordering processing on each channel of the parallel output data through the reordering control module, allows for the handling of delays in the parallel output data, thereby achieving calibration between the data and the clock, and enabling precise reordering of the LVDS data. Attached Figure Description

[0041] Figure 1 This is a functional block diagram of the first embodiment of the data reordering system of the present invention;

[0042] Figure 2 This is a functional block diagram of the second embodiment of the data reordering system of the present invention;

[0043] Figure 3 This is a flowchart illustrating the first embodiment of the data sorting method of the present invention.

[0044] Explanation of icon numbers:

[0045] Reference Name Reference Name 10 ADC chip 202 Primitive control unit 20 Sequencing multiplexing module 203 Frequency divider 30 Sequencing control module 204 Buffer 201 Preset primitive unit

[0046] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0047] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0048] This invention provides a data reordering system, referring to... Figure 1 , Figure 1 This is a functional block diagram of the first embodiment of the data sorting system of the present invention.

[0049] In this embodiment, the data sorting system includes: an ADC chip 10, a sorting and multiplexing module 20, and a sorting control module 30;

[0050] It should be noted that the ADC chip (analog-to-digital converter) is a converter chip for converting analog signals into digital signals. The specific model of the ADC chip 10 can be set according to actual conditions, and the embodiment does not make specific limitations.

[0051] The ADC chip 10 is configured to transmit data clock and LVDS data to the sequence multiplexing module 20 when the current state is a test mode.

[0052] It should be understood that the ADC chip 10 can be adjusted to the test mode by the ADC chip control module, so that the data clock output by the ADC chip 10 is fixedly and alternately output as 0 and 1. The LVDS data (low voltage differential signaling) is obtained by sampling.

[0053] The sequence multiplexing module 20 is configured to generate parallel output data according to the data clock and the LVDS data.

[0054] It can be understood that the sequence multiplexing module 20 can generate parallel output data according to the data clock and the LVDS data, that is, the data obtained by integrating the data clock and the LVDS data. The parallel output data can be eight bits wide.

[0055] The sequence control module 30 is configured to perform data sequence processing on each channel data in the parallel output data.

[0056] In a specific implementation, the sequence control module 30 can perform data sequence processing on each channel data in the parallel output data, that is, align the clock and the data in the parallel output data. Specifically, the sequence processing can be performed by delaying the clock or delaying the data.

[0057] In the embodiment, the data sequence system includes an ADC chip, a sequence multiplexing module, and a sequence control module. In the embodiment, the data clock and the LVDS data are transmitted to the sequence multiplexing module by the ADC chip when the current state is a test mode. Then, the sequence multiplexing module generates parallel output data according to the data clock and the LVDS data. Finally, the sequence control module performs data sequence processing on each channel data in the parallel output data. In the embodiment, the data clock and the LVDS data are transmitted to the sequence multiplexing module by the ADC chip when the current state is a test mode. Then, the sequence control module performs data sequence processing on each channel data in the parallel output data. The delay of the parallel output data can be processed by the sequence control module, so as to calibrate the data and the clock, and accurately sequence the LVDS data.

[0058] Based on the above Figure 1 The first embodiment shown, the second embodiment of the heart rate detection device of the present application is proposed.

[0059] In the second embodiment, the whole sequence control module 30, also used for obtaining the current delay value from the whole sequence multiplexing module 20;

[0060] It can be understood that in this embodiment, the whole sequence multiplexing module 20 can include ISERDESE3 series primitives in FPGA, which belongs to the official tool provided by FPGA, and the whole sequence control module 30 can obtain the current delay value from the ISERDESE3 series primitives.

[0061] It should be understood that the current delay value is the minimum delay value, that is, the default value, and the delay value obtained in the subsequent process of processing the current delay value cannot be less than the default value.

[0062] The whole sequence control module 30 is also used to determine the ideal delay value according to the current delay value and each channel data in the parallel output data;

[0063] It should be noted that the ideal delay value refers to the delay value required to complete the whole sequence processing, which can be determined according to the current delay value and each channel data in the parallel output data. The ideal delay value corresponding to each channel data in the parallel output data may be the same or different.

[0064] Further, in order to accurately determine the ideal delay value, in this embodiment, the whole sequence control module 30 is also used to compare each channel data in the parallel output data with a preset check value to obtain a comparison result.

[0065] It can be understood that the preset check value refers to a check value set in advance, which can include two preset check values, one of which is a first preset check value corresponding to the low level of the data clock, and the other is a second preset check value corresponding to the high level of the data clock.

[0066] In specific implementation, each channel data in the parallel output data can be compared with the preset check value. The specific comparison method can be to determine whether the clock signal in each channel data is high or low first, then obtain the data corresponding to the low level, compare the data with the first preset check value, when the two are the same, the delay value corresponding to the data is taken as the valid data, when the two are different, it is not recorded, and the comparison result can include all the recorded valid data. The data corresponding to the high level is also compared in the above-mentioned manner, which will not be described in detail in this embodiment.

[0067] The whole sequence control module 30 is also used to add one to the current delay value to obtain a processed delay value.

[0068] It should be understood that after comparing each channel data in the parallel output data with the preset check value, the current delay value needs to be incremented by one to obtain a processed delay value.

[0069] The sequence control module 30 is further configured to return to the step of comparing each channel data in the parallel output data with the preset check value to obtain a comparison result until the processed delay value is equal to the preset delay upper limit value and an effective interval is obtained when the processed delay value is less than the preset delay upper limit value.

[0070] It should be noted that the preset delay upper limit value is a maximum delay value set in advance, which is used to set an upper limit for the variable range of the delay value, and can be set according to actual conditions, which is not limited in the embodiment.

[0071] It should be understood that when the delay value after the increment by one is less than the preset delay upper limit value, the processed delay value needs to be reloaded into the ISERDES E3 series primitive to enable the sequence multiplexing module 20 to generate new parallel output data, and the sequence control module 30 to reacquire the current delay value and perform the comparison process of the new parallel output data with the preset check value again. The comparison process is as described above, and will not be described in detail in the embodiment.

[0072] It should be understood that when the delay value after the increment by one is equal to the preset delay upper limit value, the effective interval can be determined according to all the processed delay values.

[0073] Further, in order to accurately determine the effective interval, in the embodiment, the sequence control module 30 is further configured to return to the step of comparing each channel data in the parallel output data with the preset check value to obtain a comparison result until the processed delay value is equal to the preset delay upper limit value when the processed delay value is less than the preset delay upper limit value.

[0074] It should be understood that when the processed delay value is less than the preset delay upper limit value, the comparison process needs to be re-executed until the processed delay value is equal to the preset delay upper limit value.

[0075] The sequence control module 30 is further configured to obtain all the comparison results when the processed delay value is equal to the preset delay upper limit value.

[0076] The sequence control module 30 is further configured to determine the effective interval according to all the valid data in the all comparison results.

[0077] It should be understood that the valid data can include a plurality of delay values, and the continuous delay values can form intervals, and all the intervals are valid intervals, that is, a plurality of intervals with different sizes are formed, some of which are extremely small valid intervals formed by interference, and some of which are valid intervals that can work normally but have little margin.

[0078] The sequence control module 30 is further configured to determine an ideal delay value according to the valid interval.

[0079] Further, in order to accurately determine the ideal delay value, in the embodiment, the sequence control module 30 is further configured to select a target valid interval with the largest range from the valid intervals.

[0080] It should be understood that the valid interval can include a plurality of intervals with different sizes, and the target valid interval with the largest range can be selected.

[0081] The sequence control module 30 is further configured to compare the target valid interval with a preset delay value valid interval.

[0082] It should be understood that the preset delay value valid interval is a preset valid interval, which can be set according to actual conditions, and the embodiment does not make specific limitation on this. The preset delay value valid interval depends on the requirement of the user for precision. If the requirement for the data anti-interference ability is very strict, the preset delay value valid interval can be set to be very large, but the verification time can be longer, because the valid interval meeting the size can need to be verified multiple times to be sorted out, and there can be no valid interval meeting the size, resulting in unsuccessful sorting.

[0083] The sequence control module 30 is further configured to take the middle value of the target valid interval as the ideal delay value when the target valid interval is greater than the preset delay value valid interval.

[0084] It should be understood that when the target valid interval is greater than the preset delay value valid interval, that is, the target valid interval contains the preset delay value valid interval, the middle value of the target valid interval is taken as the ideal delay value.

[0085] In a specific implementation, when the target valid interval is smaller than the preset delay value valid interval, it indicates that the verification fails, at this time, the delay value in the ISERDESE3 series primitive is set to the default value, and the step of comparing each channel data in the parallel output data with the preset verification value to obtain a comparison result is repeatedly executed until the processed delay value is equal to the preset delay upper limit value, and whether the target valid interval obtained at this time is greater than the preset delay value valid interval is judged, if greater, the ideal delay value can be obtained, and if smaller, the above step needs to be executed again until the target valid interval is greater than the preset delay value valid interval.

[0086] The sequence control module 30 is further configured to perform sequence processing on each channel data in the parallel output data according to the ideal delay value.

[0087] Further, in order to determine whether the sequence processing is completed, in the embodiment, the sequence control module 30 is further configured to subtract the ideal delay value from the processed delay value to obtain a delay value difference.

[0088] It can be understood that the sequence control module 30 can subtract the ideal delay value from the processed delay value to obtain the delay value difference. When the delay value difference is negative, that is, the processed delay value is less than the ideal delay value, the ideal delay value is loaded into the ISERDESE3 series primitive.

[0089] The sequence control module 30 is further configured to subtract a preset threshold from the processed delay value to obtain a target delay value when the delay value difference is greater than the preset threshold.

[0090] It should be noted that the preset threshold is a threshold set in advance, and the specific value is not limited in the embodiment. Specifically, the embodiment can be set to 8.

[0091] It should be understood that when the delay value difference is greater than the preset threshold, the processed delay value also needs to be subtracted by the preset threshold, that is, the processed delay value is subtracted by 8 to obtain the target delay value.

[0092] The sequence control module 30 is further configured to determine that the sequence processing is completed when the target delay value is equal to the ideal delay value.

[0093] It can be understood that it is also necessary to determine whether the target delay value is greater than the preset threshold. If it is greater, the target delay value also needs to be subtracted by 8, and the target delay value is loaded into the ISERDESE3 series primitive. Then the step of comparing each channel data in the parallel output data with the preset check value to obtain a comparison result is continued to be executed until the processed delay value is equal to the preset upper delay value, and it is determined whether the target effective interval obtained at this time is greater than the preset delay value effective interval. If it is greater, the ideal delay value can be obtained. If it is less, the above steps need to be re-executed until the target effective interval is greater than the preset delay value effective interval, until the final obtained delay value is equal to the ideal delay value, and it is determined that the sequence processing is completed.

[0094] In a specific implementation, each channel data in the parallel output data can be simultaneously subjected to sequence processing to complete the sequence processing of the entire parallel output data.

[0095] The embodiment obtains the current delay value from the whole sequence multiplexing module through the whole sequence control module, then determines the ideal delay value according to the current delay value and each channel data in the parallel output data, and then respectively performs the whole sequence processing on each channel data in the parallel output data according to the ideal delay value. The embodiment can change the sampling position of the data and improve the anti-interference ability of the final FPGA sampling data by determining the ideal delay value according to the current delay value and each channel data in the parallel output data, and then adjusting the delay value in the whole sequence multiplexing module according to the ideal delay value.

[0096] Reference Figure 2 , Figure 2 The figure of the functional module of the third embodiment of the data whole sequence system.

[0097] In the embodiment, the whole sequence multiplexing module 20 comprises a preset primitive unit 201 and a primitive control unit 202.

[0098] The whole sequence control module 30 is further configured to transmit the target delay value to the primitive control unit 202.

[0099] The primitive control unit 202 is configured to transmit the target delay value to the preset primitive unit 201.

[0100] The preset primitive unit 201 is configured to determine that the data whole sequence is completed when the target delay value is received.

[0101] It can be understood that the preset primitive unit 201 in the embodiment can be an ISERDESE3 series primitive, and the primitive control unit 202 can be an IDELAYE3 primitive. The ISERDESE3 series primitive and the IDELAYE3 primitive belong to the tools provided by the FPGA official. The primitive control unit 202 can control the preset primitive unit 201 to adjust the delay value in the preset primitive unit 201.

[0102] In the specific implementation, the whole sequence control module 30 can transmit the target delay value when the whole sequence is completed to the primitive control unit 202, and then the primitive control unit 202 can transmit the target delay value to the preset primitive unit 201. When the preset primitive unit 201 receives the target delay value, it is determined that the data whole sequence is completed.

[0103] Further, in the embodiment, the whole sequence multiplexing module 20 further comprises a frequency divider 203 and a buffer 204.

[0104] The frequency divider 203 is configured to perform frequency division processing on the data clock to obtain a frequency division clock.

[0105] It should be understood that the frequency divider 203 can frequency-divide the data clock to obtain a frequency-divided clock, that is, frequency-divide a data clock with a longer time to obtain a frequency-divided clock with a shorter time.

[0106] The buffer 204 is configured to differentially serially process the LVDS data to obtain single-ended data.

[0107] In a specific implementation, since the LVDS data is differential data, it needs to be differentially serially processed to obtain single-ended data.

[0108] The preset primitive unit 201 is further configured to generate parallel output data according to the frequency-divided clock and the single-ended data.

[0109] It can be understood that the sequence alignment multiplexing module 20 can generate parallel output data according to the frequency-divided clock and the single-ended data, that is, data obtained by integrating the frequency-divided clock and the single-ended data, and the parallel output data can be eight bits wide.

[0110] Further, in the embodiment, the data sequence alignment system further includes a top-level control module 40.

[0111] The top-level control module 40 is configured to reset control the ADC chip 10 and the sequence alignment control module 30.

[0112] In a specific implementation, the top-level control module 40 can generate a reset control signal to reset control the ADC chip 10 and the sequence alignment control module 30.

[0113] In the embodiment, the target delay value is first transmitted to the primitive control unit by the sequence alignment control module, then transmitted to the preset primitive unit by the primitive control unit, and then the preset primitive unit determines that the data sequence alignment is completed when the target delay value is received. In the embodiment, the delay value in the preset primitive unit is adjusted by the target delay value, so that the sampling position of the data can be changed, and the anti-interference ability of the final FPGA sampling data can be improved.

[0114] In addition, the embodiment of the application further provides a data sequence alignment method, which is applied to the data sequence alignment system as described above, and the data sequence alignment method will be described in detail below with reference to the accompanying drawings. Figure 3 , Figure 3 FIG. 1 is a flowchart of a first embodiment of the data sequence alignment method of the application.

[0115] As shown in FIG. 1, the data sequence alignment method includes the following steps. Figure 3

[0116] Step S10: When the ADC chip is in a test mode, the data clock and the LVDS data are transmitted to the sequence alignment multiplexing module. ​

[0117] It should be noted that the ADC chip (analog-to-digital converter) is a converter chip for converting analog signals into digital signals. The specific model of the ADC chip can be set according to actual conditions, and the present embodiment does not make specific limitations.

[0118] It should be understood that the ADC chip can be adjusted to a test mode by the ADC chip control module, so that the data clock output by the ADC chip is a fixed serial alternating output of 0 and 1. The LVDS data (low voltage differential signaling) is obtained by sampling.

[0119] Step S20: The whole sequence multiplexing module generates parallel output data according to the data clock and the LVDS data.

[0120] It can be understood that the whole sequence multiplexing module can generate parallel output data according to the data clock and the LVDS data, that is, the data obtained by integrating the data clock and the LVDS data. The parallel output data can be eight bits wide.

[0121] Step S30: The whole sequence control module respectively performs data whole sequence processing on each channel data in the parallel output data.

[0122] In a specific implementation, the whole sequence control module can respectively perform data whole sequence processing on each channel data in the parallel output data, that is, align the clock and data in the parallel output data. Specifically, the whole sequence processing can be performed by delaying the clock or delaying the data.

[0123] The present embodiment first transmits the data clock and the LVDS data to the whole sequence multiplexing module when the ADC chip is in a test mode, then generates parallel output data according to the data clock and the LVDS data by the whole sequence multiplexing module, and then respectively performs data whole sequence processing on each channel data in the parallel output data by the whole sequence control module. The present embodiment transmits the data clock and the LVDS data to the whole sequence multiplexing module when the ADC chip is in a test mode, and then respectively performs data whole sequence processing on each channel data in the parallel output data by the whole sequence control module. The delay of the parallel output data by the whole sequence control module can be processed, so as to realize the calibration between the data and the clock, and accurately sequence the LVDS data.

[0124] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0125] The above-mentioned embodiment numbers of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0126] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and the necessary general hardware platform, and of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for making a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of the present application.

[0127] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied to other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A data sequencing system, comprising: The data sorting system comprises an ADC chip, a sorting multiplexing module and a sorting control module. The ADC chip is configured to transmit data clock and LVDS data to the sorting multiplexing module when the current state is a test mode. The sorting multiplexing module is configured to generate parallel output data according to the data clock and the LVDS data. The sorting control module is further configured to obtain a current delay value from the sorting multiplexing module, the current delay value being the smallest delay value and being a default value. The sorting control module is further configured to compare each channel data in the parallel output data with a preset check value to obtain a comparison result. The sorting control module is further configured to perform one processing on the current delay value to obtain a processed delay value. The sorting control module is further configured to return to the step of comparing each channel data in the parallel output data with a preset check value to obtain a comparison result when the processed delay value is smaller than a preset delay upper limit value, until the processed delay value is equal to the preset delay upper limit value. The sorting control module is further configured to obtain all comparison results when the processed delay value is equal to the preset delay upper limit value. The sorting control module is further configured to determine an effective interval according to all effective data in the all comparison results. The sorting control module is further configured to select a target effective interval with the largest range from the effective interval. The sorting control module is further configured to compare the target effective interval with a preset delay value effective interval. The sorting control module is further configured to take a middle value of the target effective interval as an ideal delay value when the target effective interval is larger than the preset delay value effective interval. The sorting control module is further configured to perform sorting processing on each channel data in the parallel output data according to the ideal delay value.

2. The data sequencing system of claim 1, wherein, The sorting control module is further configured to subtract the ideal delay value from the processed delay value to obtain a delay value difference. The sorting control module is further configured to subtract a preset threshold value from the processed delay value to obtain a target delay value when the delay value difference is larger than the preset threshold value. The sorting control module is further configured to determine that data sorting is completed when the target delay value is equal to the ideal delay value.

3. The data sequencing system of claim 2, wherein, The sorting multiplexing module comprises a preset primitive unit and a primitive control unit. The sorting control module is further configured to transmit the target delay value to the primitive control unit. The primitive control unit is configured to transmit the target delay value to the preset primitive unit. The preset primitive unit is configured to determine that data sorting is completed when the target delay value is received.

4. The data sequencing system of claim 3, wherein, The sorting multiplexing module further comprises a frequency divider and a buffer. The frequency divider is configured to perform frequency division processing on the data clock to obtain a frequency division clock. The buffer is configured to perform differential serial processing on the LVDS data to obtain single-end data. The preset primitive unit is further configured to generate parallel output data according to the frequency division clock and the single-end data.

5. The data sequencing system according to any one of claims 1 to 4, wherein, The data sorting system further comprises a top-level control module. The top layer control module is configured to reset control the ADC chip and the sequence control module.

6. A data sequencing method, characterized by, The data sequence method is applied to the data sequence system of any one of claims 1-5. The data sequence method comprises the following steps: When the ADC chip is in a test mode, the ADC chip transmits data clock and LVDS data to the sequence multiplexing module; The sequence multiplexing module generates parallel output data according to the data clock and the LVDS data; The sequence control module obtains a current delay value from the sequence multiplexing module, and the current delay value is the smallest delay value and is a default value; The sequence control module compares each channel data in the parallel output data with a preset check value to obtain a comparison result; The sequence control module processes the current delay value by adding one to obtain a processed delay value; When the processed delay value is smaller than a preset upper limit delay value, the sequence control module returns to the step of comparing each channel data in the parallel output data with a preset check value to obtain a comparison result until the processed delay value is equal to the preset upper limit delay value; When the processed delay value is equal to the preset upper limit delay value, the sequence control module obtains all comparison results; The sequence control module determines an effective interval according to all valid data in the all comparison results; The sequence control module selects a target effective interval with the largest range from the effective interval; The sequence control module compares the target effective interval with a preset delay value effective interval; When the target effective interval is greater than the preset delay value effective interval, the sequence control module takes a middle value of the target effective interval as an ideal delay value; The sequence control module respectively performs sequence processing on each channel data in the parallel output data according to the ideal delay value.

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