Design method and system of integrated circuit layout, storage medium

Abstract

The application provides a design method and system of an integrated circuit layout, and a storage medium. The design method comprises the following steps: obtaining a circuit diagram of an integrated circuit to be designed, wherein the integrated circuit comprises an input-output unit, the input-output unit comprises an input-output pad and an electrostatic protection circuit, and the electrostatic protection circuit comprises a plurality of functional units; each functional unit is disassembled into at least two sub-units, wherein each sub-unit comprises at least one electrostatic protection device; each sub-unit is physically implemented to obtain a sub-layout corresponding to each sub-unit; the input-output pad and the sub-layout of the sub-unit are spliced to obtain a layout of the corresponding input-output unit; and the layouts of a plurality of input-output units and a layout of a target IP are spliced to obtain a design layout of the integrated circuit. The layout designed by the method of the application has a smaller area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a design method and system of integrated circuit layout, and a storage medium. BACKGROUND

[0002] An integrated circuit mainly includes two parts, i.e., a core circuit and a peripheral input / output (IO) unit. The IO unit of the integrated circuit is an interaction channel between the core circuit and an external environment, and an electrostatic protection circuit is usually arranged on the IO unit. When a very high voltage is applied to the electrostatic protection circuit instantaneously due to static electricity from the outside, the electrostatic protection circuit performs electrostatic discharge through a discharge path to prevent damage to the internal circuit of the integrated circuit.

[0003] The large-scale integrated circuit design of the related art usually implements full-chip electrostatic protection design by means of an input / output (IO) library to realize effective electrostatic discharge protection channels of any two pins. However, since the sizes of the units of the IO library are fixed and the protection capability is fixed, this easily leads to the following problems in the layout of the final design: waste of area, inability to meet the integration requirements of different semiconductor intellectual property (IP) cores, and the like. If the above two shortcomings are improved and the layout is redesigned, it will bring the following problems: increase in design cycle and cost, and increase in the risk of silicon verification.

[0004] Therefore, it is necessary to propose a new design method and system of integrated circuit layout, and a storage medium, to solve at least one of the above technical problems. SUMMARY

[0005] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, and even less to determine the protection scope of the claimed technical solution.

[0006] In view of the existing problems, the present application provides a design method of integrated circuit layout, which comprises:

[0007] obtaining a circuit diagram of an integrated circuit to be designed, wherein the integrated circuit includes an input / output unit, the input / output unit includes an input / output pad and an electrostatic protection circuit, and the electrostatic protection circuit includes a plurality of functional units;

[0008] each of the functional units is disassembled into at least two sub-units, wherein each of the sub-units includes at least one electrostatic protection device;

[0009] physically implementing each of the sub-units to obtain a sub-layout corresponding to each of the sub-units;

[0010] splicing the input-output pad and the sub-layout of the sub-unit to obtain a layout of the corresponding input-output unit;

[0011] splicing the layout of the plurality of input-output units and a layout of a target IP to obtain a design layout of the integrated circuit.

[0012] Exemplarily, the layout of the plurality of input-output units includes at least one first layout and at least one second layout, wherein the first layout has a first width and a first length, the second layout has a second width and a second length, the first width is smaller than the second width, and the first length is greater than the second length.

[0013] Exemplarily, the layout of two input-output units with the same function is different in size and / or shape.

[0014] Exemplarily, physically implementing each of the sub-units to obtain a sub-layout corresponding to each of the sub-units includes:

[0015] determining the size of the corresponding sub-unit according to the size of the target IP to be spliced by each of the input-output units, wherein the layout of the plurality of input-output units located outside at least one edge of the target IP is spliced with each other.

[0016] Exemplarily, the layout of the input-output unit corresponding to different target IPs is different in size and / or shape.

[0017] Exemplarily, the electrostatic protection device includes at least one of a diode, a resistor, and a MOS tube.

[0018] Another aspect of the present application also provides an integrated circuit layout designed by the aforementioned design method.

[0019] Yet another aspect of the present application also provides a design system of an integrated circuit layout, which includes:

[0020] a memory for storing executable program instructions;

[0021] one or more processors for executing the program instructions stored in the memory, so that the processor executes the aforementioned design method.

[0022] The application further provides a computer storage medium, which stores a computer program, and the computer program is executed by a processor to implement the design method.

[0023] The design method of the application can combine each subunit more flexibly, can customize the scheme of electrostatic protection flexibly, and can arrange more shapes and sizes of input and output units, so that the input and output units can be better combined with the layout of the target IP, thereby meeting the compatibility of various IPs, improving the area utilization, shortening the design cycle, reducing the design cost, and reducing the risk of non-silicon verification. BRIEF DESCRIPTION OF DRAWINGS

[0024] The following drawings of the application are used herein as a part of the application to understand the application. The embodiments of the application and the description thereof shown in the drawings are used to explain the principles of the application.

[0025] In the drawings:

[0026] Figure 1 A flow chart of the design method of the integrated circuit layout of one specific embodiment of the application is shown;

[0027] Figure 2 A schematic diagram of the integrated circuit layout obtained by the conventional design method is shown;

[0028] Figure 3 A schematic diagram of the integrated circuit layout obtained by the design method according to the application is shown;

[0029] Figure 4 A schematic diagram of the design system of the integrated circuit layout in one embodiment of the application is shown. DETAILED DESCRIPTION

[0030] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the application. However, it is obvious to those skilled in the art that the application can be implemented without one or more of these details. In other examples, some technical features known in the art are not described in order not to obscure the application.

[0031] It is to be understood that the application can assume various alternative embodiments, and that it is not to be limited to what is presented herein. Rather, the embodiments presented herein are provided to give a thorough and complete disclosure of the application and to fully convey the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals can be used to denote like elements throughout.

[0032] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0033] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0036] For a thorough understanding of the present application, reference should be made to the following detailed description together with the accompanying drawings, in which:

[0037] Reference will now be made to the drawings, wherein: Figures 1 to 3 The design method of the integrated circuit layout of the present application, wherein, Figure 4 A flow chart of the manufacturing method of the semiconductor device of one embodiment of the present application is shown. Figure 1 A flow chart of the design method of the integrated circuit layout of one embodiment of the present application is shown. Figure 2 A schematic diagram of the integrated circuit layout obtained by the conventional design method is shown. Figure 3 A schematic diagram of the integrated circuit layout obtained by the design method according to the present application is shown.

[0038] To solve at least one of the foregoing technical problems, as Figure 1 The present application provides a design method of an integrated circuit layout, comprising the following steps S110 to S150:

[0039] In step S110, a circuit diagram of an integrated circuit to be designed is acquired, wherein the integrated circuit comprises an input-output unit, the input-output unit comprises an input-output pad and the electro-static protection circuit, and the electro-static protection circuit comprises a plurality of functional units;

[0040] In step S120, each of the functional units is disassembled into at least two sub-units, wherein each of the sub-units comprises at least one electro-static protection device;

[0041] In step S130, each of the sub-units is physically implemented to obtain a sub-layout corresponding to each of the sub-units;

[0042] In step S140, the sub-layouts of the sub-units corresponding to each of the functional units are spliced to obtain a layout of the corresponding functional unit;

[0043] In step S150, the layouts of the plurality of functional units and the layout of the input-output pad are spliced to obtain a design layout of the integrated circuit.

[0044] Through the method of the present application, each sub-unit can be more flexibly combined, more shapes and sizes of functional units can be arranged, and thus the layout of the input-output pad can be better combined, thereby meeting the compatibility of various IPs, improving the area utilization rate, shortening the design cycle, reducing the design cost, and reducing the risk of pre-silicon verification.

[0045] In one specific embodiment, in step S110, the circuit diagram of the integrated circuit to be designed can be any circuit diagram, wherein the integrated circuit mainly comprises two parts, i.e., a core circuit and a peripheral input-output (IO) unit. The IO unit of the integrated circuit is an interaction channel between the core circuit and the external environment, and an electro-static protection circuit (ESD) is usually arranged on the IO unit. When a very high voltage is applied to the electro-static protection circuit instantaneously due to static electricity from the outside, the electro-static protection circuit performs electro-static discharge through a discharge path to prevent damage to the internal circuit of the integrated circuit.

[0046] Usually, each chip in an integrated circuit comprises interface pins connected to the external interface of the chip package. Inside the chip package, the pins are connected to metal wires, and the external pins are connected to the input-output pads of the chip through the metal wires. Usually, the IO unit further comprises an input-output pad, an interface unit, and the electro-static protection circuit, wherein the interface unit can be electrically connected to the core circuit of the integrated circuit.

[0047] ESD protection circuit is used for static discharge protection of integrated circuit, human body discharge or machine discharge interference comes from outside, therefore, ESD protection circuit is usually located around the input and output pad, wherein, the static protection circuit can include input ESD, output ESD, power and ground ESD.

[0048] In some embodiments, the static protection circuit includes a plurality of functional units, such as clamping protection circuit, rectifier circuit, filter circuit, etc., wherein each functional unit includes at least two static protection devices, including but not limited to diode, resistor, MOS tube, etc. The design method of IO library is usually used, and the layout size of the physical implementation of each functional unit is fixed, so that the design method of the static protection circuit is relatively fixed when designing the layout, and the protection capability is fixed, which can easily lead to the following problems of the final designed layout: waste area, unable to meet the integration requirements of different semiconductor intellectual property (IP) cores, etc. Therefore, the present application solves these problems through steps S120 to S150.

[0049] Specifically, in step S120, each of the functional units is disassembled into at least two sub-units, wherein each of the sub-units includes at least one static protection device, and each sub-unit can include only one static protection device, or two, three or more static protection devices.

[0050] In some embodiments, in step S130, each of the sub-units is physically implemented to obtain a sub-layout corresponding to each of the sub-units.

[0051] The physical implementation method can be any suitable method, for example, the shape or size of the layout of each sub-unit can be designed according to the type of protection device included in each sub-unit according to the known design rules, combined with the splicing rules of the subsequent functional units.

[0052] For example, each of the sub-units is physically implemented to obtain a sub-layout corresponding to each of the sub-units, including: determining the size of the corresponding sub-unit according to the size of the target IP to be spliced by each of the input and output units, wherein the layouts of a plurality of input and output units located outside at least one edge of the target IP are spliced with each other.

[0053] In some embodiments, in step S140, the input and output pads and the sub-layouts of the sub-units are spliced to obtain a layout of the corresponding input and output unit. The layout of the input and output unit with a predetermined shape or size can be obtained by splicing the sub-layouts of the sub-units.

[0054] The sub-layouts of the sub-units can be arranged according to design requirements, or the spliced ​​sub-layouts can be arranged to minimize the area of ​​the region.

[0055] Optionally, the layouts of two input / output units having the same function may have different sizes and / or different shapes.

[0056] For example, the layout of the plurality of input / output units includes at least one first layout and at least one second layout. The first layout has a first width and a first length, and the second layout has a second width and a second length. The first width is smaller than the second width, and the first length is greater than the second length. This allows some input / output units to be generally long and thin, while others can be wide and flat. This allows for more flexible splicing of sub-units (i.e., fine units) to achieve electrostatic protection while obtaining input / output units with more diverse sizes and shapes. This makes it easier for the input / output units to be compatible with various IPs and to be arranged more reasonably with IPs to achieve a smaller area.

[0057] For example, for the same ESD performance and without considering compatibility, the IO area can be reduced from 100*510 to 120*165 (i.e., elongated type) and 60*365 (wide and flat type), saving more than 40% of the area.

[0058] In some embodiments, in step S150, the layouts of the plurality of input / output units and the layout of the target IP are spliced ​​together to obtain the design layout of the integrated circuit.

[0059] It is worth mentioning that IP (Intellectual Property) refers to a proven, reusable integrated circuit module with specific functions in integrated circuit design. Depending on the different design IP functions, IP can include processor IP, interface IP, memory IP, and other IPs (analog-to-digital IP and digital-to-analog IP).

[0060] In some embodiments, the layout size of the input / output units corresponding to different target IPs is different, and / or the shape of the layout of the input / output units corresponding to different target IPs is different.

[0061] Because the input / output units of this application have more diverse sizes and shapes, they can adapt to more IPs with different shapes and requirements, thus enabling compatibility with various IPs.

[0062] like Figure 2 The diagram shown is an exemplary layout obtained through conventional design methods, while Figure 3The shown is a layout obtained by the design method of the application, from the figure, it can be seen that the shape of the input and output unit in the layout of the application is more diversified, for example, Figure 3 The area of IP1 in the shown is reduced by about 10% compared with Figure 2 The area of IP1 in the shown is reduced by about 10% compared with Figure 3 The area of IP2 in the shown is reduced by about 8% compared with Figure 2 The area of IP2 in the shown is reduced by about 8% compared with Figure 3 The total area of IP3 and IP4 in the shown is reduced by about 20% compared with Figure 2 The total area of IP3 and IP4 in the shown is reduced by about 20% compared with

[0063] In summary, the design method of the application splits the functional unit of the electrostatic protection circuit into smaller sub-units, then physically realizes each sub-unit to obtain a sub-layout corresponding to each sub-unit, and splices the input and output pads and the sub-layout of the sub-unit to obtain a layout corresponding to the input and output unit; splices the layout of the input and output unit and the layout of the target IP to obtain the design layout of the integrated circuit, which can more flexibly combine each sub-unit, can flexibly customize the electrostatic protection scheme, and can arrange more shapes and sizes of input and output units, so as to better combine with the layout of the target IP, thereby meeting the compatibility of various IPs, improving the area utilization rate, shortening the design cycle, reducing the design cost, and reducing the risk of non-silicon verification.

[0064] Further, the application also provides an integrated circuit layout, which can be obtained by the foregoing design method, wherein the integrated circuit layout comprises an IP and an input and output unit located outside the IP.

[0065] Specifically, some details of the integrated circuit layout can be referred to the foregoing description, which will not be repeated here.

[0066] Further, the application also includes an integrated circuit layout design system for implementing the foregoing design method.

[0067] As Figure 4 shown, the integrated circuit layout design system 400 includes one or more processors 401, a display, a memory 402, a communication interface, etc. These components are interconnected by a bus system and / or other forms of connection mechanism (not shown). It should be noted that, Figure 4 The components and structure of the integrated circuit layout design system 400 shown are only exemplary and not limiting, and the integrated circuit layout design system 400 can also have other components and structures as needed.

[0068] The memory 402 is used to store various data generated in the diffraction process and executable programs, such as system programs of the integrated circuit layout design system 400, various application programs or algorithms for implementing various specific functions for storing integrated circuit layout designs. One or more computer program products can be included, and the computer program products can include various forms of computer readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory 402 may, for example, include random access memory (RAM) and / or cache memory 402, etc. The non-volatile memory may, for example, include read-only memory (ROM), a hard disk, a flash memory, etc. In the integrated circuit layout design system, if necessary, the data stored locally can be stored in the memory 402.

[0069] The processor 401 can be a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and can control other components in the integrated circuit layout design system 400 to perform desired functions. For example, the processor 401 can include one or more embedded processors, processor cores, microprocessors, logic circuits, hardware finite state machines (FSMs), digital signal processors (DSPs), graphics processing units (GPUs), or combinations thereof. The processor 401 can be used to execute the program instructions stored in the memory 402, so that the processor 401 performs the relevant steps of the integrated circuit layout design method described above. The details of the steps of the specific design method can be referred to the description above.

[0070] In one example, the integrated circuit layout design system 400 further includes a communication interface (not shown) for communication between various components in the integrated circuit layout design system 400 and between various components of the integrated circuit layout design system 400 and other devices outside the system.

[0071] The communication interface can be an interface of any communication protocol known in the art, such as a wired interface or a wireless interface, wherein the communication interface can include one or more serial ports, USB interfaces, Ethernet ports, WiFi, wired networks, DVI interfaces, device integrated interconnect modules, or other suitable various ports, interfaces, or connections. The design system of the integrated circuit layout can also access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G, 5G, or a combination thereof. In an example embodiment, the communication interface receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication interface further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0072] In an example, the design system of the integrated circuit layout further includes an input device (not shown), which can be a device used by a user to input instructions, and can include one or more of a keyboard, a trackball, a mouse, a microphone, a touch screen, and the like, or other control buttons.

[0073] The design system of the integrated circuit layout of the embodiments of the present application further includes an output device, which can output various information (such as images or sounds) to the outside (such as a user), and can include one or more of a display, a speaker, and the like.

[0074] In the embodiments of the present application, the display of the design system of the integrated circuit layout can be a touch display screen, a liquid crystal display screen, or the like, and can also be a liquid crystal display, a television, or the like, which is independent of the design system of the integrated circuit layout, and can also be a display screen on a mobile phone, a tablet computer, or the like. The display can be used to display information input by a user or information provided to a user, as well as various graphical user interfaces of the design system of the integrated circuit layout, which can be composed of graphics, text, icons, video, and any combination thereof.

[0075] In addition, the embodiments of the present application also provide a computer storage medium having a computer program stored thereon. One or more computer program instructions can be stored on the computer readable storage medium, and the processor can run the program instructions stored by the storage device to implement the functions (implemented by the processor) in the embodiments of the present application herein and / or other desired functions, such as to perform the corresponding steps of the integrated circuit layout design method according to the embodiments of the present application. Various application programs and various data, such as various data used and / or generated by the application programs, can also be stored in the computer readable storage medium.

[0076] For example, the computer storage medium can include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a read only memory (ROM), an erasable programmable read only memory (EPROM), a compact disc read only memory (CD-ROM), a USB memory, or any combination thereof. The computer readable storage medium can be any combination of one or more computer readable storage media.

[0077] Although example embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the example embodiments are only exemplary and are not intended to limit the scope of the present application. Those of ordinary skill in the art can make various changes and modifications of the example embodiments without departing from the scope and spirit of the present application. All such changes and modifications are intended to be within the scope of the present application as claimed.

[0078] Those of ordinary skill in the art can be aware that, in combination with the examples described in the embodiments disclosed in this paper, each unit and algorithm step of the examples can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0079] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the above-described device embodiments are merely illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another device, or some features can be omitted or not executed.

[0080] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the specification.

[0081] Similarly, it is to be understood that the features of the present application that are of a proprietary nature are set forth in the appended claims. In this respect, before the application is disclosed and described, it is to be understood that the application is not limited to the specific embodiments disclosed and described as such may, of course, vary. It is therefore desired that what is claimed be what is literally disclosed and described. It is intended to be understood that the method of the application is not to be construed as reflecting an intent that the application is to be limited to the embodiments described in this detailed description and the claims. Rather, it is intended that the method of the application is to be construed as reflecting an intent that the application is to cover all embodiments falling within the scope of the claims, along with all equivalents thereof. It is intended that the method of the application is to be construed as reflecting an intent that the application is to cover all alternatives, modifications, equivalents, and alternatives falling within the scope of the claims. Accordingly, the specification and figures are to be regarded in an illustrative manner and results are to be understood as not restrictive.

[0082] Those skilled in the art will appreciate that all features described in this specification (including the summary and abstract), and / or depicted in the drawings, can be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed in this specification (including the summary and abstract), and / or depicted in the drawings, is deemed to be illustrative for the present application.

[0083] Furthermore, those skilled in the art will recognize that references in the specification to "one embodiment", "an embodiment", "an example embodiment", "some embodiments", etc., mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "an embodiment" are not necessarily referring to the same embodiment.

[0084] Various component embodiments of the application can be implemented in hardware, or as software modules running in one or more processors, or in combinations thereof. Skilled persons will appreciate that some or all of the functionality of some of the modules according to embodiments of the application can be implemented in practice using a microprocessor or a digital signal processor (DSP). The application can also be implemented as a program (for example, a computer program and a computer program product) for performing part or all of the methods described herein. Such program implementing the application can be stored on a computer readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier medium, or in any other form.

[0085] It should be noted that the foregoing examples have been provided merely for the purpose of explanation and are in no way to be construed as limiting of the present application. While the application has been described with reference to preferred embodiments and illustrations, the preferred embodiments and illustrations provided herein are not the only ways in which the application can be made and practiced. Those skilled in the art will be able to devise numerous alternative embodiments that, although not explicitly described herein, embody the principles of the application and can be made and practiced without departing from the spirit and scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The application can be implemented by means of both hardware and software, and any combination thereof. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word comprising should not be interpreted as being restricted to means including several elements or steps, it does not exclude other elements or steps. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. It is appreciated that certain features of the application, which are, for clarity, described in the context of separate embodiments, can also be provided in combination in a single embodiment. Conversely, various features of the application, which are, for brevity, described in the context of a single embodiment, can also be provided separately or in any suitable sub-combination.

Claims

1. A method of designing an integrated circuit layout, characterized by, The method comprises: obtaining a circuit diagram of an integrated circuit to be designed, wherein the integrated circuit comprises an input-output unit, the input-output unit comprises an input-output pad and an electrostatic protection circuit, and the electrostatic protection circuit comprises a plurality of functional units; disassembling each of the functional units into at least two sub-units, wherein each of the sub-units comprises at least one electrostatic protection device; physically implementing each of the sub-units to obtain a sub-layout corresponding to each of the sub-units; splicing the input-output pad and the sub-layouts of the sub-units to obtain a layout of the corresponding input-output unit; splicing the layouts of a plurality of the input-output units and a layout of a target IP to obtain a design layout of the integrated circuit.

2. The design method of claim 1, wherein, The layouts of the plurality of input-output units comprise at least one first layout and at least one second layout, wherein the first layout has a first width and a first length, the second layout has a second width and a second length, the first width is smaller than the second width, and the first length is greater than the second length.

3. The design method of claim 1, wherein, The layouts of two input-output units having the same function are different in size and / or shape.

4. The design method of claim 1, wherein, The physically implementing each of the sub-units to obtain a sub-layout corresponding to each of the sub-units comprises: determining the size of the corresponding sub-unit according to the size of a target IP to be spliced with each of the input-output units, wherein the layouts of a plurality of the input-output units located outside at least one edge of the target IP are spliced with each other.

5. The design method according to claim 1 or 4, wherein The layouts of the input-output units corresponding to different target IPs are different in size and / or shape.

6. The design method of claim 1, wherein, The electrostatic protection device comprises at least one of a diode, a resistor, and a MOS tube.

7. An integrated circuit layout designed by the design method of any one of claims 1 to 6.

8. A design system of an integrated circuit layout, characterized by comprising: The design system comprises: a memory for storing executable program instructions; one or more processors for executing the program instructions stored in the memory, so that the processor executes the design method of any one of claims 1 to 6.

9. A computer storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the design method of any one of claims 1 to 6.

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