Image writing method, medium, electronic device and FPGA

Abstract

The present application relates to an image writing method, medium, electronic device, and FPGA. The method is applied to the electronic device and includes: scanning each pixel of a sample image and sequentially determining multiple sets of first image writing parameters; the first image writing parameters represent the writing parameters of a pixel in the sample image whose grayscale value is less than a set value; and sequentially transmitting the multiple sets of first image writing parameters to a field programmable gate array (FPGA), so that the FPGA controls an electron gun to write on a target object according to the multiple sets of writing parameters.

Description

Technical Field

[0001] The present application relates to the field of image processing, and in particular to an image writing method, medium, electronic device and FPGA. Background Art

[0002] Image engraving scanning technologies include optical probe scanning and electron beam etching. The principle is to perform scanning motion along the X / Y direction of the object to be engraved based on image information, and to use imaging technology in the Z direction to achieve image engraving. In related technologies, the scanning motion along the X / Y direction of the object to be engraved changes sequentially according to the step resolution, resulting in reduced image engraving efficiency. Summary of the Invention

[0003] Based on this, it is necessary to provide an image writing method, medium, electronic device and field programmable gate array (FPGA) that can improve the efficiency of image writing in order to address the above technical problems.

[0004] A method for writing an image, applied to an electronic device, comprises the following steps:

[0005] Scan each pixel of the sample image and determine multiple sets of first image writing parameters in sequence; the first image writing parameters represent writing parameters of a pixel in the sample image whose gray value is less than a set value;

[0006] The multiple sets of first image writing parameters are sequentially transmitted to the FPGA, so that the FPGA controls the electron gun to write on the target object according to the multiple sets of writing parameters.

[0007] An image writing method, applied to FPGA, includes the following steps:

[0008] Determine multiple sets of second image writing parameters corresponding to the target image from multiple sets of first image writing parameters corresponding to each sample image stored in the cache space; the first image writing parameters represent writing parameters for a pixel point in the sample image whose grayscale value is less than a set value; the second image writing parameters represent writing parameters corresponding to a pixel point in the target image whose grayscale value is less than the set value;

[0009] The electron gun is controlled to start, and two digital to analog converters (DACs) are controlled to work in sequence based on multiple sets of second image writing parameters to write the target image on the target object.

[0010] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements any of the above-mentioned image writing methods.

[0011] An electronic device comprises a memory and a processor. The memory stores a computer program. When the processor executes the computer program, an image writing method applied to the electronic device is implemented.

[0012] An FPGA includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, an image writing method applied to the FPGA is implemented.

[0013] The above-mentioned image writing method, medium, electronic device and FPGA determine multiple sets of first image writing parameters in sequence by scanning each pixel point of the sample image, wherein the first image writing parameter represents the writing parameter of a pixel point in the sample image whose grayscale value is less than the set value, and transmits the multiple sets of first image writing parameters to the FPGA in sequence, so that the FPGA controls the electron gun to write the target object according to the multiple sets of writing parameters. This can reduce the amount of data interaction between the electronic device and the underlying layer, and improve the efficiency of image writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the process of an image writing method in one embodiment;

[0015] Figure 2 is a schematic diagram of a sample image in one embodiment;

[0016] Figure 3 A schematic diagram of setting a scanning path in one embodiment;

[0017] Figure 4 Schematic diagram of the process of an image writing method in one embodiment;

[0018] Figure 5 is a flow chart of an image writing method according to another embodiment;

[0019] Figure 6 Schematic diagram of the implementation process of the image writing method in one embodiment;

[0020] Figure 7 Schematic diagram of the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific implementations described herein are only used to explain this application and are not intended to limit this application.

[0022] The following describes in detail the implementation details of the technical solutions of the embodiments of the present application.

[0023] In one embodiment, an image recording method is provided, which is executed by an electronic device. Figure 1 As shown, the image writing method may include the following steps:

[0024] Step S101 : Scan each pixel of a sample image and determine multiple sets of first image writing parameters in sequence.

[0025] The sample image contains inscribed content. Image engraving refers to engraving an image on a target object. In actual applications, not all pixels of the sample image contain inscribed content. Some pixels contain inscribed content, while others do not. The grayscale value is 0 to 255. The grayscale value of pixels containing inscribed content is less than 255, and the grayscale value of pixels without inscribed content is 255. In the process of image engraving, pixels with grayscale need to be engraved, while pixels with grayscale value of 255 do not need to be engraved. Therefore, pixels with grayscale value of 255 can be skipped and pixels with grayscale value can be directly engraved.

[0026] In practical applications, it is necessary to obtain the writing parameters of the pixels with grayscale in order to realize the writing of the pixels with grayscale. In this embodiment, the writing parameters are determined in the process of scanning each pixel of the sample image. During the scanning process, the first image writing parameters corresponding to the pixels with grayscale in the sample image are determined in sequence. Among them, it is not necessary to determine the first image writing parameters corresponding to the pixels with a grayscale value of 255. Since the number of pixels that need to be processed is reduced, the amount of data interaction between the electronic device and the bottom layer can be reduced. Figure 2 The sample image shown is composed of a total of 25 pixels, among which the grayscale value of the pixels marked as A in the sample image is 255, and there are 10 of them in total, and the grayscale value of the pixels marked as B is less than 255, and there are 15 of them in total. That is to say, for this sample image, only the 15 pixels marked as B need to be written, and the 10 pixels marked as A do not need to be written. In this case, the first image writing parameters corresponding to the 15 pixels marked as B are determined.

[0027] During the scanning process of all pixels of the sample image, the first image writing parameters are sequentially determined until all pixels of the sample image are scanned. In practical applications, the first image writing parameters can indicate the writing location and content of pixels with grayscale values. By using multiple sets of first image writing parameters for a sample image, the sample image can be written on a target object.

[0028] In one embodiment, the writing parameters include three sets of data, the first set of data is the first output voltage of the first DAC, the second set of data is the second output voltage of the second DAC, and the third set of data is the first hold time of the two DACs. Therefore, the writing parameters can be represented by data in the format of: (first output voltage, second output voltage, first hold time).

[0029] In this embodiment, the first output voltage corresponds to the X-axis coordinate of the pixel point, and the second output voltage corresponds to the Y-axis coordinate of the pixel point. The output voltages of the two DACs can control the position of the writing. By setting the first DAC to the first output voltage and the second DAC to the second output voltage, the position to be written on the target object can be located. For example, assuming Figure 2 In the sample image shown, the writing parameters corresponding to the pixel with coordinates (3, 1) are (A1, B1, C1), and the writing parameters corresponding to the pixel with coordinates (3, 2) are (A2, B2, C2). Setting the output voltage of the first DAC to A1 and the output voltage of the second DAC to B1 allows positioning at the position on the target object corresponding to the pixel with coordinates (3, 1) in the sample image. Setting the output voltage of the first DAC to A2 and the output voltage of the second DAC to B2 allows positioning at the position on the target object corresponding to the pixel with coordinates (3, 2) in the sample image. In practical applications, the first and second output voltages are calculated based on the target object's motion resolution and the image writing size.

[0030] In this embodiment, the first holding time of the two-way DAC can control the etching time of the electron beam at the current etching position, and can also be understood as the residence time of the electron beam emitted by the electron gun at the current writing position. In practical applications, the first holding time of the two-way DAC depends on the grayscale value of the pixel being written. When the grayscale values ​​of the pixel being written are different, the first holding time of the two-way DAC also changes accordingly. The smaller the grayscale value of the pixel being written, the longer the first holding time of the two-way DAC will be. For example, the grayscale value of the pixel with coordinates (3, 1) is smaller than the grayscale value of the pixel with coordinates (3, 2), that is, the electron gun needs to stay at the position of the pixel with coordinates (3, 1) for a longer time than the stay at the position of the pixel with coordinates (3, 2). Therefore, it can be obtained that the writing parameter C1 corresponding to the pixel with coordinates (3, 1) is greater than the writing parameter C2 corresponding to the pixel with coordinates (3, 2).

[0031] In one embodiment, the electronic device scans each pixel in the sample image according to the set scanning path, wherein the reference Figure 3 Detailed description of setting the scan path. Figure 3The sample image and the set scanning path corresponding to the sample image are shown. The resolution of the sample image is 5*5, and it consists of 5 rows of pixels and 5 columns of pixels. The scanning path is set to start with the first pixel in the fifth row of pixels of the sample image, that is, the pixel with coordinates (1, 1) is used as the starting point of the scanning path. The first pixel in the fifth row of pixels of the sample image is scanned first, and then the second pixel in the last row of pixels of the sample image (that is, the pixel with coordinates (2, 1)) is scanned. And so on, the scanning of the fifth row of pixels is completed. In the set scanning path, the scanning directions of the two adjacent rows of pixels are opposite, that is, the scanning order of the pixels in the fifth row is from the first pixel to the last pixel, that is, the scanning of the pixels in the fifth row is achieved in the order from the pixel with coordinates (1, 1) to the pixel with coordinates (5, 1). Then the scanning order of the pixels in the fourth row is from the last pixel to the first pixel, that is, the scanning of the pixels in the fourth row is achieved in the order from the pixel with coordinates (5, 2) to the pixel with coordinates (1, 2). And so on, the scanning of all the pixels in the sample image is finally completed.

[0032] In the above embodiment, the sample image is scanned according to the set scanning order. During the process of engraving the target object, when the engraving of one row of pixels is completed and the engraving of the next row of pixels is switched, the movement of the target object will not change suddenly, thereby improving the quality of image engraving.

[0033] Step S102 : transmitting multiple sets of first image writing parameters to the FPGA in sequence.

[0034] By scanning each pixel point of the sample image, multiple sets of first image writing parameters corresponding to the sample image can be obtained. The electronic device transmits the multiple sets of first image writing parameters to the FPGA. The FPGA can control the operation of the electron gun through the multiple sets of first image writing parameters, so that the sample image can be written on the target object. Among them, the transmission of the first image writing parameters can be achieved through two transmission methods.

[0035] In one transmission method, after the scanning is completed, multiple sets of first image writing parameters can be transmitted to the FPGA in sequence according to the generation order of the first image writing parameters. For example, referring to Figure 2The pixel distribution of the sample image shown in the figure, in the process of scanning all the pixel points of the sample image according to the set scanning path, a group of first image writing parameters corresponding to the pixel point with coordinates (3, 1), a group of first image writing parameters corresponding to the pixel point with coordinates (3, 2), and other groups of first writing parameters can be obtained in sequence. After completing the scanning of all the pixel points of the sample image, the group of first image writing parameters corresponding to the pixel point with coordinates (3, 1) can be first transmitted to the FPGA, and then the group of first image writing parameters corresponding to the pixel point with coordinates (3, 2) can be transmitted to the FPGA.

[0036] In another transmission mode, each set of first image writing parameters can be immediately transmitted to the FPGA when it is generated. For example, when the first image writing parameters are scanned, Figure 2 When the coordinates of the sample image shown are the pixel point (3, 1), a corresponding set of first image writing parameters can be determined, and the set of first image writing parameters corresponding to the pixel point with coordinates (3, 1) can be immediately transmitted to the FPGA. When the pixel point with coordinates (3, 2) is scanned, a corresponding set of first image writing parameters can be determined, and the set of first image writing parameters corresponding to the pixel point with coordinates (3, 2) can be immediately transmitted to the FPGA.

[0037] In one embodiment, referring to Figure 4 As shown, when scanning each pixel of the sample image, it also includes:

[0038] Step S401: determining the grayscale value of a pixel currently being scanned.

[0039] Step S402 : When the grayscale value of a currently scanned pixel is the set value, scan the next pixel.

[0040] During the writing process, it is not necessary to write pixels with preset grayscale values. Therefore, it is not necessary to determine the writing parameters of pixels with preset grayscale values. The preset value is 255. During the scanning of the sample image, when a pixel point of the sample image is scanned, the grayscale value of the currently scanned pixel point is first confirmed. If the grayscale value of the currently scanned pixel point is 255, the next pixel point of the sample image is scanned.

[0041] In another embodiment, if the grayscale value of the currently scanned pixel is less than 255, a set of first image writing parameters corresponding to the currently scanned pixel is determined, and the process continues until all pixels of the sample image are scanned, thereby obtaining multiple sets of first image writing parameters for the sample image. In practical applications, when scanning a pixel, it is possible to directly determine whether the grayscale value of the currently scanned pixel is 255. If the grayscale value of the currently scanned pixel is 255, scanning the next pixel of the sample image continues. If the grayscale value of the currently scanned pixel is not 255, a set of first image writing parameters corresponding to the pixel is obtained.

[0042] In the above embodiment, the electronic device determines multiple sets of first image writing parameters in sequence by scanning each pixel point of the sample image, wherein the first image writing parameters represent the writing parameters of a pixel point in the sample image whose grayscale value is less than the set value, and transmits the multiple sets of first image writing parameters to the FPGA in sequence, so that the FPGA controls the electron gun to write the target object according to the multiple sets of writing parameters. Since only the writing parameters of a pixel point in the sample image whose grayscale value is less than the set value are obtained, the data processing amount of the electronic device can be reduced, and the data interaction amount between the electronic device and the bottom layer can be reduced.

[0043] In one embodiment, another image writing method is provided, which is applied to FPGA. Figure 5 As shown, the image writing method may include the following steps:

[0044] Step S501 : determining a plurality of sets of second image writing parameters corresponding to a target image from a plurality of sets of first image writing parameters corresponding to each sample image stored in a cache space.

[0045] Here, the FPGA can receive multiple sets of first image writing parameters corresponding to different sample images sent by the electronic device, and store the multiple sets of first image writing parameters corresponding to each sample image in the cache space, so that the FPGA can complete the writing of different sample images. The cache space can be DDR3, and the DDR3 is divided into multiple storage areas. Each storage area can store multiple sets of first image writing parameters corresponding to a sample image. For example, the DDR3 is divided into multiple storage areas, and the multiple sets of first image writing parameters corresponding to the sample image A received by the FPGA are stored in the first storage area on the DDR3, and the multiple sets of first image writing parameters corresponding to the sample image B received by the FPGA are stored in the second storage area on the DDR3. Since the cache space stores the writing parameters corresponding to the sample image A and the writing parameters corresponding to the sample image B at the same time, the FPGA supports the writing of sample image A and sample image B.

[0046] In practical applications, the storage order of multiple sets of first image writing parameters is limited, wherein the storage order of the multiple sets of first image writing parameters is the same as the generation order of the multiple sets of first image writing parameters. In one method of receiving multiple sets of first image writing parameters corresponding to a sample image, the FPGA can sequentially and continuously receive the multiple sets of first image writing parameters corresponding to the sample image sent in the order of generation. When storing the multiple sets of first image writing parameters corresponding to the sample image, the FPGA also needs to store them in the order of receipt. In another method of receiving multiple sets of first image writing parameters corresponding to a sample image, the electronic device sends the first set of first image writing parameters generated earlier to the FPGA. The FPGA first receives the first set of first image writing parameters generated earlier for the sample image. After a short interval, the electronic device sends the next set of first image writing parameters generated later to the FPGA. The FPGA then receives the next set of first image writing parameters generated later for the sample image. In this receiving method, the FPGA stores the received set of first image writing parameters in the cache space within the interval. The order of the multiple sets of first image writing parameters for the sample image ultimately stored in the cache space is consistent with the order in which the first image writing parameters were received.

[0047] When performing image writing, since the FPGA's buffer space stores writing parameters for different sample images, it is necessary to determine multiple sets of first image writing parameters corresponding to the sample images to be written from multiple sample images in the FPGA's cache space. In actual applications, a user can select a sample image to be written on an electronic device, and the FPGA can receive a start-write instruction issued by the electronic device. The start-write instruction carries a target image, that is, the sample image to be written selected by the user. Based on the start-write instruction, the FPGA determines multiple sets of second image writing parameters for the target writing image in the cache space. For example, the FPGA's cache space stores multiple sets of first image writing parameters corresponding to sample image A received from the electronic device and multiple sets of first image writing parameters corresponding to sample image B. The FPGA can also receive a start-write instruction issued by the electronic device. Based on the start-write instruction, the FPGA determines the multiple sets of first image writing parameters corresponding to sample image A stored in the cache space as the multiple sets of second image writing parameters corresponding to the target image.

[0048] It should be noted that the first image writing parameters refer to multiple sets of image writing parameters of the sample image sent by the electronic device received by the FPGA, and the second image writing parameters refer to multiple sets of image writing parameters of the target image that the FPGA needs to write, wherein the target image is one of the multiple sample images stored in the cache space. Assuming that the sample image A in the designated cache space is the target image, the multiple sets of second image writing parameters of the target image are essentially consistent with the multiple sets of first image writing parameters of the sample image A stored in the cache space. That is, for the same image, the multiple sets of second image writing parameters are the same as the multiple sets of first image writing parameters. The use of the first image writing parameters and the second image writing parameters for representation is to distinguish the multiple sets of image writing parameters of the stored sample image from the multiple sets of image writing parameters of the target image that need to be written.

[0049] The sample image / target image contains pixels of different grayscale values. For example, the grayscale value range is 0 to 255. The pixels in the image can be divided into two types: the first type of pixels are pixels with grayscale values ​​less than 255, and the second type of pixels are pixels with grayscale values ​​of 255. During the image writing process, the first type of pixels contain writing content, while the second type of pixels do not. Therefore, image writing can be completed based on the writing parameters of the first type of pixels. In this embodiment, the multiple sets of first image writing parameters corresponding to the sample images stored in the cache space are the writing parameters corresponding to the pixels with grayscale values ​​less than 255 in the sample images. Similarly, the second image writing parameters corresponding to the target image confirmed from the cache space are the writing parameters corresponding to the pixels with grayscale values ​​less than 255 in the target image.

[0050] Step S502 , controlling the electron gun to start, and controlling the two DACs to work in sequence based on multiple sets of the second image writing parameters.

[0051] During the image writing process, the FPGA can control the start-up of the electron gun. The started electron gun can evenly emit an electron beam during the image writing process, and the target image can be written on the target object through the electron gun.

[0052] When performing image writing, it is necessary to obtain the writing location and content. The second image writing parameter can indicate the writing location and content. In the order of multiple sets of second image writing parameters, the two DACs are controlled to operate based on the multiple sets of second image writing parameters in sequence until the electron gun has executed all the second image writing parameters, completing the image writing. The second image writing parameters are the writing parameters for pixels in the target image whose grayscale values ​​are less than the preset value. During the process of performing image writing based on multiple sets of second image writing parameters, the position of the pixel with grayscale can be directly located and written. The FPGA can control the first DAC to directly skip the pixels that do not need to be written, thereby improving the efficiency of image writing.

[0053] The following is a specific example. Assuming there are a set of second image writing parameters for pixel A of a target image and a set of second image writing parameters B for pixel B, where the set of second image writing parameters for pixel A comes before the set of second image writing parameters for pixel B, during image writing, the two DACs are first controlled to operate based on the set of second image writing parameters for pixel A, completing the writing of pixel A in the target image on the target object. Then, the two DACs are controlled to operate based on the set of second image writing parameters for pixel B, completing the writing of pixel B in the target image on the target object. In practical applications, writing to the target object sequentially according to the order of multiple sets of second image writing parameters can avoid misalignment during the writing process and improve the quality of image writing.

[0054] In this embodiment, the multi-process parallel logic of the FPGA can ensure that the voltage changes and outputs of the two DACs are completely synchronous, thereby accurately locating the writing position and improving the image writing effect.

[0055] In one embodiment, a set of second image writing parameters includes a third output voltage of the first DAC, a fourth output voltage of the second DAC, and second holding times of the two DACs.

[0056] The third output voltage of the first DAC corresponds to the X-axis coordinate of the pixel point, and the fourth output voltage of the second DAC corresponds to the Y-axis coordinate of the pixel point. Therefore, the output voltage of the first DAC and the output voltage of the second DAC can determine the writing position. In this embodiment, according to a set of second image writing parameters, the output voltage of the first DAC is controlled to be the third output voltage of the second image writing parameter, and the output voltage of the second DAC is controlled to be the fourth output voltage of the second image writing parameter, so that the current writing position can be located to depict the image. Figure 2Taking the sample image shown as an example, assuming that the second image writing parameters corresponding to the pixel with coordinates (3, 1) are (A1, B1, C1), and the second image writing parameters corresponding to the pixel with coordinates (3, 2) are (A2, B2, C2), setting the output voltage of the first DAC to A1 and the output voltage of the second DAC to B1, the position of the pixel with coordinates (3, 1) on the target object can be located. Setting the output voltage of the first DAC to A2 and the output voltage of the second DAC to B2, the position of the pixel with coordinates (3, 2) on the target object can be located. The second holding time of the two DACs is related to the grayscale value of the pixel, which corresponds to the electron beam etching time of the current writing position. Among them, the smaller the grayscale value of the pixel, the longer the second holding time, which means that the electron gun stays at the current time longer, so that the electron beam of the electron gun can obtain a writing effect consistent with the grayscale value of the pixel on the target object through a longer etching time. For example, the writing parameter C1 corresponding to the pixel with coordinates (3, 1) is greater than the writing parameter C2 corresponding to the pixel with coordinates (3, 2), that is, the electron gun stays at the position of the pixel with coordinates (3, 1) for a longer time than the stay at the position of the pixel with coordinates (3, 2), so that the grayscale value of the position of the engraved pixel (3, 1) can be smaller than the grayscale value of the position of the pixel with coordinates (3, 2).

[0057] The following describes in detail how FPGA controls the operation of two DACs. The target image is Figure 2 In the sample image shown, when writing an image on a target object, the pixel with coordinates (3, 1) is first written. Assuming that the set of second image writing parameters corresponding to the pixel with coordinates (3, 1) includes a third output voltage A1, a fourth output voltage B1, and a second hold time C1, then when writing the target image on the target object, the output voltage of the first DAC is set to the third output voltage A1, and the output voltage of the second DAC is set to the fourth output voltage B1. This allows the pixel with coordinates (3, 1) to be located on the target object. At the same time, the output voltages of the first DAC and the second DAC are held for the second set time C1, allowing the pixel with coordinates (3, 1) on the target object to be written. After the second set time C1 is reached, the next pixel is written according to the set of second image writing parameters corresponding to the pixel with coordinates (3, 2).

[0058] After the image is written, the FPGA controls the electron beam to turn off and moves the target object to the starting position. In actual applications, the FPGA also provides feedback to the electronic device on the completion status.

[0059] Reference Figure 6As shown, Figure 6 A schematic diagram of the implementation process of an image writing method is shown.

[0060] In step S601, the electronic device scans the pixels of the sample image according to the set scanning path, and determines multiple sets of first image writing parameters, wherein each set of first image writing parameters records the writing parameters of a pixel point in the sample image whose grayscale value is less than the set value, and a set of first image writing parameters includes the first output voltage of the first DAC, the second output voltage of the second DAC, and the first holding time of the two DACs.

[0061] In step S602 , the electronic device sends multiple sets of first image writing parameters of the sample image to the FPGA.

[0062] In step S603 , the FPGA stores the multiple sets of first image writing parameters of the sample image into a cache space.

[0063] Step S604: The electronic device sends a start-write instruction to the FPGA, wherein the write instruction indicates a target image to be written.

[0064] In step S605 , the FPGA determines multiple sets of second writing parameters of the target image in the cache space according to the start-up writing instruction.

[0065] Step S606, start the electron gun, and control the operation of the two DACs in sequence according to multiple sets of second writing parameters of the target image, and write the target image on the target object, wherein the second writing parameters include the third output voltage of the first DAC, the fourth output voltage of the second DAC and the second holding time of the two DACs. During the second holding time, the output voltage of the first DAC is controlled to be the third output voltage, and the output voltage of the second DAC is controlled to be the fourth output voltage. After the second holding time is reached, the operation of the two DACs is controlled according to the next set of second writing parameters until the image writing is completed.

[0066] Step S607: After the image is written, the electron gun is turned off and the target object is moved to the initial position.

[0067] Step S608: FPGA uploads a writing completion instruction to the electronic device.

[0068] In the above embodiment, the FPGA determines the multiple sets of second image writing parameters corresponding to the target image from the multiple sets of first image writing parameters corresponding to each sample image stored in the cache space, controls the start-up of the electron gun, and controls the two DACs to work in sequence based on the multiple sets of second image writing parameters, so that the FPGA can completely synchronously control the voltage changes and outputs of the two DACs, thereby improving the quality of image writing. At the same time, when performing image writing, the FPGA can directly write pixels with grayscale and skip pixels that do not need to be written, thereby improving the efficiency of image writing.

[0069] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, an image writing method applied to an electronic device or an image writing method applied to an FPGA is implemented.

[0070] In one embodiment, an electronic device is provided, the internal structure of which can be as follows Figure 7 As shown, the electronic equipment includes:

[0071] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0072] The processor 2 is connected to the communication interface 1 to implement information exchange with other devices and is used to execute the image writing method provided by one or more of the above technical solutions when running a computer program. The computer program is stored in the memory 3.

[0073] Of course, in actual application, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 7 Various buses are labeled as bus system 4.

[0074] The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program used to operate on the electronic device.

[0075] The method disclosed in the above-mentioned embodiment of the present application can be applied to processor 2 or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above-mentioned method can be completed by the integrated logic circuit of the hardware in processor 2 or instructions in the form of software. The above-mentioned processor 2 can be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the above-mentioned method in combination with its hardware.

[0076] When the processor 2 executes the program, the corresponding processes in the various methods of the embodiments of the present application are implemented. For the sake of brevity, they are not repeated here.

[0077] In one embodiment, an FPGA is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, an image writing method applied to the FPGA is implemented.

[0078] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or currently unidentified medium used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0079] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An image writing method, characterized in that: Applied to electronic equipment, the method comprises the following steps: Scan each pixel of the sample image and sequentially determine multiple sets of first image writing parameters; the first image writing parameters represent the writing parameters of a pixel in the sample image whose grayscale value is less than a set value; each set of the writing parameters includes a first output voltage of a first digital-to-analog converter (DAC), a second output voltage of a second DAC, and a first hold time of the two DACs; the first output voltage corresponds to the X-axis coordinate of the pixel, and the second output voltage corresponds to the Y-axis coordinate of the pixel; the output voltages of the two DACs are used to control the writing position; the first output voltage and the second output voltage are calculated based on the motion resolution of the target object and the image writing size; The plurality of sets of the first image writing parameters are sequentially transmitted to a field programmable gate array (FPGA), so that the FPGA controls the electron gun to write on the target object according to the plurality of sets of the writing parameters.

2. The image writing method according to claim 1, characterized in that: The step of scanning each pixel point of the sample image and sequentially determining multiple sets of first image writing parameters includes: Scan each pixel of the sample image according to a set scanning path, and determine multiple sets of the first image writing parameters in sequence; wherein the starting point of the set scanning path is the first pixel of the last row of the sample image, and the scanning directions of two adjacent rows of pixels are opposite.

3. The image writing method according to any one of claims 1-2, characterized in that: When scanning each pixel point of the sample image, the method further includes: Determine the grayscale value of a pixel currently being scanned; When the grayscale value of the currently scanned pixel is the set value, the next pixel is scanned.

4. The image writing method according to claim 3, characterized in that: Determining multiple sets of first image writing parameters in sequence, including: When the grayscale value of the currently scanned pixel point is less than the set value, a set of the first image writing parameters of the currently scanned pixel point is determined.

5. An image writing method, characterized in that: Applied to FPGA, the method comprises the following steps: Determine multiple sets of second image writing parameters corresponding to the target image from multiple sets of first image writing parameters corresponding to each sample image stored in the cache space; the first image writing parameters represent the writing parameters of a pixel point in the sample image whose grayscale value is less than a set value; the second image writing parameters represent the writing parameters corresponding to a pixel point in the target image whose grayscale value is less than a set value; wherein the second image writing parameters include the third output voltage of the first DAC, the fourth output voltage of the second DAC, and the second hold time of the two DACs; the third output voltage corresponds to the X-axis coordinate of the pixel point, the fourth output voltage corresponds to the Y-axis coordinate of the pixel point, and the output voltages of the two DACs are used to control the writing position; the third output voltage and the fourth output voltage are calculated based on the motion resolution of the target object and the image writing size; The electron gun is controlled to start, and the two DACs are controlled to work in sequence based on the multiple sets of the second image writing parameters, so as to write the target image on the target object.

6. The image writing method according to claim 5, characterized in that: When controlling the two DACs to operate sequentially based on multiple sets of the second image writing parameters, the method further includes: During the second holding time of the second image writing parameter, the output voltage of the first DAC is controlled to be the third output voltage of the second image writing parameter, and the output voltage of the second DAC is controlled to be the fourth output voltage of the second image writing parameter.

7. A computer-readable storage medium, characterized in that A computer program is stored thereon, which implements the steps of the image writing method according to any one of claims 1 to 4 when executed by a processor, or implements the steps of the image writing method according to any one of claims 5 to 6 when executed.

8. An electronic device, characterized in that: The method comprises a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the image writing method according to any one of claims 1 to 4 is implemented.

9. An FPGA, characterized in that: The method comprises a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the image writing method according to any one of claims 5 to 6 are implemented.

Images