Data writing method, memory storage device, and memory control circuit unit

Abstract

The present application provides a data writing method, a memory storage device and a memory control circuit unit. The method comprises: receiving a write instruction from a host system, wherein the write instruction comprises first data; checking a state of a first physical programmed unit in a first physical erase unit; and in response to the state of the first physical programmed unit being a first state, sending a first instruction sequence, wherein the first instruction sequence is used to instruct a rewritable non-volatile memory module to store at least part of the first data into the first physical programmed unit. Thus, repeated writing to a specific physical programmed unit can be effectively avoided, thereby reducing the correctness of the written data.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a data writing method, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] Traditionally, write operations in rewritable non-volatile memory modules are performed in units of one or more physical pages. However, in practice, when writing data to a physical page (also known as the first physical page), a word line short may occur, affecting other physical pages (also known as second physical pages) and causing them to be unexpectedly written with data. Subsequently, when this second physical page is actually used to store data, it will be repeatedly written, thus reducing the accuracy of data subsequently stored in the second physical page. Summary of the Invention

[0004] The present invention provides a data writing method, a memory storage device, and a memory control circuit unit, which can improve the above-mentioned problems.

[0005] An exemplary embodiment of the present invention provides a data writing method for a rewritable non-volatile memory module, the rewritable non-volatile memory module including a plurality of physical erasure units, the plurality of physical erasure units including a first physical erasure unit, the data writing method comprising: receiving a write instruction from a host system, wherein the write instruction includes first data; checking the state of a first physical programmable unit in the first physical erasure unit before storing the first data; and sending a first instruction sequence in response to the state of the first physical programmable unit being a first state, wherein the first instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the first physical programmable unit.

[0006] In an exemplary embodiment of the present invention, the data writing method further includes: determining the total number of the first entity programmable units based on the amount of the first data.

[0007] In an exemplary embodiment of the present invention, the plurality of entity erasure units further includes a second entity erasure unit, and the data writing method further includes: in response to the state of the first entity programming unit being non-the first state, sending a second instruction sequence, wherein the second instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the second entity erasure unit.

[0008] In an exemplary embodiment of the present invention, the data writing method further includes: in response to the state of the first entity programmable unit being other than the first state, sending a third instruction sequence, wherein the third instruction sequence is used to instruct the rewritable non-volatile memory module to move at least a portion of the data in the first entity erase unit to the second entity erase unit.

[0009] In an exemplary embodiment of the present invention, the step of checking the state of the first entity programmed unit in the first entity erase unit includes: sending a fourth instruction sequence, wherein the fourth instruction sequence is used to instruct the rewritable non-volatile memory module to perform a read operation on the first entity programmed unit to obtain state data corresponding to the first entity programmed unit, wherein the state data reflects the state of at least a portion of the storage units in the first entity programmed unit; and determining the state of the first entity programmed unit based on the state data.

[0010] In an exemplary embodiment of the present invention, the step of determining the state of the first entity programmable unit based on the state data includes: determining, based on specific data in the state data, that the state of the first entity programmable unit is not the first state, wherein the specific data reflects that at least one storage unit in the first entity programmable unit is not in an erased state.

[0011] In an exemplary embodiment of the present invention, the first entity programmable unit includes P storage units, and the state data reflects the state of Q storage units in the first entity programmable unit, where Q is less than P.

[0012] In an exemplary embodiment of the present invention, the step of checking the state of the first entity programming unit in the first entity erasure unit includes: checking whether there is a storage unit in the first entity programming unit that is not in the erasure state; and in response to the existence of a storage unit in the first entity programming unit that is not in the erasure state, determining that the state of the first entity programming unit is not the first state.

[0013] An exemplary embodiment of the present invention provides a memory storage device, comprising a host interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The host interface unit is configured to connect to a host system. The rewritable non-volatile memory module includes a plurality of physical erasure units. The plurality of physical erasure units includes a first physical erasure unit. The memory control circuit unit is connected to the host interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: receive a write instruction from the host system, wherein the write instruction includes first data; check the state of a first physical programmable unit in the first physical erasure unit before storing the first data; and, in response to the state of the first physical programmable unit being a first state, send a first instruction sequence, wherein the first instruction sequence instructs the rewritable non-volatile memory module to store at least a portion of the first data into the first physical programmable unit.

[0014] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: determine the total number of the first entity programmable units based on the amount of the first data.

[0015] In an exemplary embodiment of the present invention, the plurality of entity erasure units further includes a second entity erasure unit, and the memory control circuit unit is further configured to: in response to the state of the first entity programming unit being non-the first state, send a second instruction sequence, wherein the second instruction sequence is configured to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the second entity erasure unit.

[0016] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: in response to the state of the first physical programmable unit being other than the first state, send a third instruction sequence, wherein the third instruction sequence is configured to instruct the rewritable non-volatile memory module to move at least a portion of the data in the first physical erase unit to the second physical erase unit.

[0017] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to check the state of the first physical programmable unit in the first physical erase unit includes: sending a fourth instruction sequence, wherein the fourth instruction sequence is used to instruct the rewritable non-volatile memory module to perform a read operation on the first physical programmable unit to obtain state data corresponding to the first physical programmable unit, wherein the state data reflects the state of at least a portion of the memory cells in the first physical programmable unit; and determining the state of the first physical programmable unit based on the state data.

[0018] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to determine the state of the first physical programmable unit based on the state data includes: determining, based on specific data in the state data, that the state of the first physical programmable unit is not the first state, wherein the specific data reflects that at least one memory unit in the first physical programmable unit is not in an erased state.

[0019] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to check the state of the first entity programming unit in the first entity erase unit includes: checking whether there is a memory cell in the first entity programming unit that is not in the erase state; and determining that the state of the first entity programming unit is not the first state in response to the existence of a memory cell in the first entity programming unit that is not in the erase state.

[0020] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical erasure units, including a first physical erasure unit. The memory control circuit unit includes a host interface, a memory interface, a buffer memory, and a memory management circuit. The host interface is connected to a host system. The memory interface is connected to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the buffer memory. The memory management circuit is configured to: receive a write instruction from the host system, wherein the write instruction includes first data; check the state of a first physical programmable unit in the first physical erasure unit before storing the first data; and, in response to the state of the first physical programmable unit being a first state, send a first instruction sequence, wherein the first instruction sequence instructs the rewritable non-volatile memory module to store at least a portion of the first data into the first physical programmable unit.

[0021] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: determine the total number of the first entity programmable units based on the amount of data in the first data.

[0022] In an exemplary embodiment of the present invention, the plurality of entity erasure units further includes a second entity erasure unit, and the memory management circuit is further configured to: in response to the state of the first entity programming unit being non-the first state, send a second instruction sequence, wherein the second instruction sequence is configured to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the second entity erasure unit.

[0023] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: in response to the state of the first physical programmable unit being other than the first state, send a third instruction sequence, wherein the third instruction sequence is configured to instruct the rewritable non-volatile memory module to move at least a portion of the data in the first physical erase unit to the second physical erase unit.

[0024] In an exemplary embodiment of the present invention, the operation of the memory management circuit to check the state of the first physical programmable unit in the first physical erase unit includes: sending a fourth instruction sequence, wherein the fourth instruction sequence is used to instruct the rewritable non-volatile memory module to perform a read operation on the first physical programmable unit to obtain state data corresponding to the first physical programmable unit, wherein the state data reflects the state of at least a portion of the memory cells in the first physical programmable unit; and determining the state of the first physical programmable unit based on the state data.

[0025] In an exemplary embodiment of the present invention, the operation of the memory management circuit to determine the state of the first physical programmable unit based on the state data includes: determining, based on specific data in the state data, that the state of the first physical programmable unit is not the first state, wherein the specific data reflects that at least one memory unit in the first physical programmable unit is not in an erased state.

[0026] In an exemplary embodiment of the present invention, the operation of the memory management circuit to check the state of the first entity programming unit in the first entity erase unit includes: checking whether there is a memory cell in the first entity programming unit that is not in the erase state; and in response to the existence of a memory cell in the first entity programming unit that is not in the erase state, determining that the state of the first entity programming unit is not the first state.

[0027] Based on the above, the data writing method, memory storage device, and memory control circuit unit provided in this embodiment of the invention can check the state of the first physical programmed unit before writing data to it. If the state of the first physical programmed unit meets expectations (i.e., the state of the first physical programmed unit is the first state), a first write operation can be performed on the first physical programmed unit to store the first data in the first physical programmed unit. This effectively avoids repeatedly writing to a specific physical programmed unit, thereby reducing the accuracy of the written data. Attached Figure Description

[0028] Figure 1This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram illustrating a usage scenario of a memory storage device according to an exemplary embodiment of the present invention;

[0035] Figure 8A This is a schematic diagram of a first write operation as shown in an exemplary embodiment of the present invention;

[0036] Figure 8B This is a schematic diagram of a first write operation as shown in an exemplary embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram illustrating the second write operation and data transfer operation according to an exemplary embodiment of the present invention;

[0038] Figure 10 This is a schematic diagram of the critical voltage distribution of the memory cells of the first physical programmable unit under different states, as shown in an exemplary embodiment of the present invention.

[0039] Figure 11 This is a schematic diagram of the critical voltage distribution of the memory cells in the first physical programmable unit according to an exemplary embodiment of the present invention;

[0040] Figure 12 This is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention;

[0041] Figure 13 This is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention;

[0042] Figure 14 This is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention. Detailed Implementation

[0043] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0044] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0045] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0046] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to the system bus 110.

[0047] In one exemplary embodiment, the host system 11 can be connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0048] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be connected to the memory storage device 10 via wired or wireless means.

[0049] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0050] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0051] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0052] Please refer to Figure 3The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0053] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0055] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0056] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0057] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0058] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0059] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0060] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0061] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0062] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to a description of the operation of the memory control circuit unit 42.

[0063] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0064] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0065] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0066] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0067] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0068] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0069] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0070] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0071] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0072] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0073] Please refer to Figure 6 The memory management circuit 51 can group the physical erase units 610(0) to 610(B) logic in the rewritable non-volatile memory module 43 to the storage area 601 and the spare area 602. Each physical erase unit may include multiple physical programmable units.

[0074] The entity erasure units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 The user data of the host system 11). For example, entity erasure units 610(0) to 610(A) in storage area 601 may store valid data and / or invalid data. Entity erasure units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity erasure unit does not store valid data, this entity erasure unit may be associated (or added) to free area 602. In addition, entity erasure units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity erasure units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0075] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map entity erase units 610(0) to 610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logical addresses.

[0076] It should be noted that a logical unit can be mapped to one or more entity erase units. If an entity erase unit is currently mapped to a logical unit, it means that the data currently stored in this entity erase unit includes valid data. Conversely, if an entity erase unit is not currently mapped to any logical unit, it means that the data currently stored in this entity erase unit is invalid data.

[0077] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and entity erasure units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0078] Figure 7 This is a schematic diagram illustrating a usage scenario of a memory storage device according to an exemplary embodiment of the present invention.

[0079] Please refer to Figure 7 In one exemplary embodiment, the memory management circuit 51 can access the memory from... Figure 1 The host system 11 receives a write instruction. This write instruction may contain data (also referred to as first data) 701. For example, this write instruction may instruct the data 701 to be stored in a specific logic unit. Then, the memory management circuit 51 may temporarily store the data 701 in the buffer memory 55.

[0080] In one exemplary embodiment, the rewritable non-volatile memory module 43 includes a physical erasure unit (also referred to as a first physical erasure unit) 71. The physical erasure unit 71 includes physical programming units 711(0) to 711(D). The memory management circuitry 51 can determine the physical erasure unit 71 from the rewritable non-volatile memory module 43 based on the data 701 to be stored. For example, the memory management circuitry 51 can determine the physical erasure unit 71 from the data 701 to be stored. Figure 6 In the idle area 602, select one of the entity erasure units 610(A+1) to 610(B) as entity erasure unit 71.

[0081] In one exemplary embodiment, before storing data 701 according to a write instruction, memory management circuitry 51 may check the state of at least a portion of the physical programmable units (also referred to as first physical programmable units) in physical erase unit 71. In response to the state of the first physical programmable unit being a specific state (also referred to as a first state), memory management circuitry 51 may perform a data write operation (also referred to as a first write operation) on the first physical programmable unit according to data 701. The first write operation may be used to store at least a portion of data 701 into the first physical programmable unit. For example, in the first write operation, memory management circuitry 51 may send a sequence of write instructions (also referred to as a first instruction sequence) to rewritable non-volatile memory module 43. This first instruction sequence may be used to instruct rewritable non-volatile memory module 43 to store at least a portion of data 701 into the first physical programmable unit.

[0082] In other words, in response to the first entity programming unit being in a first state, the memory management circuit 51 may allow data 701 to be stored in the pre-selected entity erase unit 71 (or the first entity programming unit). In an exemplary embodiment, the first entity programming unit being in a first state may also mean that the state of the first entity programming unit meets preset conditions.

[0083] In one exemplary embodiment, the memory management circuit 51 can determine the total number of first physical programming units available for storing the data 701 in the physical erase unit 71 based on the amount of data 701 to be stored (or the total amount of data). In one exemplary embodiment, it is assumed that the capacity of one physical programming unit is 16 kilobytes (KB). If the total amount of data 701 is less than or equal to the capacity of one physical programming unit (i.e., 16 KB), then the total number of first physical programming units can be one. Alternatively, if the total amount of data 701 is greater than the capacity of one physical programming unit (i.e., 16 KB), then the total number of first physical programming units can be multiple. Subsequently, in response to the state of the first physical programming unit being a first state, the memory management circuit 51 can perform a first write operation on the first physical programming unit based on the data 701.

[0084] Figure 8A This is a schematic diagram of the first write operation shown in an exemplary embodiment of the present invention.

[0085] Please refer to Figure 8AAssume that data 702 is already stored in the physical erase unit 71 before data 701 is stored in it. The memory management circuit 51 can determine the physical programming unit 711(I) in the physical erase unit 71 as the first physical programming unit based on the data 701 to be stored. In response to the physical programming unit 711(I) being in the first state, the memory management circuit 51 can perform a first write operation on the physical programming unit 711(I) based on the data 701 to store the data 701 in the physical programming unit 711(I).

[0086] Figure 8B This is a schematic diagram of the first write operation shown in an exemplary embodiment of the present invention.

[0087] Please refer to Figure 8B Assuming that data 702 is already stored in the physical erase unit 71 before data 701 is stored in it, the memory management circuit 51 can determine all of the multiple physical programming units 711(I) to 711(J) in the physical erase unit 71 as first physical programming units based on the data 701 to be stored. That is, the first physical programming unit can refer to any one of the physical programming units 711(I) to 711(J). In response to the state of physical programming units 711(I) to 711(J) being in the first state, the memory management circuit 51 can perform a first write operation on physical programming units 711(I) to 711(J) based on data 701 to store data 701 in physical programming units 711(I) to 711(J). That is, physical programming units 711(I) to 711(J) are respectively used to store a portion of the data 701.

[0088] Please return Figure 7 In one exemplary embodiment, the rewritable non-volatile memory module 43 further includes a physical erasure unit (also referred to as a second physical erasure unit) 72. The physical erasure unit 72 includes physical programming units 712(0) to 712(D). In response to the state of the first physical programming unit (i.e., the physical erasure unit 71) being other than a first state, the memory management circuitry 51 can determine the physical erasure unit 72 from the rewritable non-volatile memory module 43 based on the data 701 to be stored. For example, the memory management circuitry 51 can determine the physical erasure unit 72 from the data 701 to be stored. Figure 6 In the idle area 602, one of the physical erase units 610(A+1) to 610(B) is selected as the physical erase unit 72. In response to the first physical programming unit (i.e., physical erase unit 71) being in a state other than the first state, the memory management circuit 51 may use the physical erase unit 72 to replace the physical erase unit 71 to store data 701.

[0089] In one exemplary embodiment, after determining the physical erase unit 72, the memory management circuit 51 may similarly check the state of at least a portion of the physical programmable units (also referred to as second physical programmable units) in the physical erase unit 72. The total number of second physical programmable units may also be determined based on the (total) data volume of data 701. In response to the state of the second physical programmable unit being a first state, the memory management circuit 51 may perform a data write operation (also referred to as a second write operation) on the second physical programmable unit based on data 701. The second write operation may be used to store at least a portion of the data 701 into the second physical programmable unit. For example, in the second write operation, the memory management circuit 51 may send a write instruction sequence (also referred to as a second instruction sequence) to the rewritable nonvolatile memory module 43. This second instruction sequence may be used to instruct the rewritable nonvolatile memory module 43 to store at least a portion of the data 701 into the second physical programmable unit.

[0090] In other words, in response to the first entity programming unit being in a state other than the first state, the memory management circuit 51 may not allow data 701 to be stored in the pre-selected entity erase unit 71 (or the first entity programming unit). Instead, in response to the second entity programming unit being in the first state, the memory management circuit 51 may store data 701 in the entity erase unit 72 (or the second entity programming unit) through a second write operation. In an exemplary embodiment, the state of the second entity programming unit being in the first state may also mean that the state of the second entity programming unit meets preset conditions.

[0091] In one exemplary embodiment, if the state of the second entity programming unit is also not the first state, another entity erase unit (also referred to as the third entity erase unit) in the rewritable non-volatile memory module 43 can also be determined, and at least some of the entity programming units (also referred to as the third entity programming units) in the third entity erase unit can be used to replace the second entity programming unit to store data 701, provided that a preset condition is met (i.e., the state of the third entity programming unit is the first state).

[0092] In one exemplary embodiment, in response to the state of the first physical programmable unit being other than the first state, the memory management circuit 51 may also perform a data transfer operation on the first physical erase unit. This data transfer operation can be used to transfer at least a portion of the data in the first physical erase unit to the second physical erase unit. For example, in the data transfer operation, the memory management circuit 51 may send a specific instruction sequence (also referred to as a third instruction sequence) to the rewritable non-volatile memory module 43. This third instruction sequence can be used to instruct the rewritable non-volatile memory module 43 to transfer at least a portion of the data in the first physical erase unit to the second physical erase unit. In particular, the data transferred in this data transfer operation may include valid data already stored in the first physical erase unit. Furthermore, this data transfer operation may be performed before, after, or simultaneously with the second write operation, without limitation by the present invention.

[0093] Figure 9 This is a schematic diagram illustrating the second write operation and data transfer operation according to an exemplary embodiment of the present invention.

[0094] Please refer to Figure 9 Assume that data 702 is already stored in physical erase unit 71 before data 701 is stored in physical erase unit 71. In response to a non-first state of the first physical programming unit (e.g., physical programming unit 711(I)), memory management circuit 51 may select physical erase unit 72 to replace physical erase unit 71 to store data 701. Simultaneously, memory management circuit 51 may determine physical programming unit 712(I) in physical erase unit 72 as the second physical programming unit based on the data 701 to be stored. In response to a first state of physical programming unit 712(I), memory management circuit 51 may perform a second write operation on physical programming unit 712(I) based on data 701 to store data 701 in physical programming unit 712(I). Furthermore, data 701 may also be stored in more second physical programming units in physical erase unit 72, depending on the total amount of data 701.

[0095] On the other hand, the memory management circuit 51 can perform a data transfer operation on the physical erase unit 71 to move the data 702 (i.e., valid data) stored in the physical erase unit 71 to the physical erase unit 72 for storage. For example, the data 702 can be stored in the physical programming units 712(0) to 712(I-1) in the physical erase unit 72. Furthermore, the actual storage addresses of data 701 and 702 in the physical erase unit 72 can also be adjusted according to practical needs, and the present invention does not impose any limitations. For example, in an exemplary embodiment, in the physical erase unit 72, the physical programming unit used to store data 701 can also be ordered before the physical programming unit used to store data 702, and the present invention does not impose any limitations.

[0096] Figure 10 This is a schematic diagram of the critical voltage distribution of the memory cell in different states of the first physical programmable unit according to an exemplary embodiment of the present invention.

[0097] Please refer to Figure 10 After programming the first entity programming unit, in the programmed state, the critical voltage distribution of the storage cells in the first entity programming unit may include states 1010 and 1020. Storage cells belonging to state 1010 and storage cells belonging to state 1020 can be used to store different bit data. For example, storage cells belonging to state 1010 can be used to store bit "1", while storage cells belonging to state 1020 can be used to store bit "0". However, it should be noted that... Figure 10 The critical voltage distribution of the memory cells in the example is merely an example and is not intended to limit the invention. In another exemplary embodiment, different types of programmed operations are performed on the memory cells. The memory cells in the first entity programmed unit may have different states, and the bit data corresponding to each state can also be set according to practical needs. The invention does not impose any limitations on this.

[0098] When data is to be read from the first programmed unit, a read voltage level V(Read) can be applied to the first programmed unit (e.g., the word line where the first programmed unit is located). The rewritable non-volatile memory module 43 can send the read result corresponding to the first programmed unit back to the memory management circuit 51. For example, this read result may reflect that the threshold voltage of a memory cell belonging to state 1010 is less than the read voltage level V(Read) and / or the threshold voltage of a memory cell belonging to state 1020 is greater than the read voltage level V(Read). Thus, the memory management circuit 51 can obtain the state of each memory cell in the first programmed unit, and then obtain the data stored in each memory cell according to the state of these memory cells.

[0099] In one exemplary embodiment, after an erase operation is performed on the first entity programming unit (or the first entity erase unit containing the first entity programming unit), each storage unit in the first entity programming unit will theoretically be in state 1030. State 1030 is also called the erase state. In the erase state, all previously stored data in the first entity programming unit has been erased (i.e., cleared).

[0100] It should be noted that, in the aforementioned exemplary embodiments, ideally, all memory cells in the entity programming unit (e.g., the first entity programming unit) selected by the memory management circuit 51 to store new data (e.g., data 701) should be in an erased state to avoid duplicate data writes to the same memory cell in subsequent data write operations. Duplicate data writes can lead to a decrease in the write quality of newly written data (e.g., an increase in bit error rate).

[0101] However, in practice, an erased physical programming unit (e.g., the first physical programming unit) may still be in a programmed state due to factors such as a "word line short," rather than the preset erased state. For example, due to the influence of a word line short, even if the first physical programming unit has been erased and all the memory cells in the first physical programming unit are in an erased state, when another physical programming unit in the rewritable non-volatile memory module 43 is programmed to write new data, at least some of the memory cells in the first physical programming unit may also be programmed synchronously, causing at least some of the memory cells in the first physical programming unit to unexpectedly change from the preset erased state to a programmed state. Subsequently, if the memory management circuit 51 does not detect that at least some of the memory cells in the first physical programming unit are in a programmed state and performs a data write operation on the first physical programming unit to store new data, the data write quality may degrade (e.g., the bit error rate may increase) due to repeated writing of memory cells.

[0102] In one exemplary embodiment, during the process of checking the state of the first physical programming unit, the memory management circuit 51 may check whether there are any memory cells in the first physical programming unit that are not in an erased state. In response to the presence of memory cells in the first physical programming unit that are not in an erased state, the memory management circuit 51 may determine that the state of the first physical programming unit is not the first state. Conversely, in response to the detection that all memory cells in the first physical programming unit are in an erased state, the memory management circuit 51 may determine that the state of the first physical programming unit is the first state.

[0103] In one exemplary embodiment, during the process of checking the state of the first physical programmed unit, the memory management circuit 51 can determine whether the total number of memory cells not in an erased state (i.e., memory cells in a programmed state) in the detected first physical programmed unit exceeds a threshold. If the total number of memory cells not in an erased state in the detected first physical programmed unit exceeds this threshold, the memory management circuit 51 can determine that the state of the first physical programmed unit is not the first state. Conversely, if the total number of memory cells not in an erased state in the detected first physical programmed unit does not exceed this threshold, the memory management circuit 51 can still determine that the state of the first physical programmed unit is the first state.

[0104] In one exemplary embodiment, the memory management circuit 51 may determine this threshold value based on the total number of memory cells in the first physical programmable unit. For example, this threshold value may be obtained by multiplying the total number of memory cells in the first physical programmable unit by a proportional value. For example, this proportional value may be 2%, 5%, or 10%, and this proportional value may be adjusted according to practical needs.

[0105] In one exemplary embodiment, during the process of checking the state of the first physical programmed unit, the memory management circuit 51 may send a specific instruction sequence (also referred to as a fourth instruction sequence) to the rewritable non-volatile memory module 43. This fourth instruction sequence can be used to instruct the rewritable non-volatile memory module 43 to perform a read operation on the first physical programmed unit to obtain state data corresponding to the first physical programmed unit. This state data may reflect the state of at least a portion of the memory cells in the first physical programmed unit. The memory management circuit 51 may determine the state of the first physical programmed unit based on the state data. For example, the memory management circuit 51 may determine whether the state of the first physical programmed unit is a first state based on the state data.

[0106] In one exemplary embodiment, the memory management circuit 51 can determine whether the status data includes specific data. This specific data may reflect that at least one memory cell in the first physical programmable unit is not in an erased state. If the status data includes this specific data, the memory management circuit 51 can determine that the state of the first physical programmable unit is not the first state based on this specific data (e.g., the total number of this specific data). If the status data does not include this specific data, the memory management circuit 51 can determine that the state of the first physical programmable unit is the first state.

[0107] Figure 11 This is a schematic diagram of the critical voltage distribution of the memory cells in the first physical programmable unit according to an exemplary embodiment of the present invention.

[0108] Please refer to Figure 11In one exemplary embodiment, it is assumed that the critical voltage distribution of the memory cells of the first physical programmed unit after erasure includes states 1030 and 1110. The vast majority of memory cells are in the erased state (i.e., state 1030) because they have been erased, while only a small portion of memory cells are back in the programmed state (i.e., state 1110) due to factors such as word line short circuits. However, the critical voltage distribution of the memory cells of the first physical programmed unit may vary depending on the actual situation, and this invention does not impose limitations.

[0109] In one exemplary embodiment, during the process of checking the state of the first physical programmed unit, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to read the first physical programmed unit using a read voltage level V (Read). Based on the read result returned by the rewritable non-volatile memory module 43, the memory management circuit 51 may obtain state data corresponding to the first physical programmed unit. For example, this state data may contain a large number of bits "1" and a small number of bits "0", where the total number of bits "1" reflects the total number of memory cells belonging to state 1030, and the total number of bits "0" reflects the total number of memory cells belonging to state 1110.

[0110] In one exemplary embodiment, the specific data may include bits "1" in the status data. The memory management circuit 51 may determine the state of the first entity programmable unit based on the total number of bits "1", the total number of bits "0", and / or the ratio of bits "1" to bits "0" in the status data. For example, the memory management circuit 51 may determine the state of the first entity programmable unit based on whether the total number of bits "1" is greater than a threshold, whether the total number of bits "0" is greater than a threshold, or whether the ratio of bits "1" to bits "0" is greater than a proportional value. For example, in one exemplary embodiment, in response to the total number of bits "1" in the status data being greater than a threshold, the total number of bits "0" being less than a threshold, or the ratio of bits "1" to bits "0" being greater than a proportional value, the memory management circuit 51 may determine that the state of the first entity programmable unit is a first state. Conversely, if the total number of bits "1" in the state data is not greater than a threshold value, the total number of bits "0" is not less than a threshold value, or the ratio of bits "1" to bits "0" is not greater than a ratio value, then the memory management circuit 51 can determine that the state of the first entity programmable unit is not the first state.

[0111] In one exemplary embodiment, the status data may reflect the status of all storage units in the first entity programmable unit. In another exemplary embodiment, the status data may reflect the status of only a subset of the storage units in the first entity programmable unit. For example, assuming the first entity programmable unit comprises P storage units, the status data may reflect the status of Q storage units in the first entity programmable unit, where Q is less than P. Alternatively, assuming the first entity programmable unit stores 16KB of data, the status data may be only 4KB or other values ​​less than 16KB. This effectively reduces the amount of data that needs to be read and / or analyzed.

[0112] From another perspective, in one exemplary embodiment, the memory management circuit 51 can determine the state of the first physical programming unit based on the state of a portion of the memory cells within the first physical programming unit, without needing to completely read the entire first physical programming unit (or all memory cells within the first physical programming unit). This improves the efficiency of determining the state of the first physical programming unit.

[0113] In one exemplary embodiment, if the state of the first physical programmable unit is in the first state, it indicates that the total number of storage units in the first physical programmable unit that should be in an erased state but are actually in a programmable state does not exceed the allowable value (or there are no storage units in a programmable state). Therefore, the memory management circuit 51 can continue to use the first physical programmable unit to store data. However, if the state of the first physical programmable unit is not in the first state, it indicates that the total number of storage units in the first physical programmable unit that should be in an erased state but are actually in a programmable state has exceeded the allowable value. Therefore, the memory management circuit 51 can use other physical erase units (e.g., a second physical erase unit) to store data to improve the data storage quality. At the same time, valid data in the first physical erase unit can be synchronously moved to a new physical erase unit (e.g., a second physical erase unit) for storage, and the first physical erase unit can be erased again and recycled. Figure 6 The idle area 602. When the first entity erase unit is selected again to store data, the same operation can be used to verify the first entity erase unit to ensure the data write quality for the first entity erase unit (or the first entity programmable unit). The relevant operational details have been described above and will not be repeated here.

[0114] Figure 12 This is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention.

[0115] Please refer to Figure 12In step S1201, a write instruction is received from the host system, wherein the write instruction contains first data. In step S1202, the state of the first entity programming unit in the first entity erase unit is checked. In step S1203, it is determined whether the state of the first entity programming unit is a first state. In response to the state of the first entity programming unit being in the first state, in step S1204, a first write operation is performed on the first entity programming unit according to the first data. For example, the first write operation is used to store at least a portion of the first data into the first entity programming unit. Alternatively, in response to the state of the first entity programming unit not being in the first state, in step S1205, a second write operation is performed on the second entity programming unit in the second entity erase unit according to the first data. For example, the second write operation is used to store at least a portion of the first data into the second entity programming unit.

[0116] Figure 13 This is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention.

[0117] Please refer to Figure 13 In step S1301, a read operation is performed on a specific entity programming unit (also referred to as the target entity programming unit) in the first entity erasure unit. For example, the target entity programming unit is one of a plurality of first entity programming units. In step S1302, the state of the target entity programming unit is determined based on the read result. In step S1303, it is determined whether the state of the target entity programming unit is a first state. In response to the state of the target entity programming unit being a first state, in step S1304, a data write operation is performed on the target entity programming unit based on a portion of the first data. In step S1305, the target entity programming unit is switched. For example, the target entity programming unit is switched to another of the plurality of first entity programming units. Then, step S1301 can be repeated. On the other hand, in response to the state of the target entity programming unit not being a first state, in step S1306, the entity erasure unit used to store the first data is changed from a first entity erasure unit to a second entity erasure unit.

[0118] Figure 14 This is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention.

[0119] Please refer to Figure 14In step S1401, a read operation is performed on multiple target entity programming units in the first entity erasure unit. For example, each target entity programming unit is one of multiple first entity programming units. In step S1402, the state of the multiple target entity programming units is determined based on the read result. In step S1403, it is determined whether the states of the multiple target entity programming units are all in the first state. In response to the states of the multiple target entity programming units being all in the first state, in step S1404, a data write operation is performed on the multiple target entity programming units based on the first data. Alternatively, in response to the states of the multiple target entity programming units not all being in the first state (i.e., at least one target entity programming unit is not in the first state), in step S1405, the entity erasure unit used to store the first data is changed from the first entity erasure unit to the second entity erasure unit.

[0120] However, Figures 12 to 14 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 12 to 14 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figures 12 to 14 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0121] In summary, the data writing method, memory storage device, and memory control circuit unit provided in this embodiment of the invention can check the state of the first physical programmed unit before writing data to it. If the state of the first physical programmed unit meets expectations (i.e., the state of the first physical programmed unit is the first state), a first write operation can be performed on the first physical programmed unit to store the first data. However, if the state of the first physical programmed unit does not meet expectations (i.e., the state of the first physical programmed unit is not the first state), a second physical erase unit can be used to replace the first physical erase unit to store the first data. Therefore, repeated writing to a specific physical programmed unit can be effectively avoided and the data writing quality can be improved.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data writing method, characterized in that, For a rewritable non-volatile memory module, the rewritable non-volatile memory module includes multiple physical erasure units, the multiple physical erasure units include a first physical erasure unit, and the data writing method includes: Receive a write instruction from the host system, wherein the write instruction contains first data; Before storing the first data, check the state of the first entity programming unit in the first entity erasure unit; and In response to the first entity programming unit being in a first state, a first instruction sequence is sent, wherein the first instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the first entity programming unit. The step of checking the state of the first entity programming unit in the first entity erasure unit includes: Check whether the total number of memory units that are not in an erased state in the first entity programmatic unit exceeds a critical value; In response to the total number of storage units in the first entity programmable unit that are not in the erase state exceeding the threshold, it is determined that the state of the first entity programmable unit is not the first state. Send a fourth instruction sequence, wherein the fourth instruction sequence is used to instruct the rewritable non-volatile memory module to perform a read operation on the first physical programmable unit to obtain state data corresponding to the first physical programmable unit, wherein the state data reflects the state of at least a portion of the memory cells in the first physical programmable unit; and The state of the first entity programmatic unit is determined based on the state data. The first entity programmable unit includes P storage units, and the state data reflects the state of Q storage units in the first entity programmable unit, where Q is less than P.

2. The data writing method according to claim 1 further includes: The total number of the first entity programmatic units is determined based on the amount of data in the first data.

3. The data writing method according to claim 1, wherein the plurality of entity erasure units further includes a second entity erasure unit, and the data writing method further includes: In response to the first entity programmable unit being in a state other than the first state, a second instruction sequence is sent, wherein the second instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the second entity erase unit.

4. The data writing method according to claim 3 further includes: In response to the first entity programmable unit being in a state other than the first state, a third instruction sequence is sent, wherein the third instruction sequence is used to instruct the rewritable non-volatile memory module to move at least a portion of the data in the first entity erase unit to the second entity erase unit.

5. The data writing method according to claim 1, wherein the step of determining the state of the first entity programming unit based on the state data includes: Based on specific data in the state data, it is determined that the state of the first entity programmatic unit is not the first state. The specific data therein reflects that at least one storage unit in the first entity programming unit is not in the erased state.

6. A memory storage device, characterized in that, include: Host interface unit, used to connect to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasure units, and the plurality of physical erasure units includes a first physical erasure unit; and The memory control circuit unit is connected to the host interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Receive a write instruction from the host system, wherein the write instruction contains first data; Before storing the first data, check the state of the first entity programming unit in the first entity erasure unit; as well as In response to the first entity programming unit being in a first state, a first instruction sequence is sent, wherein the first instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the first entity programming unit. The operation of the memory control circuit unit checking the state of the first entity programming unit in the first entity erase unit includes: Check whether the total number of memory units that are not in an erased state in the first entity programmatic unit exceeds a critical value; In response to the total number of storage units in the first entity programmable unit that are not in the erase state exceeding the threshold, it is determined that the state of the first entity programmable unit is not the first state. Send a fourth instruction sequence, wherein the fourth instruction sequence is used to instruct the rewritable non-volatile memory module to perform a read operation on the first physical programmable unit to obtain state data corresponding to the first physical programmable unit, wherein the state data reflects the state of at least a portion of the memory cells in the first physical programmable unit; and The state of the first entity programmatic unit is determined based on the state data. The first entity programmable unit includes P storage units, and the state data reflects the state of Q storage units in the first entity programmable unit, where Q is less than P.

7. The memory storage device according to claim 6, wherein the memory control circuit unit is further configured to: The total number of the first entity programmatic units is determined based on the amount of data in the first data.

8. The memory storage device according to claim 6, wherein the plurality of physical erasure units further comprises a second physical erasure unit, and the memory control circuit unit is further configured to: In response to the first entity programmable unit being in a state other than the first state, a second instruction sequence is sent, wherein the second instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the second entity erase unit.

9. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: In response to the first entity programmable unit being in a state other than the first state, a third instruction sequence is sent, wherein the third instruction sequence is used to instruct the rewritable non-volatile memory module to move at least a portion of the data in the first entity erase unit to the second entity erase unit.

10. The memory storage device of claim 6, wherein the operation of the memory control circuit unit in determining the state of the first entity programming unit based on the state data includes: Based on specific data in the state data, it is determined that the state of the first entity programmatic unit is not the first state. The specific data therein reflects that at least one storage unit in the first entity programming unit is not in the erased state.

11. A memory control circuit unit, characterized in that, This is used to control a rewritable non-volatile memory module, the rewritable non-volatile memory module including multiple physical erasure units, the multiple physical erasure units including a first physical erasure unit, and the memory control circuit unit including: Host interface, used to connect to the host system; A memory interface for connecting to the rewritable non-volatile memory module; Buffer memory; and A memory management circuit is connected to the host interface, the memory interface, and the buffer memory. The memory management circuit mentioned above is used for: Receive a write instruction from the host system, wherein the write instruction contains first data; Before storing the first data, check the state of the first entity programming unit in the first entity erasure unit; and In response to the first entity programming unit being in a first state, a first instruction sequence is sent, wherein the first instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the first entity programming unit. The operation of the memory management circuit checking the state of the first entity programming unit in the first entity erase unit includes: Check whether the total number of memory units that are not in an erased state in the first entity programmatic unit exceeds a critical value; In response to the total number of storage units in the first entity programmable unit that are not in the erase state exceeding the threshold, it is determined that the state of the first entity programmable unit is not the first state. Send a fourth instruction sequence, wherein the fourth instruction sequence is used to instruct the rewritable non-volatile memory module to perform a read operation on the first physical programmable unit to obtain state data corresponding to the first physical programmable unit, wherein the state data reflects the state of at least a portion of the memory cells in the first physical programmable unit; and The state of the first entity programmatic unit is determined based on the state data. The first entity programmable unit includes P storage units, and the state data reflects the state of Q storage units in the first entity programmable unit, where Q is less than P.

12. The memory control circuit unit according to claim 11, wherein the memory management circuit is further configured to: The total number of the first entity programmatic units is determined based on the amount of data in the first data.

13. The memory control circuit unit of claim 11, wherein the plurality of physical erase units further includes a second physical erase unit, and the memory management circuit is further configured to: In response to the first entity programmable unit being in a state other than the first state, a second instruction sequence is sent, wherein the second instruction sequence is used to instruct the rewritable non-volatile memory module to store at least a portion of the first data into the second entity erase unit.

14. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to: In response to the first entity programmable unit being in a state other than the first state, a third instruction sequence is sent, wherein the third instruction sequence is used to instruct the rewritable non-volatile memory module to move at least a portion of the data in the first entity erase unit to the second entity erase unit.

15. The memory control circuit unit of claim 11, wherein the operation of the memory management circuit in determining the state of the first entity programmable unit based on the state data includes: Based on specific data in the state data, it is determined that the state of the first entity programmatic unit is not the first state. The specific data therein reflects that at least one storage unit in the first entity programming unit is not in the erased state.

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