Hardware acceleration implementation method and device of soft decoding LDPC and computer equipment

Abstract

The application relates to a hardware acceleration implementation method and device of soft decode LDPC, a computer device and a storage medium, wherein the method comprises the following steps: in the booting initialization process, related data information addresses of offset voltages are transmitted to hardware; offset voltage information, the maximum modification times of offset voltages, the recovery value of the offset voltage for exiting the soft decode LDPC are maintained through a hardware acceleration module; a read command is acquired and whether the data can be correctly read through a DP module error correction; if the data can be read, correct data is returned; if the data cannot be read, whether the data can be correctly read through a read retry process is determined; if the data can be read, correct data is returned; if the data cannot be read, whether the data can be correctly read is determined through a hardware automatic execution soft decode LDPC process. The process of the soft decode LDPC is automatically realized by the application, the operation of FW repeated preparation and command issuing is reduced, and the error correction efficiency is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage systems, and in particular to a hardware acceleration implementation method and device for soft decode LDPC, a computer device and a storage medium. BACKGROUND

[0002] With the increase of NAND FLASH storage density, the reliability decreases relatively. In the process of reading the NAND Flash, data errors that cannot be corrected by the BCH algorithm may occur. At this time, the LDPC algorithm (Low Density Parity Check Code) is needed to correct.

[0003] At present, the LDPC algorithm is used in SSD and is divided into hard decode LDPC and soft decode LDPC. The process of the soft decode LDPC is to adjust different offset voltage values through the FW. Whether the offset voltage value needs to be changed to read data is determined according to the correct or incorrect data result each time. In order to read the correct data result, the software may need to determine multiple times. The whole process is too repetitive and tedious, which is not conducive to improving the performance of the SSD. SUMMARY

[0004] Therefore, it is necessary to provide a hardware acceleration implementation method and device for soft decode LDPC, a computer device and a storage medium in view of the above technical problems.

[0005] A hardware acceleration implementation method for soft decode LDPC, characterized in that the method comprises:

[0006] In the process of booting and initializing, the related data information address of the offset voltage is transmitted to the hardware.

[0007] The offset voltage information, the maximum number of offset voltage modifications, and the recovery value of the offset voltage for exiting the soft decode LDPC are maintained by the hardware acceleration module.

[0008] The read command is obtained and whether the data can be correctly read is determined by the DP module.

[0009] If the data can be read, the correct data is returned. If the data cannot be read, whether the data can be correctly read is determined by the read retry process.

[0010] If the data can be read, the correct data is returned. If the data cannot be read, the hardware automatically executes the soft decode LDPC process to determine whether the data can be correctly read.

[0011] In one of the embodiments, after the step of checking whether the data can be read correctly by the hardware automatically performing soft decode LDPC procedure if not, the method further comprises:

[0012] If the data can be read, correct data is returned, and if not, the method jumps to checking whether the data can be read correctly by the raid procedure.

[0013] In one of the embodiments, after the step of checking whether the data can be read correctly by the raid procedure if not, the method further comprises:

[0014] If the data can be read, correct data is returned, and if not, the data error correction fails to read the correct data.

[0015] In one of the embodiments, the method further comprises:

[0016] The hardware performs the offset voltage value prepared in advance by the FW in the form of a linked list.

[0017] When the LDPC succeeds, the linked list is exited, or when the number of times has reached the maximum set value and still fails, the soft decode LDPC operation is ended.

[0018] A hardware acceleration implementation device of soft decode LDPC, the device comprises:

[0019] A passing module, configured to pass the address of the related data information of the offset voltage to the hardware in the process of booting initialization.

[0020] A hardware acceleration module, configured to maintain the offset voltage information, the maximum number of times of modifying the offset voltage, and the recovery value of the offset voltage for exiting the soft decode LDPC.

[0021] A first judging module, configured to acquire the read command issued and check whether the data can be read correctly by the DP module.

[0022] A second judging module, configured to return correct data if the data can be read, and check whether the data can be read correctly by the read retry procedure if not.

[0023] A third judging module, configured to return correct data if the data can be read, and check whether the data can be read correctly by the hardware automatically performing soft decode LDPC procedure if not.

[0024] In one of the embodiments, the device further comprises a fourth judging module, configured to:

[0025] If it can be read, return the correct data, if not, jump to whether the data can be read correctly through the raid process.

[0026] In one embodiment, the device further comprises an error reporting module, which is configured to:

[0027] If it can be read, return the correct data, if not, the data error correction fails to read the correct data.

[0028] In one embodiment, the hardware acceleration module is further configured to:

[0029] The hardware performs the offset voltage value prepared in advance by the FW in the form of a linked list;

[0030] After the LDPC succeeds, the linked list is exited or the number of times has reached the maximum set value and still fails, and the soft decode LDPC operation is ended.

[0031] A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of any of the above methods when executing the computer program.

[0032] A computer readable storage medium, having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0033] The hardware acceleration implementation method, device, computer device and storage medium of the above soft decode LDPC pass the address of the related data information of the offset voltage to the hardware in the boot initialization process; the hardware acceleration module maintains the offset voltage information, the maximum number of times of modifying the offset voltage, and the recovery value of the offset voltage for exiting the soft decode LDPC; the read command is obtained and whether the data can be read correctly through the DP module error correction; if it can be read, the correct data is returned, if not, whether the data can be read correctly through the read retry process; if it can be read, the correct data is returned, if not, the hardware automatically executes the soft decode LDPC process to check whether the data can be read correctly. The present application changes the soft decode LDPC process to be automatically implemented by the hardware, reduces the operation of FW repeated preparation and command issuing, and effectively improves the error correction efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The present application is a schematic diagram of the implementation method of the soft decode LDPC in the prior art;

[0035] Figure 2A flowchart of a method for hardware acceleration of soft decode LDPC in one embodiment;

[0036] Figure 3 A flowchart of a method for hardware acceleration of soft decode LDPC in another embodiment;

[0037] Figure 4 A flowchart of a method for hardware acceleration of soft decode LDPC in yet another embodiment;

[0038] Figure 5 A block diagram of an apparatus for hardware acceleration of soft decode LDPC in one embodiment;

[0039] Figure 6 A block diagram of an apparatus for hardware acceleration of soft decode LDPC in another embodiment;

[0040] Figure 7 A block diagram of an apparatus for hardware acceleration of soft decode LDPC in yet another embodiment;

[0041] Figure 8 An internal block diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0043] Currently, the stability of NAND FALSH particles decreases in the later stage of the entire life cycle, at which time BCH algorithm, LDPC hardware error correction, soft decode LDPC, RAID error correction, etc. are needed for data recovery. Soft decode LDPC needs to be implemented synchronously by SSDFW, which can be referred to as Figure 1 As shown in the figure, the steps of soft decode LDPC are as follows:

[0044] Step 1: Change the internal offset voltage of the particle by set feature, so as to change the read data returned by the particle.

[0045] Step 2: Check whether the correct data can be read through the newly modified offset voltage. If yes, exit the soft decode LDPC flow; if not, go to step 3.

[0046] Step 3, check whether the number of times of modifying the offset voltage reaches the set maximum value, if not, jump to step 1, repeat the above steps, if yes, exit the soft decode LDPC process, and no correct data is read.

[0047] Therefore, in the soft decode LDPC process, the offset voltage in the grain needs to be issued multiple times to obtain correct read data.

[0048] Therefore, in the soft decode LDPC process, the offset voltage in the grain needs to be issued multiple times to obtain correct read data.

[0049] In one embodiment, as shown in Figure 2 A hardware acceleration implementation method of soft decode LDPC is provided, and the method comprises the following steps:

[0050] Step 202, in the booting initialization process, the related data information address of the offset voltage is transmitted to the hardware.

[0051] Step 204, the offset voltage information, the maximum modification number of the offset voltage, and the recovery value of the offset voltage for exiting the soft decode LDPC are maintained by the hardware acceleration module.

[0052] Step 206, a read command is acquired, and whether the data can be correctly read by the DP module is corrected.

[0053] Step 208, if the data can be read, correct data is returned, if not, whether the data can be correctly read by the read retry process is checked.

[0054] Step 210, if the data can be read, correct data is returned, if not, the hardware automatically executes the soft decode LDPC process to check whether the data can be correctly read.

[0055] In the embodiment, a hardware acceleration implementation method of soft decode LDPC is provided, and the method changes the process of soft decode LDPC into hardware implementation, so that the operation process of the FW is simplified, and the efficiency is improved.

[0056] Firstly, in the booting initialization process, the related data information address of the offset voltage is transmitted to the hardware. The offset voltage information, the maximum modification number of the offset voltage, and the recovery value of the offset voltage for exiting the soft decode LDPC are maintained by the hardware acceleration module.

[0057] In one embodiment, the method further comprises: performing the offset voltage value prepared in advance by the FW in a linked list form by hardware; ending the soft decode LDPC operation when the LDPC succeeds or the number of times has reached the maximum set value and still fails.

[0058] Specifically, the flow of the soft decode LDPC is changed to be implemented by hardware, the hardware performs the offset voltage value prepared in advance by the FW in a linked list form, and the linked list is exited after the LDPC succeeds or the number of times has reached the maximum set value and still fails, so that the operation flow of the FW is simplified and the efficiency is improved.

[0059] Then, it is determined whether the data can be read correctly by the DP module error correction based on the read command issued, and if yes, the correct data is returned, and if not, it is determined whether the data can be read correctly by the read retry flow, and if yes, the correct data is returned, and if not, the soft decode LDPC flow is automatically executed by the hardware to determine whether the data can be read correctly.

[0060] In the embodiment, the address of the offset voltage related data information is transmitted to the hardware in the boot initialization process, the offset voltage information, the maximum number of times of modification of the offset voltage, and the recovery value of the offset voltage for exiting the soft decode LDPC are maintained by the hardware acceleration module, it is determined whether the data can be read correctly by the DP module error correction based on the read command issued, and if yes, the correct data is returned, and if not, it is determined whether the data can be read correctly by the read retry flow, and if yes, the correct data is returned, and if not, the soft decode LDPC flow is automatically executed by the hardware to determine whether the data can be read correctly. The flow of the soft decode LDPC is changed to be automatically implemented by the hardware, the operation of the FW repeated preparation and the command issued is reduced, and the error correction efficiency is effectively improved.

[0061] In one embodiment, as shown in Figure 3 the hardware acceleration implementation method of the soft decode LDPC further comprises, after the step of determining whether the data can be read correctly by the soft decode LDPC flow automatically executed by the hardware:

[0062] In step 302, if the data can be read, the correct data is returned, and if not, the read flow is jumped to determine whether the data can be read correctly.

[0063] In step 304, if the data can be read, the correct data is returned, and if not, the data error correction fails and the correct data cannot be read.

[0064] In the embodiment, a hardware acceleration implementation method of soft decode LDPC is provided, which can refer to Figure 4 The specific process is as follows:

[0065] Step 1. In the process of booting initialization, the address of the related data information of the offset voltage is transmitted to the hardware. The hardware acceleration module maintains the offset voltage information, the maximum number of offset voltage modifications, and the recovery value of the offset voltage for exiting the soft decode LDPC.

[0066] Step 2. After receiving the read command, it is determined whether the data can be correctly read through the DP module error correction. If yes, the correct data is returned. If no, go to step 3.

[0067] Step 3. It is determined whether the data can be correctly read through the read retry process. If yes, the correct data is returned. If no, go to step 4.

[0068] Step 4. The hardware automatically executes the soft decode LDPC process to determine whether the data can be correctly read. If yes, the correct data is returned. If no, go to step 5.

[0069] Step 5. It is determined whether the data can be correctly read through the raid process. If yes, the correct data is returned. If no, the data error correction fails and the correct data cannot be read.

[0070] In the embodiment, the operation of FW repeated preparation and command issuing is reduced. The process of soft decode LDPC is changed to hardware implementation, which further simplifies the operation process of the FW and improves the efficiency.

[0071] It should be understood that, although Figures 1-4 the steps in the flowchart of the method are shown in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified in this document, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figures 1-4 At least part of the steps in the method can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0072] In one embodiment, as Figure 5As shown, a hardware acceleration implementation device 500 for soft decode LDPC is provided, the device comprising:

[0073] The transmission module 501 is used to transmit the relevant data information address of the offset voltage to the hardware during the power-on initialization process.

[0074] Hardware acceleration module 502, which is used to maintain offset voltage information, maximum number of times the offset voltage is modified, and recovery value of the offset voltage after exiting soft decode LDPC;

[0075] The first judgment module 503 is used to obtain the issued read command and correct whether the data can be read correctly through the DP module.

[0076] The second judgment module 504 is used to return the correct data if it can be read, and to check whether the data can be read correctly through the read retry process if it cannot be read.

[0077] The third judgment module 505 is used to return the correct data if it can be read, and to automatically execute the soft decode LDPC process to check whether the data can be read correctly if it cannot be read.

[0078] In one embodiment, such as Figure 6 As shown, a hardware acceleration implementation device 500 for soft decode LDPC is provided. This device further includes a fourth judgment module 506, which is used for:

[0079] If the data can be read, return the correct data; otherwise, proceed to check if the data can be read correctly via the RAID process.

[0080] In one embodiment, such as Figure 7 As shown, a hardware acceleration implementation device 500 for soft decode LDPC is provided. This device further includes an error reporting module 507, which is used for:

[0081] If the data can be read, return the correct data; otherwise, data correction fails and the correct data cannot be read.

[0082] In one embodiment, the hardware acceleration module 502 is further configured to:

[0083] The offset voltage values ​​pre-prepared by FW are executed in the form of a linked list through the hardware;

[0084] When the LDPC succeeds, the execution chain table is exited or the number of times has reached the set maximum value and still fails, the soft decode LDPC operation is ended.

[0085] The specific limitation of the hardware acceleration implementation device for the soft decode LDPC can refer to the limitation of the hardware acceleration implementation method for the soft decode LDPC in the foregoing, which will not be repeated here.

[0086] In an embodiment, a computer device is provided, and an internal structure diagram of the computer device can be as shown in Figure 8 The computer device includes a processor, a memory and a network interface connected through a device bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating device, a computer program and a database. The internal memory provides an environment for the operation of the operating device and the computer program in the non-volatile storage medium. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement a hardware acceleration implementation method for soft decode LDPC.

[0087] Those skilled in the art can understand that Figure 8 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0088] In an embodiment, a computer device is provided, and includes a memory, a processor and a computer program stored in the memory and executable on the processor. The processor implements the steps in each of the method embodiments above when executing the computer program.

[0089] In an embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program is executed by the processor to implement the steps in each of the method embodiments above.

[0090] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0091] Any combination of the technical features of the above embodiments can be made, and in order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0092] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. A method for hardware-accelerated implementation of soft-decoding LDPC, the method comprising: The method comprises: passing the address of the related data information of the offset voltage to the hardware in the boot initialization process; maintaining the offset voltage information, the maximum modification times of the offset voltage, and the recovery value of the offset voltage for exiting the soft decode LDPC by the hardware acceleration module; acquiring the read command issued and checking whether the data can be correctly read by the DP module; if the data can be read, returning the correct data, and if the data cannot be read, checking whether the data can be correctly read by the read retry process; if the data can be read, returning the correct data, and if the data cannot be read, automatically executing the soft decode LDPC process by the hardware to check whether the data can be correctly read; the method further comprises: performing the offset voltage value prepared in advance by the FW in the form of a linked list by the hardware; ending the soft decode LDPC operation when the linked list is exited after the LDPC succeeds or the number of times has reached the maximum value set and still fails.

2. The method of Claim 1, wherein, after the step of automatically executing the soft decode LDPC process by the hardware to check whether the data can be correctly read, the method further comprises: if the data can be read, returning the correct data, and if the data cannot be read, jumping to the process of checking whether the data can be correctly read by the raid process.

3. The method of Claim 2, wherein, after the step of jumping to the process of checking whether the data can be correctly read by the raid process, the method further comprises: if the data can be read, returning the correct data, and if the data cannot be read, failing to read the correct data due to the data error correction.

4. An apparatus for hardware-accelerated implementation of soft-decoding LDPC, the apparatus comprising: the device comprises: a passing module configured to pass the address of the related data information of the offset voltage to the hardware in the boot initialization process; a hardware acceleration module configured to maintain the offset voltage information, the maximum modification times of the offset voltage, and the recovery value of the offset voltage for exiting the soft decode LDPC; a first judging module configured to acquire the read command issued and check whether the data can be correctly read by the DP module; a second judging module configured to, if the data can be read, return the correct data, and if the data cannot be read, check whether the data can be correctly read by the read retry process; a third judging module configured to, if the data can be read, return the correct data, and if the data cannot be read, automatically execute the soft decode LDPC process by the hardware to check whether the data can be correctly read. the hardware acceleration module is further configured to: perform the offset voltage value prepared in advance by the FW in the form of a linked list by the hardware; end the soft decode LDPC operation when the linked list is exited after the LDPC succeeds or the number of times has reached the maximum value set and still fails.

5. The apparatus for hardware-accelerated implementation of soft-decision decoding of LDPC codes of claim 4, wherein, the device further comprises a fourth judging module configured to: if the data can be read, return the correct data, and if the data cannot be read, jump to the process of checking whether the data can be correctly read by the raid process.

6. The apparatus for hardware-accelerated implementation of soft decode LDPC of claim 5, wherein, the device further comprises an error reporting module configured to: if the data can be read, return the correct data, and if the data cannot be read, fail to read the correct data due to the data error correction.

7. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 3.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 3.

Images