Semiconductor Components and Their Fabrication Methods

Abstract

This disclosure provides a semiconductor device with an inverter and a method for fabricating the semiconductor device. The semiconductor device has a substrate; a gate structure disposed on the substrate; a first impurity region and a second impurity region respectively disposed on opposite sides of the gate structure and in the substrate; a first contact point disposed on the first impurity region and including a first resistance value; and a second contact point disposed on the first impurity region and including a second resistance value, the second resistance value being less than the first resistance value of the first contact point. The first contact point is configured to be electrically coupled to a power supply, and the second contact point is configured to be electrically coupled to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact point, and the second contact point are collectively configured as an inverter.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. Official Application No. 17 / 345,915, filed June 11, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor element and a method for fabricating the semiconductor element. In particular, it relates to a semiconductor element having an inverter and a method for fabricating the semiconductor element having the inverter. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is gradually shrinking to meet the increasing demands for computing power. However, this shrinking process introduces new and increasingly complex problems. Therefore, the challenges of improving quality, yield, performance, and reliability, while reducing complexity, continue.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a substrate; a gate structure disposed on the substrate; a first impurity region and a second impurity region respectively disposed on opposite sides of the gate structure and in the substrate; a first contact point disposed on the first impurity region and including a first resistance value; and a second contact point disposed on the first impurity region and including a second resistance value, the second resistance value being less than the first resistance value of the first contact point. The first contact point is configured to be electrically coupled to a power supply, and the second contact point is configured to be electrically coupled to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact point, and the second contact point are collectively configured as an inverter.

[0006] In some embodiments, the first contact point comprises titanium nitride or doped polycrystalline silicon.

[0007] In some embodiments, the second contact point comprises tungsten.

[0008] In some embodiments, the semiconductor device further includes a barrier layer disposed between the second contact point and the first impurity region, and disposed on a sidewall of the second contact point. The barrier layer comprises tungsten nitride.

[0009] In some embodiments, the width of the first contact point is smaller than the width of the second contact point.

[0010] In some embodiments, the semiconductor device further includes a third contact point disposed on the second impurity region. The third contact point comprises tungsten. The third contact point is configured to be electrically coupled to a ground potential.

[0011] In some embodiments, the semiconductor device further includes a gate contact disposed on the gate structure. The gate contact comprises tungsten. The gate contact is configured to be electrically coupled to a signal output.

[0012] In some embodiments, the semiconductor device further includes an auxiliary layer disposed between the first contact point and the first impurity region. The auxiliary layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0013] In some embodiments, the semiconductor device further includes a plurality of gate spacers disposed on the substrate and on both sides of the gate structure. The plurality of gate spacers comprises silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide.

[0014] In some embodiments, the semiconductor device further includes a plurality of lightly doped regions disposed in the substrate and beneath the plurality of gate spacers. The plurality of lightly doped regions are doped with phosphorus, arsenic, antimony, or boron.

[0015] In some embodiments, the width of the first impurity region is greater than the width of the second impurity region.

[0016] In some embodiments, the gate structure includes a gate isolation layer disposed on the substrate; and a lower gate conductive layer disposed on the gate isolation layer. The gate contact is disposed on the lower gate conductive layer.

[0017] In some embodiments, the semiconductor device further includes a gate-on conductive layer disposed between the gate contact and the gate-below conductive layer. The gate-on conductive layer comprises titanium silicide, nickel silicide, nickel-platinum silicide, tantalum silicide, or cobalt silicide.

[0018] In some embodiments, one sidewall of the first contact point is substantially vertical.

[0019] In some embodiments, the semiconductor device further includes a capping layer disposed on the substrate and covering the gate structure.

[0020] In some embodiments, one sidewall of the first contact point is generally tapered.

[0021] In some embodiments, the semiconductor device further includes a well layer disposed in the substrate. The first impurity region and the second impurity region are disposed in the well layer.

[0022] In some embodiments, the semiconductor device further includes a buried isolation layer disposed in the substrate. The first impurity region and the second impurity region are disposed on the buried isolation layer.

[0023] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a gate structure on the substrate; forming a first impurity region and a second impurity region on both sides of the gate structure and in the substrate; forming a first contact point on the first impurity region and including a first resistance value; and forming a second contact point on the first impurity region and including a second resistance value, the second resistance value being smaller than the first resistance value of the first contact point. The first contact point is configured to be electrically coupled to a power supply, and the second contact point is configured to be electrically coupled to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact point, and the second contact point are collectively configured as an inverter.

[0024] In some embodiments, the first contact point comprises titanium nitride or doped polycrystalline silicon, while the second contact point comprises tungsten.

[0025] Due to the design of the semiconductor device disclosed herein, an inverter can be easily implemented using the first contact point with a high resistance value. The compact design of the inverter saves actual space in the semiconductor device. Therefore, the manufacturing cost of the semiconductor device can be reduced.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the embodiments and claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0029] Figure 2This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0030] Figure 3 This is a sectional view, illustrating along... Figure 2 The section along line A-A'.

[0031] Figure 4 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 5 This is a sectional view, illustrating along... Figure 4 The section along line A-A'.

[0033] Figure 6 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0034] Figure 7 This is a sectional view, illustrating along... Figure 6 The section along line A-A'.

[0035] Figure 8 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0036] Figure 9 This is a sectional view, illustrating along... Figure 8 The section along line A-A'.

[0037] Figure 10 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0038] Figure 11 This is a sectional view, illustrating along... Figure 10 The section along line A-A'.

[0039] Figures 12 to 18 This is a sectional view, along... Figure 10 The cross-section A-A' illustrates a fabrication process of a semiconductor element according to an embodiment of the present disclosure.

[0040] Figure 19 This is a circuit diagram illustrating a semiconductor element according to an embodiment of the present disclosure.

[0041] Figures 20 to 23 This is a cross-sectional schematic diagram illustrating various semiconductor elements according to an embodiment of the present disclosure.

[0042] Figures 24 to 28 This is a cross-sectional schematic diagram illustrating a fabrication process of a semiconductor element according to another embodiment of the present disclosure.

[0043] The reference numerals in the attached figures are explained as follows:

[0044] 1A: Semiconductor components

[0045] 1B: Semiconductor components

[0046] 1C: Semiconductor components

[0047] 1D: Semiconductor components

[0048] 1E: Semiconductor components

[0049] 1F: Semiconductor components

[0050] 10: Preparation method

[0051] 101: Base

[0052] 103: Insulation layer

[0053] 105: Lightly doped region

[0054] 107: First impurity region

[0055] 109: Second impurity region

[0056] 111: Auxiliary Layer

[0057] 113: Covering layer

[0058] 115: Well Formation

[0059] 117: Embedding the isolation layer

[0060] 200: Gate structure

[0061] 201: Gate isolation layer

[0062] 203: Lower gate conductive layer

[0063] 205: Gate spacer

[0064] 207: Conductive layer on gate

[0065] 301: First contact point

[0066] 301-1: Lower part

[0067] 301-3: Upper part

[0068] 303: Second contact point

[0069] 305: Third contact point

[0070] 307: Gate contact point

[0071] 401: Barrier Layer

[0072] 501: First dielectric layer

[0073] 503: Second dielectric layer

[0074] 505: Third dielectric layer

[0075] 507: Fourth dielectric layer

[0076] 601: Barrier Materials

[0077] 603: Conductive materials

[0078] 701: First opening

[0079] 703: Second opening

[0080] AA: Active Zone

[0081] GND: Grounding potential

[0082] S11: Steps

[0083] S13: Steps

[0084] S15: Steps

[0085] S17: Steps

[0086] T1: Thickness

[0087] T2: Thickness

[0088] T3: Thickness

[0089] T4: Thickness

[0090] Vcc: Power supply

[0091] Vin: Signal Input

[0092] Vout: Signal output

[0093] W1: Width

[0094] W2: Width

[0095] W3: Width

[0096] W4: Width

[0097] Z: Direction Detailed Implementation

[0098] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0099] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0100] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0101] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0102] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0103] In this disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor devices.

[0104] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0105] It should be understood that the terms "forming," "formed," and "form" can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0106] It should be understood that the functions or steps mentioned in this disclosure may occur in a different order than in the diagrams. For example, two diagrams displayed consecutively may actually be executed approximately simultaneously, or sometimes in reverse order, depending on the functions or steps contained therein.

[0107] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 This is a sectional view, illustrating along... Figure 2 The section along line A-A'. Figure 4 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 This is a sectional view, illustrating along... Figure 4 The section along line A-A'.

[0108] Please refer to Figures 1 to 5 In step S11, a substrate 101 may be provided, an insulating layer 103 may be formed in the substrate 101 to define an active region AA, and a gate structure 200 may be formed on the active region AA and the insulating layer 103.

[0109] Please refer to Figure 2 and Figure 3The substrate 101 may be a bulk semiconductor substrate. For example, the bulk semiconductor may include an elemental semiconductor or a compound semiconductor. The elemental semiconductor may be silicon or germanium, and the compound semiconductor may be silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors.

[0110] Please refer to Figure 2 and Figure 3 A series of deposition processes can be performed to deposit a pad oxide layer (not shown) on the substrate 101, and to deposit a pad nitride layer (not shown) on the pad oxide layer. For example, the pad oxide layer may comprise silicon oxide. For example, the pad nitride layer may comprise silicon nitride. A photolithography process can be performed to form a mask layer on the pad nitride layer. The mask layer may be a photoresist layer and may define the location and pattern of the insulating layer 103.

[0111] Please refer to Figure 2 and Figure 3 An etching process, such as an anisotropic dry etching process, can be performed to remove the pad oxide layer, the pad nitride layer, and the substrate 101 not covered by the masking layer, in order to form a recess extending into the substrate 101. After the etching process, the masking layer can be removed. An isolation material can be deposited to fill the recess, and a planarization process, such as chemical mechanical polishing, can be performed sequentially to remove excess material until the remaining substrate 101 is exposed, while simultaneously forming an insulating layer 103. For example, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. The remaining substrate 101 can be considered as the active region AA.

[0112] It should be understood that, in this disclosure, silicon oxynitride represents a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide represents a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0113] It should be understood that, in the description of this disclosure, the active region AA may include a portion of the substrate 101 and a plurality of spaces above and below that portion of the substrate 101. Describing an element disposed on the active region AA means that the element is disposed on an upper surface of that portion of the substrate 101. Describing an element disposed in the active region AA means that the element is disposed within that portion of the substrate 101; however, an upper surface of the element may be flush with the upper surface of that portion of the substrate 101. Describing an element disposed above the active region AA means that the element is disposed above the upper surface of that portion of the substrate 101.

[0114] Please refer to Figure 4 and Figure 5 A layer of insulating material (not shown) can be formed to cover the active region AA and the insulating layer 103. A layer of conductive material (not shown) can be sequentially formed on the insulating material. In some embodiments, the fabrication technique of the insulating material may include a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar methods. The insulating material may have a thickness between approximately 0.5 nm and approximately 5.0 nm. Preferably, the thickness of the insulating material may be between approximately 0.5 nm and approximately 2.5 nm. It should be understood that, depending on the environment, the thickness of the insulating material can be set to an arbitrary range.

[0115] In some embodiments, for example, the insulating material may be silicon oxide. In some embodiments, for example, the insulating material may be a dielectric material with a high dielectric constant, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, metal nitride, metal aluminate, zirconium silicate, zirconium aluminate, or combinations thereof.

[0116] In some embodiments, the insulating layer may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof. In some embodiments, the insulating layer may be a multilayer structure, for example, comprising a layer of silicon oxide and another layer of a high dielectric constant dielectric material.

[0117] In some embodiments, the fabrication technique for the conductive material layer may include a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, or other suitable techniques. For example, the conductive material layer may be polycrystalline silicon, polycrystalline silicon germanium, or a combination thereof. In some embodiments, for example, the conductive material layer may be copper, tungsten, aluminum, or other suitable conductive metals. A masking layer (not shown) may be formed on the conductive material layer. For example, the masking layer may be a photoresist layer. The masking layer may define the location and pattern of the gate structure 200.

[0118] Please refer to Figure 4 and Figure 5 An etching process, such as an anisotropic dry etching process, can be performed to remove portions of the insulating material layer and the conductive material layer. After the etching process, the remaining portions of the insulating material layer and the conductive material layer can be transformed into a gate isolation layer 201 and a lower gate conductive layer 203, respectively. The gate isolation layer 201 and the lower gate conductive layer 203 are configured together to form a gate structure 200.

[0119] Figure 6 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 This is a sectional view, illustrating along... Figure 6 The section along line A-A'. Figure 8 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 9 This is a sectional view, illustrating along... Figure 8 The section along line A-A'.

[0120] Please refer to Figure 1 and Figures 6 to 9 In step S13, a plurality of lightly doped regions 105 may be formed in the active region AA and adjacent to both sides of the gate structure 200, and a plurality of gate spacers 205 may be formed on the active region AA and the insulating layer 103 and on both sides of the gate structure 200.

[0121] Please refer to Figure 6 and Figure 7 A gate structure 200 can be used as a mask to perform an implantation process to form multiple lightly doped regions 105. The multiple dopants in the implantation process can include p-type impurities (dopants) or n-type impurities (dopants). The p-type impurities can be added to an intrinsic semiconductor to create defects with multiple valence electrons. Examples of p-type dopants in a silicon-containing substrate include, but are not limited to, boron, aluminum, gallium, or indium. The n-type impurities can be added to an intrinsic semiconductor to contribute multiple free electrons to the intrinsic semiconductor. Examples of n-type dopants in a silicon-containing substrate include, but are not limited to, antimony, arsenic, and phosphorus.

[0122] In some embodiments, an annealing process may be performed to activate a plurality of lightly doped regions 105. The annealing process may have a fabrication temperature between approximately 800°C and approximately 1250°C. The annealing process may have a process duration between approximately 1 millisecond and approximately 500 milliseconds. For example, the annealing process may be a rapid thermal anneal, a laser spike anneal, or a flash anneal. During operation of the semiconductor device 1A, the plurality of lightly doped regions 105 can reduce the hot carrier effect.

[0123] It should be understood that the term "about" modifies an ingredient, a quantity of a component, or a reactant of this disclosure, indicating a possible variation in numerical quantity, for example, through typical measurements and liquid handling procedures used to produce concentrates or solutions. Furthermore, variation can arise from unintentional errors in the measurement procedures applied to the manufacture of the components or the implementation of the methods or similar methods, differences in manufacturing, source, or purity of the component. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0124] Please refer to Figure 8 and Figure 9 A layer of insulating material can be conformally formed in such a way as Figure 7 On the described intermediate semiconductor device. For example, the fabrication technique for this isolation material may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. For example, the isolation material may be silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, the like, or combinations thereof. An etching process may be performed to remove portions of the isolation material and simultaneously form a plurality of gate spacers 205. The plurality of gate spacers 205 may be formed on a plurality of lightly doped regions 105.

[0125] Figure 10 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 11 This is a sectional view, illustrating along... Figure 10 The section along line A-A'. Figures 12 to 18 This is a sectional view, along... Figure 10 The cross-section along line A-A' illustrates a fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0126] Please refer to Figure 1 and Figures 10 to 13In step S15, a first impurity region 107 and a second impurity region 109 may be formed in the active region AA, a plurality of auxiliary layers 111 may be formed on the first impurity region 107 and the second impurity region 109, a gate conductive layer 207 may be formed on the gate structure 200, and a first dielectric layer 501 may be formed above the substrate 101 and the insulating layer 103.

[0127] Please refer to Figure 10 and Figure 11 An implantation process can be performed using the gate structure 200 and a plurality of gate spacers 205 as a mask to form a first impurity region 107 and a second impurity region 109. The first impurity region 107 and the second impurity region 109 are respectively formed on both sides adjacent to the gate structure 200 and in the active region AA. The width W1 of the first impurity region 107 is greater than the width W2 of the second impurity region 109.

[0128] For example, the dopant used in the implantation process may be phosphorus, arsenic, antimony, or boron. In some embodiments, the concentration of the dopant in the first impurity region 107 and the second impurity region 109 may be between approximately 4 × 10⁻⁶. 20 atoms / cm 3 Up to approximately 2×10 21 atoms / cm 3 The concentration of the dopant in the first impurity region 107 and the second impurity region 109 may be greater than the concentration of the dopant in the plurality of lightly doped regions. The first impurity region 107 and the second impurity region 109 may have an electrical type, such as n-type or p-type. The electrical type of the first impurity region 107 or the second impurity region 109 may be the same as the electrical type of the plurality of lightly doped regions 105. An annealing process may be performed to activate the first impurity region 107 and the second impurity region 109. The annealing process may have a process temperature between approximately 800°C and approximately 1250°C. The annealing process may have a process duration between approximately 1 millisecond and approximately 500 milliseconds. For example, the annealing process may be a rapid thermal anneal, a laser spike anneal, or a flash lamp anneal.

[0129] Please refer to Figure 12 A layer of conductive material (not shown) can be conformally formed on such a surface. Figure 11 The described intermediate semiconductor element is covered with a first impurity region 107, a second impurity region 109, a gate under-gate conductive layer 203, a plurality of gate spacers 205, and an insulating layer 103. For example, the conductive material may include titanium, nickel, platinum, tantalum, or cobalt.

[0130] A heat treatment can be performed sequentially. During the heat treatment, multiple metal atoms of the conductive material can chemically react with multiple silicon atoms of the first impurity region 107, the second impurity region 109, and the under-gate conductive layer 203 to respectively form multiple auxiliary layers 111 and the under-gate conductive layer 207. The multiple auxiliary layers 111 and the under-gate conductive layer 207 may contain titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The heat treatment can be a dynamic surface annealing process. After the heat treatment, a cleaning process can be performed to remove unreacted conductive material. The cleaning process can use etchants such as hydrogen peroxide and SC-1 solution. The multiple auxiliary layers 111 and the under-gate conductive layer 207 may have a thickness between approximately 2 nm and approximately 20 nm and can act as ohmic contacts to reduce the contact resistance of the first impurity region 107, the second impurity region 109, and the under-gate conductive layer 203.

[0131] Please refer to Figure 13 The first dielectric layer 501 can be formed in such a way as Figure 12 The described intermediate semiconductor element is covered with a plurality of auxiliary layers 111, a gate conductive layer 207, a plurality of gate spacers 205, and an insulating layer 103. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a generally flat surface for subsequent processing steps. For example, the fabrication technique of the first dielectric layer 501 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. In some embodiments, the first dielectric layer 501 may be deposited using a silicate or silicon source, some dopant sources, and an ozone source. For example, the dopant source may be triethylborate, triethylphosphate, triethylphosphite, trimethylphosphate, or trimethylphosphite. For example, the silicate or silicon source may be tetramethylorthosilicate. The dopant source may result in a plurality of impurity atoms in the first dielectric layer 501, such as phosphorus or boron. In some embodiments, the first dielectric layer 501 can be formed without any dopant source.

[0132] Please refer to Figure 1 and Figures 14 to 19 In step S17, a first contact point 301, a second contact point 303, a third contact point 305 and a gate contact point 307 may be formed in the first dielectric layer 501.

[0133] Please refer to Figure 14A masking layer (not shown) may be formed on the first dielectric layer 501 to define the positions and patterns of the second contact 303, the third contact 305, and the gate contact 307. An etching process, such as anisotropic dry etching, may be performed to form a plurality of first apertures 701. In some embodiments, the sidewalls of the plurality of first apertures 701 may be substantially vertical. A plurality of auxiliary layers 111 and the gate conductive layer 207 may be exposed respectively via the plurality of first apertures 701.

[0134] It should be understood that, in the description of this disclosure, if there is a vertical plane, and the deviation of a surface from the vertical plane does not exceed three times the root mean square roughness of the surface, then the surface is "substantiallyvertical".

[0135] Please refer to Figure 15 A barrier material 601 may be conformally formed in a plurality of first openings 701 and on the upper surface of the first dielectric layer 501. For example, the barrier material 601 may comprise titanium nitride.

[0136] In some embodiments, the fabrication technique for the barrier material 601 may include chemical vapor deposition. In some embodiments, the preparation of the barrier material 601 may include a source gas introduction step, a first scavenging step, a reactant flow step, and a second scavenging step. The source gas introduction step, the first scavenging step, the reactant flow step, and the second scavenging step may be represented as a cycle. Multiple cycles may be performed to obtain the desired thickness of the barrier material 601.

[0137] like Figure 14 The described intermediate semiconductor device can be placed in a reaction chamber and preheated to a predetermined temperature. In the source gas introduction step, a source gas containing a precursor and a reducing agent can be introduced into the reaction chamber. It should be understood that the precursor and the reducing agent can be injected using different inlet valves, but are not limited to this. The precursor can diffuse across the boundary layer and reach... Figure 14 The described intermediate semiconductor element has a surface (e.g., the upper surface of the first dielectric layer 501 and the inner walls of each of the plurality of first openings 701). The precursor can be adsorbed onto the aforementioned surface and subsequently migrate thereon. The adsorbed precursor can react with the reducing agent on the aforementioned surface to produce a plurality of solid byproducts and a plurality of gaseous byproducts. The solid byproducts can form nuclei on the aforementioned surface. The nuclei can grow into a plurality of islands, which can merge on the aforementioned surface to form a continuous thin film. In the first scavenging step, a scavenging gas, such as argon, can be injected into the reaction chamber to remove the gaseous byproducts, unreacted precursors, and unreacted reactants.

[0138] In the reactant flow step, the reactant may be introduced individually into the reaction chamber to transform the continuous film on the aforementioned surface. In the second scavenging step, a scavenging gas, such as argon, may be injected into the reaction chamber to remove the gaseous byproducts and unreacted reactants.

[0139] For example, the precursor can be titanium tetrachloride. The reducing agent can be hydrogen gas. The reactant can be ammonia. In the source gas introduction step, titanium tetrachloride and hydrogen gas can react on the surface to form a titanium film and gaseous hydrogen chloride. In the reactant flow step, ammonia can react with the aforementioned titanium film formed on the surface to form the barrier material 601 containing titanium nitride.

[0140] In some embodiments, plasma can be used to assist in the preparation of the barrier material 601 using chemical vapor deposition. For example, the plasma source can be argon, hydrogen, or a combination thereof.

[0141] In some embodiments, the fabrication technique of the barrier material 601 may include atomic layer deposition, such as photo-assisted atomic layer deposition or liquid-injection atomic layer deposition. In some embodiments, the preparation of the barrier material 601 includes a first precursor introduction step, a first removal step, a second precursor introduction step, and a second removal step. The first precursor introduction step, the first removal step, the second precursor introduction step, and the second removal step may be represented as a cycle. Multiple cycles may be performed to obtain the desired thickness of the barrier material 601.

[0142] In some embodiments, such as Figure 14 The described intermediate semiconductor device can be placed in a reaction chamber. In the first precursor introduction step, a first precursor can be introduced into the reaction chamber. The first precursor can diffuse across the boundary layer and reach, as... Figure 14 The surface of the described intermediate semiconductor device. The first precursor can be adsorbed onto the aforementioned surface to form a monolayer on a single atomic layer plane. In the first scavenging step, a scavenging gas, such as argon, can be injected into the reaction chamber to remove unreacted first precursor.

[0143] In the second precursor introduction step, a second precursor may be introduced into the reaction chamber. The second precursor can react with the monolayer, transforming the monolayer into the barrier material 601. In the second scavenging step, a scavenging gas, such as argon, may be injected into the reaction chamber to remove unreacted second precursor and gaseous byproducts. Compared to chemical vapor deposition, because the first and second precursors are introduced separately, particle generation caused by gas-phase reactions can be suppressed.

[0144] For example, the first precursor can be titanium tetrachloride. The second precursor can be ammonia. The adsorbed titanium tetrachloride can form a titanium monolayer. The ammonia in the second precursor introduction step can react with the titanium monolayer and transform the titanium monolayer into the barrier material 601.

[0145] In some embodiments, plasma can be used to assist in the preparation of the barrier material 601 using atomic layer deposition. For example, the plasma source can be argon, hydrogen, oxygen, or a combination thereof. In some embodiments, the oxygen source can be, for example, water, oxygen, or ozone. In some embodiments, co-reactants can be introduced into the reaction chamber. The co-reactants can be selected from hydrogen, hydrogen plasma, oxygen, air, water, ammonia, hydrazines, alkylhydrazines, boranes, silanes, ozone, and combinations thereof.

[0146] In some embodiments, the preparation of the barrier material 601 can be performed using the following process conditions: The substrate temperature can be between approximately 160°C and approximately 300°C. The evaporator temperature can be approximately 175°C. The pressure in the reaction chamber can be approximately 5 mbar. The solvent used for the first precursor and the second precursor can be toluene.

[0147] Please refer to Figure 15 A conductive material 603 can be formed to fill the plurality of first openings 701. For example, the fabrication technique of the conductive material 603 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, or similar techniques. For example, the conductive material 603 may be tungsten, copper, aluminum, or the like.

[0148] Please refer to Figure 16A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the first dielectric layer 501 is exposed to remove excess material, providing a generally flat surface for subsequent processing steps, and simultaneously forming a second contact 303, a third contact 305, a gate contact 307, and a plurality of barrier layers 401. The second contact 303 may be formed on the first impurity region 107. The third contact 305 may be formed on the second impurity region 109. The gate contact 307 may be formed on the under-gate conductive layer 203. The second contact 303 and the barrier layers 401 as a whole may have a first resistance value.

[0149] Please refer to Figure 17 A masking layer (not shown) may be formed on the first dielectric layer 501 to define the location and pattern of the first contact point 301. An etching process, such as an anisotropic dry etching process, may be performed to form a second aperture 703. In some embodiments, the sidewalls of the second aperture 703 may be generally vertical. An auxiliary layer 111 formed on the first impurity region 107 may be exposed via the second aperture 703.

[0150] Please refer to Figure 18 A conductive material layer (not shown) can be formed to fill the second opening 703. For example, the fabrication technique for this conductive material layer may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, or similar techniques. For example, the conductive material may be tungsten nitride, polycrystalline silicon, doped polycrystalline silicon, or the like. A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the first dielectric layer 501 is exposed to remove excess material, providing a generally flat surface for subsequent processing steps, and simultaneously forming the first contact point 301. The first contact point 301 may have a width W3, which is smaller than the width W4 of the second contact point 303. The first contact point 301 may be formed on the first impurity region 107. The first contact point 301 may have a second resistance value. The second resistance value of the first contact point 301 may be greater than the first resistance value of the second contact point 303, the third contact point 305, or the gate contact point 307.

[0151] Please refer to Figure 18 The first impurity region 107, the second impurity region 109, the gate structure 200, the first contact 301, the second contact 303, the third contact 305, and the gate contact 307 are configured together as an inverter. In some embodiments, the substrate 101, the plurality of lightly doped regions 104, and the plurality of barrier layers 401 can also be considered as part of the inverter.

[0152] Figure 19 This is a circuit diagram illustrating a semiconductor element 1A according to an embodiment of the present disclosure.

[0153] Please refer to Figure 19The first contact 301 is electrically coupled to a power supply Vcc. The second contact 303 is electrically coupled to a signal output Vout. The third contact 305 is electrically coupled to a ground potential GND. The gate contact 307 is electrically coupled to a signal input Vin. The gate structure 200 is electrically coupled to the signal input Vin via the gate contact 307. The first impurity region 107 is electrically coupled to the signal output Vout and the power supply Vcc via the second contact 303 and the first contact 301, respectively. The second impurity region 109 is electrically coupled to the ground potential GND via the third contact 305.

[0154] For example, when no signal input Vin is provided (Vin = 0), current can flow from the power supply Vcc through the first impurity region 107 and the second contact 303 to the signal output (Vout = 1). As another example, when a signal input Vin is provided (Vin = 1), current can flow from the power supply Vcc through the first impurity region 107, the channel region between the first impurity region 107 and the second impurity region 109, the second impurity region 109, and the third contact 305 to the ground potential GND. Therefore, the signal output Vout may not exist (Vout = 0).

[0155] Figures 20 to 23 This is a cross-sectional schematic diagram illustrating various semiconductor elements 1B, 1C, 1D, and 1E according to an embodiment of the present disclosure.

[0156] Please refer to Figure 20 Semiconductor element 1B may have similar characteristics to, for example... Figure 18 The structure described. In Figure 20 The same or similar Figure 18 The components have been labeled with similar component numbers, and their redundant descriptions have been omitted.

[0157] Please refer to Figure 20 A well layer 115 may be disposed in the active region AA of the substrate 101. Multiple lightly doped regions 105, a first impurity region 107, and a second impurity region 109 may be disposed in the well layer 115. The well layer 115 may be doped with multiple dopants, such as phosphorus, arsenic, antimony, or boron. The concentration of the dopants in the well layer 115 may be less than the concentration of the dopants in the multiple lightly doped regions 105. The well layer 115 may have an electrical type different from the electrical type of the first impurity region 107.

[0158] Please refer to Figure 21 Semiconductor element 1C may have similar characteristics to, for example Figure 18 The structure described. In Figure 21 The same or similar Figure 18 The components have been labeled with similar component numbers, and their redundant descriptions have been omitted.

[0159] Please refer to Figure 21 An embedded isolation layer 117 may be disposed in the substrate 101. A first impurity region 107 and a second impurity region 109 may be disposed on the embedded isolation layer 117. In some embodiments, the embedded isolation layer 117 may be a crystalline or non-crystalline dielectric material, such as an oxide and / or a nitride. In one example, the embedded isolation layer 117 may be a dielectric oxide, such as silicon dioxide. In another example, the embedded isolation layer 117 may be a dielectric nitride, such as silicon nitride or boron nitride. In yet another example, the embedded isolation layer 117 may be a stack of a dielectric oxide and a dielectric nitride. In some embodiments, a stack of silicon dioxide and silicon nitride or boron nitride in any order may be used as the embedded isolation layer 117. The embedded isolation layer 117 may have a thickness between 10 nm and 200 nm, although other thicknesses less than or greater than the aforementioned thickness range may be used as the thickness of the embedded isolation layer 117. The embedded isolation layer 117 can reduce the leakage current between the first impurity region 107 and the second impurity region 109.

[0160] Please refer to Figure 22 Semiconductor element 1D can have similar characteristics to, for example... Figure 18 The structure described. In Figure 22 The same or similar Figure 18 The components have been labeled with similar component numbers, and their repetitive descriptions have been omitted. The sidewalls of the first contact point 301, the second contact point 303, the third contact point 305, and the gate contact point 307 may be tapered.

[0161] Please refer to Figure 23 Semiconductor element 1E may have similar characteristics to, for example Figure 22 The structure described. In Figure 23 The same or similar Figure 22 The components have been labeled with similar component numbers, and their redundant descriptions have been omitted.

[0162] Please refer to Figure 23 A capping layer 113 may be provided to cover the active region AA, insulating layer 103, multiple auxiliary layers 111, multiple gate spacers 205, and gate conductive layer 207 of the substrate 101. For example, the capping layer 113 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, other semiconductor oxides, other semiconductor nitrides, or combinations thereof. First contact point 301, second contact point 303, third contact point 305, and gate contact point 307 may be disposed along the capping layer 113 to respectively contact the multiple auxiliary layers 111 and the gate conductive layer 207.

[0163] Figures 24 to 28 This is a cross-sectional schematic diagram illustrating a fabrication process of a semiconductor device 1F according to another embodiment of the present disclosure. Please refer to... Figure 24 An intermediate semiconductor device can be similar to, for example Figures 2 to 13 The process described herein is used to manufacture the first dielectric layer 501. The first dielectric layer 501 may include multiple impurity atoms, such as phosphorus or boron. The first dielectric layer 501 may have a thickness T1.

[0164] Please refer to Figure 24 A second dielectric layer 503 may be formed on the first dielectric layer 501. In some embodiments, the second dielectric layer 503 may have a thickness T2, which is smaller than the thickness T1 of the first dielectric layer 501. For example, the fabrication technique of the second dielectric layer 503 may include chemical vapor deposition or plasma-enhanced chemical vapor deposition. In some embodiments, the second dielectric layer 503 may be deposited using a silicate or silicon source, some dopant sources, and an ozone source. For example, the dopant source may be triethylborate, triethylphosphate, triethylphosphite, trimethylphosphate, or trimethylphosphite. For example, the silicate or silicon source may be tetramethylorthosilicate. The dopant source may result in multiple impurity atoms in the second dielectric layer 503, such as phosphorus or boron. In some embodiments, the dopant sources for the first dielectric layer 501 and the second dielectric layer 503 may be the same. Therefore, the first dielectric layer 501 and the second dielectric layer 503 may contain the same impurity atoms. In some embodiments, the concentration of the atoms in the second dielectric layer 503 may be greater than the concentration of the atoms in the first dielectric layer 501.

[0165] Please refer to Figure 24A third dielectric layer 505 may be formed on the second dielectric layer 503. In some embodiments, the third dielectric layer 505 may have a thickness T3, which is greater than the thickness T2 of the second dielectric layer 503. In some embodiments, the thickness T3 of the third dielectric layer 505 may be greater than or equal to the thickness T1 of the first dielectric layer 501. In some embodiments, the fabrication technique of the third dielectric layer 505 may include chemical vapor deposition or plasma-enhanced chemical vapor deposition. In some embodiments, the third dielectric layer 505 may be deposited using a silicate or silicon source, some dopant sources, and an ozone source. For example, the dopant source may be triethylborate, triethylphosphate, triethylphosphite, trimethylphosphate, or trimethylphosphite. For example, the silicate or silicon source may be tetramethylorthosilicate. The dopant source can result in multiple impurity atoms in the third dielectric layer 505, such as phosphorus or boron. In some embodiments, the dopant source of the third dielectric layer 505 may be different from the dopant source of the second dielectric layer 503. Therefore, the third dielectric layer 505 and the second dielectric layer 503 may contain different impurity atoms.

[0166] Please refer to Figure 24A fourth dielectric layer 507 may be formed on the third dielectric layer 505. In some embodiments, the fourth dielectric layer 507 may have a thickness T4, which is greater than or equal to the thickness T3 of the third dielectric layer 505. The thickness T4 of the fourth dielectric layer 507 may be greater than the thickness T2 of the second dielectric layer 503. For example, the fabrication technique of the fourth dielectric layer 507 may include chemical vapor deposition or plasma-enhanced chemical vapor deposition. In some embodiments, the fourth dielectric layer 507 may be deposited using a silicate or silicon source, some dopant sources, and an ozone source. For example, the dopant source may be triethylborate, triethylphosphate, triethylphosphite, trimethylphosphate, or trimethylphosphite. For example, the silicate or silicon source may be tetramethylorthosilicate. The dopant source can result in a plurality of impurity atoms in the fourth dielectric layer 507, such as phosphorus or boron. In some embodiments, the dopant source of the fourth dielectric layer 507 may be the same as the dopant source of the third dielectric layer 505. Therefore, the fourth dielectric layer 507 and the third dielectric layer 505 may contain the same impurity atoms. In some embodiments, the concentration of the atoms in the fourth dielectric layer 507 may be greater than the concentration of the atoms in the third dielectric layer 505.

[0167] Please refer to Figure 25 A mask layer (not shown) may be formed on the fourth dielectric layer 507 to define the positions and patterns of the second contact 303, the third contact 305, and the gate contact 307. An etching process, such as an anisotropic dry etching process, may be performed to form a plurality of first apertures 701.

[0168] During etching, the concentration of the atoms in the dielectric layer can influence the etching behavior, thus determining the profile of the first aperture 701. The first aperture 701 can be formed by using different concentrations of the atoms in the dielectric layer and different stacking structures of the dielectric layers, resulting in different sidewall profiles between the dielectric layers. Generally, a low concentration of the atoms in the dielectric layer leads to a tapered sidewall profile. A high concentration of the atoms in the dielectric layer leads to a generally vertical sidewall profile.

[0169] For the sake of brevity, clarity, and ease of description, only one first opening 701 is described. The first opening 701 may be formed along the fourth dielectric layer 507, the third dielectric layer 505, the second dielectric layer 503, and the first dielectric layer 501. The sidewalls of the first opening 701 formed by the fourth dielectric layer 507, the third dielectric layer 505, and the second dielectric layer 503 may be substantially vertical. The sidewalls of the first opening 701 formed by the first dielectric layer 501 may be tapered.

[0170] Please refer to Figure 26 The barrier material 601 and the conductive material 603 can be similar to... Figure 15 The procedure described herein is formed in a plurality of first openings 701, and its description will not be repeated in the text.

[0171] Please refer to Figure 27 A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the fourth dielectric layer 507 is exposed to remove excess material, provide a generally flat surface for subsequent processing steps, and simultaneously form the second contact 303, the third contact 305, the gate contact 307, and a plurality of barrier layers 401.

[0172] Please refer to Figure 28 The first contact point 301 can be similar to... Figure 17 and Figure 18 The procedure described herein will not be repeated. The first contact 301 may include a lower portion 301-1 and an upper portion 301-3. The upper portion 301-3 may be disposed along the fourth dielectric layer 507, the third dielectric layer 505, and the second dielectric layer 503. The sidewall profile of the upper portion 301-3 may be generally vertical. The lower portion 301-1 may be disposed within the first dielectric layer 501. The sidewall profile of the lower portion 301-1 may be tapered. The second contact 303, the third contact 305, and the gate contact 307 may have sidewall profiles similar to those of the first contact 301, and will not be repeated herein.

[0173] One embodiment of this disclosure provides a semiconductor device including a substrate; a gate structure disposed on the substrate; a first impurity region and a second impurity region respectively disposed on opposite sides of the gate structure and in the substrate; a first contact point disposed on the first impurity region and including a first resistance value; and a second contact point disposed on the first impurity region and including a second resistance value, the second resistance value being less than the first resistance value of the first contact point. The first contact point is configured to be electrically coupled to a power supply, and the second contact point is configured to be electrically coupled to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact point, and the second contact point are collectively configured as an inverter.

[0174] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a gate structure on the substrate; forming a first impurity region and a second impurity region on both sides of the gate structure and in the substrate; forming a first contact point on the first impurity region and including a first resistance value; and forming a second contact point on the first impurity region and including a second resistance value, the second resistance value being smaller than the first resistance value of the first contact point. The first contact point is configured to be electrically coupled to a power supply, and the second contact point is configured to be electrically coupled to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact point, and the second contact point are collectively configured as an inverter.

[0175] Due to the design of the semiconductor element disclosed herein, an inverter can be easily implemented using a first contact point 301 with a high resistance value. The compact design of this inverter saves actual space in the semiconductor element 1A. Therefore, the manufacturing cost of the semiconductor element 1A can be reduced.

[0176] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0177] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One base; A gate structure is disposed on the substrate; A first impurity region and a second impurity region are respectively located on both sides of the gate structure and in the substrate; A first contact point is disposed on the first impurity region and includes a first resistance value; and A second contact point is disposed on the first impurity region and includes a second resistance value, the second resistance value being less than the first resistance value of the first contact point; A third contact point is provided on the second impurity region and is configured to be electrically coupled to a ground potential; A gate contact is disposed on the gate structure and configured to be electrically coupled to a signal output; The first contact point is configured to be electrically coupled to a power supply, and the second contact point is configured to be electrically coupled to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact point, the second contact point, the third contact point, and the gate contact point are configured together to form an inverter.

2. The semiconductor device of claim 1, wherein the first contact point comprises titanium nitride or doped polycrystalline silicon.

3. The semiconductor device of claim 1, wherein the second contact point comprises tungsten.

4. The semiconductor device of claim 3 further includes a barrier layer disposed between the second contact point and the first impurity region, and disposed on a sidewall of the second contact point, wherein the barrier layer comprises tungsten nitride.

5. The semiconductor element of claim 4, wherein the width of the first contact point is smaller than the width of the second contact point.

6. The semiconductor device of claim 5 further includes a third contact point disposed on the second impurity region; wherein the third contact point comprises tungsten; wherein the third contact point is configured to be electrically coupled to a ground potential.

7. The semiconductor device of claim 6 further includes a gate contact disposed on the gate structure; wherein the gate contact comprises tungsten; wherein the gate contact is configured to be electrically coupled to a signal output.

8. The semiconductor device of claim 7 further includes an auxiliary layer disposed between the first contact point and the first impurity region; wherein the auxiliary layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

9. The semiconductor device of claim 8 further includes a plurality of gate spacers disposed on the substrate and on both sides of the gate structure; wherein the plurality of gate spacers comprises silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide.

10. The semiconductor device of claim 9, further comprising a plurality of lightly doped regions disposed in the substrate and under the plurality of gate spacers; wherein the plurality of lightly doped regions are doped with phosphorus, arsenic, antimony or boron.

11. The semiconductor device of claim 10, wherein the width of the first impurity region is greater than the width of the second impurity region.

12. The semiconductor device of claim 11, wherein the gate structure comprises: A gate isolation layer is disposed on the substrate; as well as A gate-below conductive layer is disposed on the gate isolation layer; The gate contact point is located on the conductive layer below the gate.

13. The semiconductor device of claim 12, further comprising a gate-on conductive layer disposed between the gate contact and the gate-below conductive layer; wherein the gate-on conductive layer comprises titanium silicide, nickel silicide, nickel-platinum silicide, tantalum silicide, or cobalt silicide.

14. The semiconductor element of claim 1, wherein one sidewall of the first contact point is substantially vertical.

15. The semiconductor device of claim 1, further comprising a capping layer disposed on the substrate and covering the gate structure.

16. The semiconductor element of claim 1, wherein one sidewall of the first contact point is generally tapered.

17. The semiconductor device of claim 1, further comprising a well layer disposed in the substrate; wherein the first impurity region and the second impurity region are disposed in the well layer.

18. The semiconductor device of claim 1, further comprising a buried isolation layer disposed in the substrate; wherein the first impurity region and the second impurity region are disposed on the buried isolation layer.

19. A method for fabricating a semiconductor element, comprising: Provide a base; A gate structure is formed on the substrate; A first impurity region and a second impurity region are respectively formed on both sides of the gate structure and in the substrate; A first contact point is formed on the first impurity region and includes a first resistance value; and A second contact point is formed on the first impurity region and includes a second resistance value, the second resistance value being smaller than the first resistance value of the first contact point; A third contact point is formed on the second impurity region and configured to be electrically coupled to a ground potential; A gate contact is formed on the gate structure and configured to be electrically coupled to a signal output; The first contact point is configured to be electrically coupled to a power supply, and the second contact point is configured to be electrically coupled to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact point, the second contact point, the third contact point, and the gate contact point are configured together to form an inverter.

20. The method for fabricating a semiconductor element as claimed in claim 19, wherein the first contact point comprises titanium nitride or doped polycrystalline silicon, and the second contact point comprises tungsten.

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