A radio frequency switch structure and a radio frequency switch module

Abstract

The application relates to a radio frequency switch structure and a radio frequency switch module, and belongs to the radio frequency switch field.The radio frequency switch structure comprises a signal input end, a signal output end and a transistor stack; the transistor stack comprises N transistors which are connected in series; the signal input end is connected with the first transistor of the transistor stack; the signal output end is connected with the Nth transistor of the transistor stack; and in the polysilicon layer, at least one of the polysilicon regions where the gate electrodes of the preset gate electrode interdigital electrodes of the N transistors are located and the corresponding first regions in the metal layer are connected through a first connecting structure. The radio frequency switch structure of the application makes the actual resistance on the preset gate electrode interdigital electrodes in the transistor much smaller than the square resistance of the polysilicon layer, thereby avoiding the problem that the voltage drops of different gate electrode interdigital electrodes in the transistor are too large due to the too large square resistance of the polysilicon layer where the gate electrode interdigital electrodes of the transistor are located, and effectively improving the voltage resistance of the transistor and the stability of the radio frequency switch structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency switch, in particular to a radio frequency switch structure and a radio frequency switch module. BACKGROUND

[0002] In the prior art radio frequency switch structure, the transistor stack contains several transistor interdigital M1, M2, …, MN, each transistor interdigital includes a gate, a source and a drain. In the actual process design process, the gate interdigital of each transistor is arranged on the polysilicon layer (i.e. Poly layer), and the resistance of the square resistance of the polysilicon layer (i.e. Poly layer) is often large, so when the number of gate interdigital in the transistor is too large, the problem of excessive voltage drop between different gate interdigital in the transistor will be caused, thereby affecting the voltage resistance of the transistor and affecting the normal work of the radio frequency switch structure. SUMMARY

[0003] In view of the above technical problems, the present application provides a radio frequency switch structure and a radio frequency switch module to solve the problem of excessive voltage drop between different gate interdigital in the transistor of the prior art radio frequency switch structure.

[0004] In a first aspect, the present application provides a radio frequency switch structure, comprising:

[0005] a signal input end, a signal output end and a transistor stack;

[0006] The transistor stack includes N transistors connected in series, N>1, the signal input end is connected with the first transistor of the transistor stack, and the signal output end is connected with the Nth transistor of the transistor stack;

[0007] Each transistor is realized as an interdigital configuration device, and each transistor includes M gate interdigital, M>1;

[0008] In the polysilicon layer, the polysilicon region where at least one preset gate interdigital in the transistor is located and the corresponding first region in the metal layer are connected by a first connecting structure.

[0009] Optionally, the projection of the polysilicon region and the first region in the longitudinal direction at least partially overlaps.

[0010] Optionally, in the M gate interdigital of the transistor, every interval set number of gate interdigital is set as the preset gate interdigital.

[0011] Optionally, the metal layer where the first region is located is the adjacent upper layer of the polysilicon layer where the polysilicon region is located, or the metal layer where the first region is located is the adjacent lower layer of the polysilicon layer where the polysilicon region is located.

[0012] Optionally, the polysilicon layer has a square resistance of Z1, the metal layer has a square resistance of Z2, and the preset gate finger has a resistance Z0=(Z1*Z2) / (Z1+Z2).

[0013] Optionally, the first connecting structure is a metal connecting column.

[0014] Optionally, a first via hole is formed in the polysilicon layer, and a second via hole is formed in the metal layer, and the first via hole is connected to the second via hole through the first connecting structure.

[0015] Optionally, the active region layer and the metal layer in the transistor are connected through a second connecting structure, a third via hole is formed in the active region layer, and a fourth via hole is formed in the metal layer, and the third via hole is connected to the fourth via hole through the second connecting structure.

[0016] Optionally, the first via hole and the third via hole have a spacing with a set distance, and the second via hole and the fourth via hole have a spacing with a set distance.

[0017] Optionally, the active region layer below the preset gate finger has a hollow structure, and the position of the hollow structure is arranged in the extension direction of the first connecting structure.

[0018] Optionally, a bias control voltage output by a bias voltage end is loaded on at least one gate finger of the transistor through the polysilicon layer.

[0019] In a second aspect, the present application provides a radio frequency switch module, comprising:

[0020] The radio frequency switch module comprises a substrate and a radio frequency switch structure according to the first aspect arranged on the substrate.

[0021] The above scheme has the following beneficial effects:

[0022] The radio frequency switch structure and the radio frequency switch module of the present application comprise a signal input end, a signal output end and a transistor stack; the transistor stack comprises N transistors connected in series, N>1, the signal input end is connected with the first transistor of the transistor stack, and the signal output end is connected with the Nth transistor of the transistor stack; each transistor is realized as an interdigital configuration device, and each transistor comprises M gate interdigitations, M>1; in a polysilicon layer, at least one preset gate interdigitations in each transistor is connected between the polysilicon region and the corresponding first region in the metal layer through a first connection structure; by connecting the polysilicon region of one or several preset gate interdigitations in the transistor to the preset first region in the adjacent metal layer through the first connection structure, the actual resistance on the preset gate interdigitations in the transistor is far less than the square resistance of the polysilicon layer, thereby the problem of excessive voltage drop in different gate interdigitations in the transistor due to the excessive square resistance of the polysilicon layer (Poly layer) where the gate interdigitations of the transistor are located can be avoided, and the voltage resistance of the transistor is effectively improved, so as to improve the stable working performance of the radio frequency switch structure. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is the radio frequency switch structure circuit diagram provided in the first embodiment of the present application;

[0024] Figure 2 is the transistor structure diagram in the radio frequency switch structure provided in the first embodiment of the present application;

[0025] Figure 3 is the radio frequency switch module structure diagram provided in the third embodiment of the present application;

[0026] The symbols are explained as follows:

[0027] 1, polysilicon layer; 101, polysilicon region; 2, metal layer; 201, first region; 3, first connection structure; 41, N-type source region; 42, P-type source region; 51, P-type well region; 52, N-type well region; 6, substrate; 7, source electrode; 8, drain electrode; 9, second connection structure; 31, substrate; 32, radio frequency switch chip; 33, radio frequency switch structure; 34, antenna. DETAILED DESCRIPTION

[0028] In order to make the technical problems, technical solutions and beneficial effects of the present application more clearly understood, the present application is further described in detail below with reference to the drawings and embodiments.

[0029] It should be understood that the embodiments set forth herein represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best modes of practicing the embodiments. Upon reading the following description, those skilled in the art will understand how to implement the concepts described herein and will realize the scope of the disclosure and will realize the applicability of the concepts described herein to other applications. It should be understood that these concepts and applications fall within the scope of the disclosure and the following claims.

[0030] It should also be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0032] It should also be understood that the terms "upper", "lower", "left", "right", "front", "rear", "bottom", "intermediate", "middle", "top", and the like, can be used in this document to describe various elements as their orientation or position relationship based on the orientation or position relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore these elements should not be limited by these clauses.

[0033] These terms are only used to distinguish one element from another. For example, a first element can be referred to as an "upper" element, and similarly, a second element can be referred to as an "upper" element according to the relative orientation of these elements, without departing from the scope of the present disclosure.

[0034] It is further understood that the terms "comprise", "comprise", "comprise" and / or "comprise" as used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0036] In one embodiment, a radio frequency switch structure is provided, comprising:

[0037] Figure 1 The signal input end IN, the signal output end OUT and the transistor stack shown in the figure; wherein the transistor stack comprises N transistors M1, M2, …, MN connected in series, N>1, the signal input end IN is connected with the first end of the first transistor M1 of the transistor stack, the second end of the first transistor M1 is connected with the first end of the second transistor M2, and so on, the second end of the i-1 transistor is connected with the first end of the i transistor, wherein 2<i≤N; the Nth transistor MN of the transistor stack is connected with the signal output end OUT.

[0038] Specifically, the radio frequency switch circuit 22 comprises a radio frequency input end IN, a radio frequency output end Out and a transistor stack; the transistor stack comprises N transistors connected in series between the radio frequency input end IN and the radio frequency output end Out; in this example, the transistors are sequentially named as the first transistor M1, the second transistor M2, …, the n-th transistor Mn, the n+1-th transistor Mn+1, …, the Nth transistor MN from the radio frequency input end IN to the radio frequency output end Out. The first transistor M1, the second transistor M2, …, the n-th transistor Mn, the n+1-th transistor Mn+1, …, the Nth transistor MN are connected in series. Wherein, the series connection of the transistors here means that the source S and the drain D of the adjacent transistors are connected. For example, in this example, the drain D of the first transistor M1 is the input end In, the drain D of the second transistor M2 is connected with the source S of the first transistor, the drain D of the third transistor M3 is connected with the source S of the second transistor M2, …, and so on, the drain D of the Nth transistor MN is connected with the source S of the N-1th transistor MN-1; wherein the source S of the Nth transistor MN is the output end Out. Of course, according to the different types of transistors, conversely, the source of the first transistor M1 is the input end In, the source S of the second transistor M2 is connected with the drain D of the first transistor M1, the source S of the third transistor M3 is connected with the drain D of the second transistor M2, …, and so on, the source S of the Nth transistor MN is connected with the drain D of the N-1th transistor MN-1; wherein the drain D of the Nth transistor MN is also possible as the output end Out.

[0039] Each transistor of the transistor stack is implemented as an interdigital configuration device, and the total width of each transistor is calculated according to the following formula:

[0040] W = FW*F*M

[0041] Wherein, W is the total width of the transistor, FW is the width of the gate interdigital, F is the number of gate interdigital, and M is the number of parallel interdigital tubes.

[0042] Each of the transistors is implemented as an interdigital configuration device, each of the transistors includes M gate interdigital, M>1;Wherein, in the polysilicon layer, the polysilicon region where at least one preset gate interdigital in the transistor is located and the corresponding first region in the metal layer are connected by the first connecting structure.

[0043] Referring to Figure 2 The transistor structure is shown, each transistor includes a plurality of interdigital tubes. For example: the transistor on the right side of the figure is a first interdigital tube (for example: NMOS tube), and the transistor on the left side is a second interdigital tube (for example: PMOS tube). Each interdigital tube includes gate interdigital, source interdigital and drain interdigital. Wherein, the gate interdigital of the first interdigital tube is arranged in the polysilicon layer 1. In Figure 2 The polysilicon region 101 where at least one preset gate interdigital in the transistor is located and the corresponding first region 201 in the metal layer 2 are connected by the first connecting structure 3 in the polysilicon layer 1 where the gate interdigital is located. In this embodiment, only Figure 2 The connection relationship between the polysilicon region 101 where one gate interdigital is located and the corresponding first region 201 in the metal layer 2 is shown schematically, and the connection relationship between the polysilicon region where other gate interdigital in the transistor is located and the corresponding first region 201 in the metal layer can also be connected by the first connecting structure 3.

[0044] Wherein, the polysilicon region 101 is arranged in the polysilicon layer 1, and the first region is arranged in the adjacent metal layer. In this example, the polysilicon layer 1 and the first region 201 are arranged on the adjacent two layers of the wiring layer, the adjacent two layers of the wiring layer are arranged in parallel, and the projection of the polysilicon region 101 and the first region 201 in the longitudinal direction at least partially overlaps, so that the polysilicon region 101 and the first region 201 can be connected by the first connecting structure 3.

[0045] In the embodiment, the bias control voltage Vg output by the bias voltage terminal is loaded on at least one gate interdigital electrode of the transistor through the polysilicon layer 1. Moreover, since the square resistance of the polysilicon layer 1 is Z1, the square resistance of the metal layer 2 is Z2, and the square resistance of the polysilicon layer 1 is much smaller than the square resistance of the metal layer 2, the present application connects the polysilicon region 101 of the polysilicon layer 1 and the first region 201 of the metal layer 2 through the first connection structure 3 respectively. After the polysilicon region 101 of the polysilicon layer 1 and the first region of the metal layer 2 are connected through the first connection structure 3, the actual equivalent resistance on the preset gate interdigital electrode is equivalent to the parallel value of the square resistance Z1 and the square resistance Z2, that is, the actual equivalent resistance on the preset gate interdigital electrode is:

[0046] Z0=(Z1*Z2) / (Z1+Z2)

[0047] wherein Z0 is the actual equivalent resistance on the preset gate interdigital electrode, Z1 is the square resistance (equivalent resistance) of the polysilicon layer 1, Z2 is the square resistance (equivalent resistance) of the metal layer 2, and Z2

[0048] Therefore, after one or several preset gate interdigital electrodes in the transistor are connected through the first connection structure between the polysilicon region and the corresponding first region in the metal layer, the actual equivalent resistance on the preset gate interdigital electrode is reduced, thereby solving the problem that the voltage drop of different gate interdigital electrodes in the transistor is too large due to the too large square resistance of the polysilicon layer (Poly layer) where the gate interdigital electrodes of the transistor are located, and effectively improving the voltage resistance of the transistor to improve the stable working performance of the radio frequency switch structure.

[0049] In the embodiment, the radio frequency switch structure includes a signal input terminal, a signal output terminal and a transistor stack; the transistor stack includes N transistors connected in series, N>1, the signal input terminal is connected with the first transistor of the transistor stack, and the signal output terminal is connected with the Nth transistor of the transistor stack; each transistor is realized as an interdigital device, and each transistor includes M gate interdigital electrodes, M>1; in the polysilicon layer, at least one preset gate interdigital electrode in each transistor is connected through a first connection structure between the polysilicon region and the corresponding first region in the metal layer; by connecting one or several preset gate interdigital electrodes in the transistor through the first connection structure to the preset first region in the adjacent metal layer, the actual resistance on the preset gate interdigital electrode in the transistor is much smaller than the square resistance of the polysilicon region, thereby avoiding the problem that the voltage drop of different gate interdigital electrodes in the transistor is too large due to the too large square resistance of the polysilicon layer (Poly layer) where the gate interdigital electrodes of the transistor are located, and effectively improving the voltage resistance of the transistor to improve the stable working performance of the radio frequency switch structure

[0050] The projection of the polysilicon region and the first region in the longitudinal direction is at least partially overlapped.

[0051] In an example, Figure 2 The projection of the polysilicon region 101 and the first region 201 in the longitudinal direction is in an all or partial overlapping relationship. As other embodiments, the first region 201 can be arranged in other regions of the metal layer 2 surface, so that the projection of the polysilicon region 101 and the first region in the longitudinal direction is at least partially overlapped, for example, the first region 201 is arranged in the region of the metal layer 2 surface that is adjacent to the polysilicon region 101. Figure 2 In the example shown in FIG. 1, the first region 201 is arranged in the region of the metal layer 2 surface that is adjacent to the polysilicon region 101. The first connection structure 3 is arranged to connect the polysilicon region 101 and the first region 201. The first region 201 can be arranged in other regions of the metal layer 2 surface, so that the projection of the polysilicon region 101 and the first region in the longitudinal direction is at least partially overlapped. For example, the first region 201 is arranged in the region of the metal layer 2 surface that is adjacent to the polysilicon region 101.

[0052] The metal layer where the first region is arranged is an adjacent upper layer of the polysilicon layer where the polysilicon region is arranged, or the metal layer where the first region is arranged is an adjacent lower layer of the polysilicon layer where the polysilicon region is arranged.

[0053] As an example, the metal layer where the first region is arranged is an adjacent upper layer of the polysilicon layer where the polysilicon region is arranged, and the projection of the polysilicon region and the first region in the longitudinal direction is at least partially overlapped, so that the polysilicon region 101 and the first region 201 can be connected through the first connection structure 3, thereby reducing the actual equivalent resistance on the preset gate finger, thereby solving the problem of excessive voltage drop in different gate fingers in the transistor due to excessive sheet resistance of the polysilicon layer (Poly layer) where the gate finger of the transistor is arranged, thereby effectively improving the voltage resistance of the transistor, and improving the stable working performance of the radio frequency switch structure.

[0054] As an example, the metal layer where the first region is arranged is an adjacent lower layer of the polysilicon layer where the polysilicon region is arranged, and the projection of the polysilicon region and the first region in the longitudinal direction is at least partially overlapped, so that the polysilicon region 101 and the first region 201 can be connected through the first connection structure 3, thereby reducing the actual equivalent resistance on the preset gate finger, thereby solving the problem of excessive voltage drop in different gate fingers in the transistor due to excessive sheet resistance of the polysilicon layer (Poly layer) where the gate finger of the transistor is arranged, thereby effectively improving the voltage resistance of the transistor, and improving the stable working performance of the radio frequency switch structure.

[0055] In this example, the gap between the polysilicon layer (Poly layer) where the gate finger is arranged and the metal layer where the first region is arranged can be filled with air medium or insulating medium, which can be set according to actual needs.

[0056] In an example, in order to realize the connection between the polysilicon region 101 and the first region 201, a first via (not shown in the figure) is opened on the polysilicon layer 1, a second via (not shown in the figure) is opened on the metal layer 2, and the first via is connected to the second via through the first connection structure 3. Optionally, the first connection structure can be a metal connecting column, one end of which is connected to the first via, and the other end of which is connected to the second via.

[0057] In the embodiment, Figure 2 The NMOS tube structure on the right side is sequentially provided with an N-type substrate 6, a P-type well region 51, an N-type source region 41, a polysilicon layer 1, a first connection structure 3, a dielectric layer 10, and a metal layer 2 from bottom to top. Figure 2 The PMOS tube structure on the left side is sequentially provided with an N-type substrate 6, an N-type well region 52, a P-type source region 42, a source 7, a drain 8, a polysilicon layer 1, a dielectric layer 10, and a metal layer 2 from bottom to top.

[0058] In an example, the drain 8 on the P-type source region 42 of the PMOS tube active region layer (i.e. Figure 2 In an example, the drain 8 on the P-type source region 42 of the PMOS tube active region layer (i.e.

[0059] In an example, the second via for connecting the first connection structure 3 and the fourth via for connecting the second connection structure 9 on the metal layer 2 have a first distance.

[0060] Similarly, the first via for connecting the first connection structure 3 and the second via for connecting the second connection structure 9 also have a second distance.

[0061] The active region layer of the preset gate finger has a hollow structure, and the position of the hollow structure is arranged in the extension direction of the first connection structure.

[0062] In an example, since the lower part connected by the first connection structure between the polysilicon layer and the metal layer cannot exist the active region, the hollow structure is provided on the active region layer (i.e. N-type source region 41 in Figure 2 the extension direction of the first connection structure 3.

[0063] In the embodiment, the metal layer 1 where the first region 201 is located is the adjacent upper layer of the polysilicon layer 1 where the polysilicon region 101 is located. As another embodiment, when the transistor structure is provided with multiple metal layers, for example, one metal layer is further provided above the metal layer 1 in Figure 2 , the polysilicon region where the preset gate finger is located and the corresponding first region in the non-adjacent upper metal layer can also be connected by the first connection structure. Figure 2

[0064] In the embodiment, since the hollow structure is provided on the active region layer under the preset gate finger, and the position of the hollow structure is set in the extension direction of the first connection structure, the more the number of preset transistors in the transistor, the better the voltage resistance of the transistor, but the larger the area occupied by the transistor.

[0065] The radio frequency switch structure of the embodiment, by connecting the polysilicon region where one or several preset gate fingers of the transistor are located to the preset first region in the adjacent metal layer through the first connection structure, compared with the prior art, it is equivalent to connecting a resistance with a smaller resistance (i.e. the sheet resistance of the metal layer) in parallel with the resistance (the sheet resistance of the polysilicon layer) of the original gate finger in the transistor of the radio frequency switch structure. Since the sheet resistance of the metal layer is much smaller than the sheet resistance of the polysilicon layer, after the two sheet resistances are connected in parallel, the equivalent resistance of each preset gate finger is much smaller than the resistance of the original gate finger. On the basis of reducing the gate resistance, the problem of excessive voltage drop of different gate fingers in the transistor caused by the excessive sheet resistance of the polysilicon layer (Poly layer) where the gate finger of the transistor is located can be avoided, thereby effectively improving the voltage resistance of the transistor and improving the stable working performance of the radio frequency switch structure.

[0066] Embodiment two provides a radio frequency switch structure, which is different from the structure in embodiment one in that:

[0067] ​In the plurality of gate fingers of the transistor, every interval of a set number of gate fingers is set as a preset gate finger. Optionally, every interval of L gate fingers selects one as a preset gate finger, L≥1. For example, when L=1, in N (assuming N is an odd number) gate fingers M1, M2, …, MN, then the gate fingers M1, M3, …, MN-2, MN are sequentially selected as preset gate fingers, and each preset gate finger is connected to the corresponding first region in the polysilicon region and the metal layer through the first connection structure according to the description in the first embodiment.

[0068] Optionally, when selecting the number of preset gate fingers, at least one preset gate finger can be selected to connect the corresponding first region in the polysilicon region and the metal layer, which can still improve the voltage resistance of the transistor to some extent, thereby improving the stable working performance of the radio frequency switch structure. The more the number of preset gate fingers selected, the better the effect of improving the voltage resistance of the transistor, for example, selecting each transistor in the transistor stack as a preset gate finger can make the voltage resistance of the transistor reach the best state.

[0069] In the third embodiment, a radio frequency switch module is provided, which includes a substrate 31 and a radio frequency switch chip 32 arranged on the substrate. The radio frequency switch chip 32 has the radio frequency switch structure 33 described in the first or second embodiment. The signal input end IN of the radio frequency switch structure 33 is connected to an antenna 34 through a transmission line, and the signal output end OUT of the radio frequency switch structure 33 is used to output a radio frequency signal.

[0070] Since the specific structure of the radio frequency switch structure 33 has been clearly and completely described in the first or second embodiment, the specific structure of the radio frequency switch structure 33 will not be described again in this embodiment.

[0071] The radio frequency switch module of the present embodiment uses the radio frequency switch structure described above, which can reduce the gate resistance. The bias voltage of the transistor stack can be applied to the gate of each transistor through a smaller gate resistance, thereby improving the non-uniformity of the bias voltage on the gates of different transistors in the transistor stack, and effectively improving the stable working performance of the radio frequency switch structure.

[0072] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A radio frequency switch structure, characterized in that, include: Signal input terminals, signal output terminals, and transistor stack; The transistor stack includes N transistors connected in series, where N>1. The signal input terminal is connected to the first transistor of the transistor stack, and the signal output terminal is connected to the Nth transistor of the transistor stack. Each of the transistors is implemented as an interdigitated configuration device, and each of the transistors includes M gate interdigitates, where M>1; In the polysilicon layer, the polysilicon regions where at least two preset gate interdigitates of the transistor are located and the corresponding first regions in the metal layer are connected by a first connection structure that penetrates the dielectric layer, wherein the dielectric layer is included between the polysilicon layer and the metal layer where the first regions are located.

2. The radio frequency switch structure according to claim 1, characterized in that, The projections of the polycrystalline silicon region and the first region in the longitudinal direction at least partially overlap.

3. The radio frequency switch structure according to claim 1, characterized in that, In the M gate interdigitates of the transistor, a predetermined number of gate interdigitates are used as the preset gate interdigitates.

4. The radio frequency switch structure according to claim 1, characterized in that, The metal layer containing the first region is the adjacent upper layer of the polycrystalline silicon layer containing the polycrystalline silicon region, or the metal layer containing the first region is the adjacent lower layer of the polycrystalline silicon layer containing the polycrystalline silicon region.

5. The radio frequency switch structure according to claim 1, characterized in that, The sheet resistance of the polysilicon layer is Z1, the sheet resistance of the metal layer is Z2, and the resistance of the preset gate interdigitation is Z0 = (Z1*Z2) / (Z1+Z2).

6. The radio frequency switch structure according to claim 1, characterized in that, The first connection structure is a metal connecting column.

7. The radio frequency switch structure according to claim 1, characterized in that, A first via is formed on the polysilicon layer, and a second via is formed on the metal layer. The first via is connected to the second via through the first connection structure.

8. The radio frequency switch structure according to claim 7, characterized in that, The active region layer and the metal layer in the transistor are connected by a second connection structure. A third via is formed on the active region layer, and a fourth via is formed on the metal layer. The third via is connected to the fourth via through the second connection structure.

9. The radio frequency switch structure according to claim 8, characterized in that, The first via and the third via have a predetermined distance between them, and the second via and the fourth via have a predetermined distance between them.

10. The radio frequency switch structure according to claim 4, characterized in that, The active region layer below the preset gate interdigitation has a hollow structure, and the hollow structure is located in the extension direction of the first connection structure.

11. The radio frequency switch structure according to claim 1, characterized in that, The bias control voltage output from the bias voltage terminal is applied to at least one of the gate interdigitates of the transistor through the polysilicon layer.

12. A radio frequency switch module, characterized in that, It includes a substrate and a radio frequency switch structure as described in any one of claims 1-11 disposed on the substrate.

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