Multi-conductive layer wiring structure, array substrate and display panel

Abstract

The application is suitable for the technical field of display products, and provides a multi-conductive-layer wiring structure, which comprises a substrate, a conductive layer, a signal line, and a plurality of main lines and branch lines; the conductive layer is arranged on the substrate and comprises a first conductive layer and a second conductive layer arranged in a stack; the signal line comprises the plurality of main lines and the plurality of branch lines; the main lines are arranged in the first conductive layer; the plurality of branch lines are arranged in the second conductive layer at intervals; and the plurality of main lines and the plurality of branch lines are electrically connected. The application also provides an array substrate comprising the multi-conductive-layer wiring structure. The application also provides a display panel comprising the array substrate. The application can effectively improve the situation of electrostatic shock injury of the conductive layer, and can also improve the influence of the signal line caused by the electrostatic shock injury, thereby improving the product yield.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display products, and particularly relates to a multi-conductive-layer wiring structure, an array substrate and a display panel. BACKGROUND

[0002] When a test circuit is designed at a driving IC of a current thin-film transistor liquid crystal display (TFT-LCD) product, the wiring design of a data signal (DS) circuit has long lines and many branches. Referring to Figure 1 , the long and branched wiring design is prone to static electricity. During use of a mask, static electricity is continuously accumulated, and the high-static lines will discharge to the low-static lines in the same layer, causing static shock. The static shock will change the line width and the line spacing of the DS circuit.

[0003] Referring to Figure 2a , Figure 2b , if slight static shock is caused, the DS circuit may be short-circuited, affecting the stability of the product. Slight static shock may not cause the DS circuit to be short-circuited, but still causes the change of the properties of the TFT transistor. Since no short circuit is caused, the defect of the product cannot be detected, resulting in a low product yield and a rising cost. SUMMARY

[0004] In view of the above problems, the present application provides a multi-conductive-layer wiring structure, an array substrate and a display panel, which at least solve the problem that static shock is prone to occur between the main lines and the branches of the signal line in the prior art.

[0005] The multi-conductive-layer wiring structure provided by the present application comprises:

[0006] a substrate;

[0007] a conductive layer, which is arranged on the substrate and comprises a first conductive layer and a second conductive layer arranged in layers;

[0008] a signal line, which comprises a plurality of main lines and a plurality of branches, the plurality of main lines are arranged in the first conductive layer, the plurality of branches are arranged in the second conductive layer at intervals, and the plurality of main lines and the plurality of branches are electrically connected.

[0009] The beneficial effects of the embodiment are that the main lines and the branches of the signal line are arranged in different conductive layers, so as to improve the situation that static electricity occurs between adjacent main lines and branches, thereby improving the negative influence of static electricity on the conductive layer and the signal line.

[0010] In an embodiment, the lengths of the plurality of main lines are the same, and the lengths of the plurality of branches are the same.

[0011] The beneficial effect of the embodiment is that the main lines have the same length, and the branches also have the same length, the length difference between adjacent lines in the same layer is reduced, the electrostatic generation is improved, and the negative effect of electrostatic on the conductive layer and the signal line is further improved.

[0012] In an embodiment, the distance between the projection of each main line on the second conductive layer and the adjacent branch is equal.

[0013] In an embodiment, the second conductive layer is a source-drain electrode layer.

[0014] In an embodiment, the first conductive layer is a gate electrode layer.

[0015] In an embodiment, the first conductive layer is a pixel electrode layer.

[0016] In an embodiment, an insulating layer is arranged between the first conductive layer and the second conductive layer, and a plurality of vias are arranged in the insulating layer, and each branch is connected to the main line through a corresponding via.

[0017] The beneficial effect of the embodiment is that the insulating layer is arranged between the first conductive layer and the second conductive layer, which further avoids electrostatic between the main line and the branch, thereby further improving the negative effect of electrostatic on the conductive layer and the signal line.

[0018] In an embodiment, the substrate is one of a glass substrate, a metal substrate, and a ceramic substrate.

[0019] The application also provides an array substrate comprising the multi-conductive layer wiring structure.

[0020] The application also provides a display panel comprising the array substrate.

[0021] The application improves the prior art that the branches of the DS line are prone to electrostatic shock.

[0022] The main line and the branch of the signal line are arranged on different conductive layers, so as to avoid electrostatic between adjacent main lines and branches, thereby protecting the conductive layer and the signal line.

[0023] The display panel provided by the embodiment has the following beneficial effects:

[0024] The multi-conductive layer wiring structure reduces or avoids the occurrence of electrostatic breakdown, improves the damage of electrostatic to the conductive layer and the signal line, improves the yield of the product, improves the stability of the product, and prolongs the service life of the product.

[0025] The application has simple structure, can effectively improve the electrostatic shock injury of the conductive layer, and can also improve the influence of the electrostatic shock injury on the signal line, and has high practicability. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0027] Figure 1 The arrangement schematic diagram of the main line and the branch in the same conductive layer.

[0028] Figure 2a The arrangement schematic diagram of the main line and the branch in the same conductive layer. Figure 1 The partial enlarged view of one case of the electrostatic shock injury at A in the middle.

[0029] Figure 2b The arrangement schematic diagram of the main line and the branch in the same conductive layer. Figure 1 The partial enlarged view of another case of the electrostatic shock injury at A in the middle.

[0030] Figure 3 The arrangement schematic diagram of the conductive layer of the multi-conductive layer wiring structure provided by the embodiment of the present application.

[0031] Figure 4 The schematic diagram of the signal line in the multi-conductive layer wiring structure provided by the embodiment of the present application.

[0032] Figure 5 The arrangement schematic diagram of the conductive layer of the multi-conductive layer wiring structure provided by another embodiment of the present application.

[0033] The meaning of the mark in the figure is:

[0034] 10, substrate;

[0035] 20, conductive layer; 21, first conductive layer; 22, second conductive layer;

[0036] 30, signal line; 31, main line; 32, branch; 33, via hole;

[0037] 40, insulating layer. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with the drawings, i.e. embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not used to limit the present application.

[0039] In the description of the present application, it should be understood that the terms "length", "width", "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0040] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified.

[0041] When the current TFT product designs a test line at the driving IC, the line design of the DS line is long and has many branches, as shown in Figure 1 , the long and branched line design is prone to static electricity. During the use of the mask (MASK), static electricity will continue to accumulate, and high static electricity lines will discharge to the surrounding low static electricity lines of the same layer, causing static shock. Static shock can change the line width and line spacing of the DS line.

[0042] If a slight static shock is caused, as shown in Figure 2a , Figure 2b , it may cause a short circuit of the DS line, affecting the stability of the product. Slight static shock may not cause a short circuit of the DS line, but it can still change the properties of the TFT transistor. Since no short circuit is caused, the product defect cannot be detected, resulting in a low product yield and rising costs.

[0043] Therefore, the present application provides a multi-conductive layer wiring structure, which arranges the main line and branches of the signal line on different conductive layers to improve the situation of static electricity between adjacent main lines and branches, thereby improving the negative effects of static electricity on the conductive layer and the signal line.

[0044] In order to illustrate the technical solutions of the present application, the specific drawings and examples will be described below.

[0045] Referring to Figure 3 , Figure 4 , the embodiment of the first aspect of the present application provides a multi-conductive layer wiring structure, comprising: a substrate 10, a conductive layer 20 and a signal line 30.

[0046] The substrate 10 is used to provide a fixed basis for the conductive layer 20, and is also used to obtain the required circuit pattern after hole processing, chemical copper plating, electroplating copper, etching and other processing technologies.

[0047] The conductive layer 20 is arranged on the substrate 10, and the conductive layer 20 comprises a first conductive layer 21 and a second conductive layer 22 arranged in a stack.

[0048] The signal line 30 is arranged between the first conductive layer 21 and the second conductive layer 22, and the signal line 30 comprises a plurality of main lines 31 and a plurality of branches 32, the plurality of main lines 31 and the plurality of branches 32 are electrically connected, the plurality of main lines 31 are arranged on the first conductive layer 21 in a spaced manner, and the plurality of branches 32 are arranged on the second conductive layer 22 in a spaced manner, that is, the main lines 31 and the branches 32 are not located on the same layer, so that the main lines 31 and the adjacent branches 32 are electrically isolated, thereby avoiding the generation of static electricity between the main lines 31 and the adjacent branches 32, and preventing static electricity from causing injury.

[0049] The embodiment has the beneficial effect that a wiring mode of the signal line 30 is provided, the main lines 31 and the branches 32 of the signal line 30 are arranged on the first conductive layer 21 and the second conductive layer 22 respectively, so that static electricity cannot be generated between the main lines 31 and the branches 32, thereby improving the situation that static electricity is generated between the adjacent main lines 31 and the branches 32, and further improving the negative influence of static electricity on the conductive layer 20 and the signal line 30.

[0050] In the embodiment, the signal line 30 is a DS signal line; in another embodiment, the signal line 30 can also be other metal wiring.

[0051] In the embodiment, the substrate 10 can be a glass substrate, or a metal substrate, a ceramic substrate, a polyimide film substrate, or other various substrates.

[0052] Reference Figure 3 , Figure 5 In an embodiment, the first conductive layer 21, the insulating layer 40, and the second conductive layer 22 are arranged in a stack on the substrate 10, and the second conductive layer 22 is a source-drain electrode layer.

[0053] Reference Figure 3 In the embodiment, the first conductive layer 21 is a gate electrode layer, and the insulating layer 40 is arranged between the first conductive layer 21 and the second conductive layer 22, and a plurality of vias 33 are arranged in the insulating layer 40, each of the branches 32 is connected to the main line 31 through a corresponding via 33; optionally, the signal line further comprises an extension line, the extension line and the main line 31 are located on the first conductive layer 21, and the extension line and each main line 31 are electrically connected, and the extension line is electrically connected to the branch 32 through the via 33, so as to realize the electrical connection between the main line 31 and the branch 32.

[0054] The arrangement of the insulating layer 40 can avoid the mutual influence between the first conductive layer 21 and the second conductive layer 22, and further avoid the generation of static electricity between the main line 31 and the branch 32, so as to further improve the situation that the conductive layer 20 and the signal line 30 are injured by static electricity.

[0055] Reference Figure 5 In another embodiment, the first conductive layer 21 is a pixel electrode layer, and an insulating layer 40 is arranged between the first conductive layer 21 and the second conductive layer 22, and a plurality of vias 33 are arranged in the insulating layer 40, and each branch 32 is connected to the main line 31 through a corresponding via 33.

[0056] The arrangement of the insulating layer 40 can avoid the mutual influence between the first conductive layer 21 and the second conductive layer 22, and can further avoid the static electricity generated between the main line 31 and the branch 32, so as to further improve the situation that the conductive layer 20 and the signal line 30 are damaged by static electricity.

[0057] The beneficial effect of the embodiment is that a plurality of first conductive layers 21 are provided, the mutual influence between the first conductive layer 21 and the second conductive layer 22 is reduced by arranging the insulating layer 40, and the static electricity generated between the main line 31 and the branch 32 is avoided, so as to improve the situation that the conductive layer 20 and the signal line 30 are damaged by static electricity.

[0058] Reference Figure 4 In an embodiment, the length of each branch 32 is the same, and all the branches 32 are located in the second conductive layer 22, so that the length difference of adjacent branches 32 in the second conductive layer 22 is reduced, the situation of static electricity generation is improved, and the negative influence of static electricity on the conductive layer 20 and the signal line 30 is further improved.

[0059] The length of each main line 31 is the same, and all the main lines 31 are located in the first conductive layer 21, so that the length difference of adjacent main lines 31 in the first conductive layer 21 is reduced, the situation of static electricity generation is improved, and the negative influence of static electricity on the conductive layer 20 and the signal line 30 is further improved.

[0060] In the embodiment, the length of the main line 31 is greater than the length of the branch 32.

[0061] In the embodiment, the distance between the projection of each main line 31 on the second conductive layer 22 and the adjacent two branches 32 is equal.

[0062] The beneficial effect of the multi-conductive layer wiring structure provided by the application is that:

[0063] 1. The main line 31 and the branch 32 of the signal line 30 are arranged in the first conductive layer 21 and the second conductive layer 22 respectively, so as to improve the situation of static electricity generated between adjacent main lines 31 and branches 32, thereby improving the negative influence of static electricity on the conductive layer 20 and the signal line 30;

[0064] 2. The main line 31 can be arranged in any conductive layer to adapt to different needs of different conductive layer structures;

[0065] 3. Signal line 30 can be used not only as a data signal line, but also as other metal traces to adapt to more wiring situations;

[0066] 4. Make all main lines 31 the same length and all branches 32 the same length, reducing the difference in line length between adjacent lines in the same layer, so as to improve the situation of static electricity generation, thereby further improving the negative impact of static electricity on conductive layer 20 and signal line 30.

[0067] The second aspect of this application also provides an array substrate, which includes the substrate (not shown) described in the first aspect and a multi-conductive layer wiring structure disposed on the substrate. The specific structure of the multi-conductive layer wiring structure is as described in the above embodiments. Since this array substrate adopts all the technical solutions of all the above embodiments, it will not be described in detail here.

[0068] Please refer to Figure 3 or Figure 5 The array substrate also includes thin-film transistors, which include a gate, a semiconductor layer, a source, and a drain. The array substrate also includes pixel electrodes electrically connected to the drain.

[0069] The beneficial effects of the array substrate provided in this application embodiment are as follows: by utilizing the multi-conductive layer structure, the main line 31 and the branch 32 are respectively disposed on the first conductive layer 21 and the second conductive layer 22, so as to improve the situation of electrostatic damage to the conductive layer and signal line, improve the product yield, improve the product stability, and extend the product service life.

[0070] This application also provides a display panel that includes the array substrate described in the second aspect. It will be understood that the display panel further includes a counter substrate disposed opposite to the array substrate.

[0071] The array substrate includes a multi-conductive layer trace structure. The specific structure of the multi-conductive layer trace structure is as described in the above embodiments. Since this display panel adopts all the technical solutions of all the above embodiments, it will not be described in detail here.

[0072] The beneficial effects of the display panel provided in this application embodiment are as follows:

[0073] An array substrate with a multi-conductive layer trace structure is configured, with the main line 31 and the branch line 32 respectively located on the first conductive layer 21 and the second conductive layer 22. This reduces or avoids electrostatic breakdown, improves the situation of electrostatic damage to conductive layers and signal lines, increases product yield, enhances product stability, and extends product lifespan.

[0074] The above examples are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

[0075] The above examples are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A multi-conductive-layer trace structure, characterized in that, include: substrate; A conductive layer is disposed on the substrate, and the conductive layer includes a first conductive layer and a second conductive layer stacked together. The signal line includes multiple main lines and multiple branches. The multiple main lines are disposed in the first conductive layer, and the multiple branches are disposed at intervals in the second conductive layer. The multiple main lines and the multiple branches are electrically connected. The main lines are of the same length, and the branches are of the same length, and the length of the main line is greater than the length of the branch; The projection of each main line onto the second conductive layer is equidistant from the distance between adjacent branches in the branch arrangement direction.

2. The multi-conductive layer trace structure according to claim 1, characterized in that, The second conductive layer is the source / drain electrode layer.

3. The multi-conductive layer trace structure according to claim 2, characterized in that, The first conductive layer is a gate electrode layer.

4. The multi-conductive layer trace structure according to claim 2, characterized in that, The first conductive layer is a pixel electrode layer.

5. The multi-conductive layer trace structure according to claim 3 or 4, characterized in that, An insulating layer is provided between the first conductive layer and the second conductive layer. The insulating layer has a plurality of vias, and each branch is connected to the main line through a corresponding via.

6. The multi-conductive layer trace structure according to claim 1, characterized in that, The substrate is one of a glass substrate, a metal substrate, or a ceramic substrate.

7. An array substrate, characterized in that, Includes the multi-conductive layer trace structure as described in any one of claims 1-6.

8. A display panel, characterized in that, Includes the array substrate as described in claim 7.

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