A self-biased split-gate bipolar transistor

Abstract

The application belongs to the technical field of power semiconductor devices, and relates to a self-bias split insulated gate bipolar transistor and a manufacturing method thereof. The application is characterized in that a diode is connected in series between a split polysilicon gate 11 and a floating P region 13, the diode cathode is connected with the split polysilicon gate 11, the diode anode is connected with the floating P region 13, a capacitor is connected in series between the split gate 11 and the emitter metal 1, and the floating P region 13 is clamped by an active region to obtain a higher potential at the time of IGBT turn-off. The potential makes the diode open, thereby charging the capacitor and making the capacitor obtain a stable potential. The split gate 11 is connected with the capacitor, so that the split gate also has a stable potential, the potential attracts the electrons near the split gate to accumulate to form an electron accumulation layer, the accumulation layer improves the injection efficiency of the channel, further improves the drift region conductance modulation effect, and reduces the forward conduction voltage drop of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a self-biased split gate bipolar transistor. BACKGROUND

[0002] The emergence of electric energy has promoted the rapid development of modern social science and technology, and how to more efficiently handle electric energy has always been a popular topic of scientific research all over the world. Efficient use of electric energy highly depends on power electronic systems, and the core electronic components of various power electronic systems are semiconductor power devices. Semiconductor power devices are widely used in various household appliances, various industrial equipment and other fields dominated by electric power. In the 21st century, global climate warming has attracted more and more attention, and energy saving and emission reduction and improvement of energy utilization efficiency are becoming increasingly important. Today, as the proportion of clean and renewable energy is increasing, society has higher expectations for energy conversion efficiency, and higher requirements are put forward for the performance of power semiconductor devices, which are the core of energy control.

[0003] Insulated gate bipolar transistors (IGBTs) are a new generation of power electronic devices because they combine the advantages of field effect transistors (MOSFETs) and bipolar junction transistors (BJTs). They have the advantages of MOSFETs, such as easy driving, low input impedance, and fast switching speed, and the advantages of BJTs, such as large on-state current density, low on-state voltage drop, small loss, and good stability. Therefore, they have developed into one of the core electronic components in modern power electronic circuits and are widely used in transportation, power grids, communications, household appliances, and aerospace fields. The use of IGBTs has greatly improved the performance of power electronic systems.

[0004] Since the invention of IGBT, people have been committed to improving the performance of IGBT. After more than 20 years of development, multiple generations of IGBT device structures have been proposed, and the performance of the devices has been steadily improved. Traditional trench IGBT (such as Figure 1 ) changes the gate from a horizontal planar MOS to a vertical trench MOS structure, which not only improves the power density and structural design space, but also eliminates the adverse effects of the JFET region and the latch-up effect caused by the parasitic NPN. Shielded gate trench IGBT (such as Figure 2 ) based on trench IGBT has lower gate capacitance, so it has faster switching speed and lower switching loss. Moreover, compared with the high peak electric field at the bottom of the traditional trench gate structure, the SGT structure has the advantage of optimizing the electric field to increase the withstand voltage, so the SGT-IGBT has greater application value in high-reliability high-performance application fields. Figure 2A cell structure of a conventional SGT-IGBT device is shown. As an insulated gate controlled structure, the gate of IGBT attracts electrons in the non-channel region through the gate voltage to form an electron accumulation layer while forming a channel, further reducing the forward conduction voltage drop. However, in the SGT-IGBT, since the shield gate is connected to the emitter, it cannot attract electrons to form an electron accumulation layer, and the channel electron injection efficiency is reduced, so the conductance modulation effect is weaker than that of the conventional trench IGBT, and the forward conduction voltage drop is increased. SUMMARY

[0005] In order to reduce the on-state voltage drop of the device and improve the performance of the device, the present application provides a self-biased split gate bipolar transistor. In the present application, a potential is introduced in the floating P region 13. When the IGBT is blocked, the capacitor is charged through the diode. When the IGBT is turned on, the voltage on the capacitor provides a self-biased potential for the SG (split gate), so that an electron accumulation is formed below the split gate structure, thereby enhancing the forward conduction capability of the IGBT device. At the same time, the split gate structure forms an internal field plate structure when it is blocked, which optimizes the peak electric field at the bottom of the trench and improves the forward voltage resistance capability of the IGBT. Moreover, the existence of the split gate structure weakens the capacitive effect between the gate and the collector, accelerates the switching speed of the IGBT, reduces the switching loss of the device, and further optimizes the characteristics of the device.

[0006] To solve the above technical problems, the present application provides a self-biased split gate bipolar transistor, which has a cell structure comprising: a collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top;

[0007] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are in contact with each other on the side of the top layer of the P-type base region 4, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2;

[0008] The trench emitter structure comprises a trench emitter 12 and a trench oxide layer 6 on the side and bottom of the trench emitter; the split gate structure comprises a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 is on the split polysilicon gate 11, and there is a trench oxide layer 6 between the split polysilicon gate 11 and the polysilicon gate 5, and there is a trench oxide layer 6 between the split polysilicon gate 11 and the polysilicon gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3;

[0009] A split diode is connected in series between the split polysilicon gate 11 and the floating P region 13, the N-type region of the diode is connected with the split polysilicon gate 11, the P-type region of the diode is connected with the floating P region 13, and a capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0010] To solve the above technical problems, the embodiment of the present application provides a self-biased split insulated gate bipolar transistor, which comprises a cell structure including a collector metal 10, a P-type collector region 9, an N-type electric field blocking layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type electric field blocking layer 8 and the N-drift region 7 are sequentially stacked from bottom to top.

[0011] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are located on the top layer of the P-type base region 4 and contact each other on the side, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P region 13 has a Schottky contact diode metal layer 14 on the side away from the trench emitter structure; the Schottky contact diode metal layer 14 is connected with the split polysilicon gate 11.

[0012] The trench emitter structure comprises a trench emitter 12 and a trench oxide layer 6 on the side and bottom of the trench emitter; the split gate structure comprises a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 is on the split polysilicon gate 11, and there is a trench oxide layer 6 between the split polysilicon gate 11 and the polysilicon gate 5, and there is a trench oxide layer 6 between the split polysilicon gate 11 and the polysilicon gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3; a capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0013] To solve the above technical problems, the embodiment of the present application provides a self-biased split gate bipolar transistor, which has a cell structure comprising: a collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top;

[0014] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are located on the top layer of the P-type base region 4 and contact each other, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P region 13 has an N-type region 15 with a PN junction on the top layer of the side away from the trench emitter structure, and the N-type region 15 with the PN junction has an ohmic contact metal layer 16 with a PN junction on it;

[0015] The trench emitter structure comprises a trench emitter 12 and a trench oxide layer 6 located on the side and bottom of the trench emitter 12; the split gate structure comprises a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 is located on the split polysilicon gate 11, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3; the split polysilicon gate 11 is connected with the ohmic contact metal layer 16 with the PN junction; an external capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0016] To solve the above technical problems, the embodiment of the present application provides a self-biased split gate bipolar transistor, which has a cell structure comprising: a collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top;

[0017] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are located on the top layer of the P-type base region 4 and are in contact with each other, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P region 13 has a P+ region 17 on the top layer of the side away from the trench emitter structure, and the P+ region 17 has a metal layer 18 thereon; the floating P region 13 between the trench emitter structure and the P+ region 17 has a field oxide layer 19 of a polysilicon diode structure, and the field oxide layer 19 has a P-type region 20 of a polysilicon diode and an N-type region 21 of a polysilicon diode which are in contact with each other on the side, and the side of the P-type region 20 of the polysilicon diode is in contact with the side of the metal layer 18;

[0018] The trench emitter structure comprises a trench emitter 12 and a trench oxide layer 6 located on the side and bottom of the trench emitter 12; the split gate structure comprises a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 is located on the split polysilicon gate 11, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3; the split polysilicon gate 11 is connected with the N-type region 21; an external capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0019] On the basis of the above technical solution, the application can be further improved as follows.

[0020] Further, the P-type base region 4 has an N-type carrier storage layer 22 below.

[0021] Further, the N-type carrier storage layer 22, the trench emitter structure and the floating P region 13 have a P-type region 23 below, and the split gate structure and the P-type region 23 have the N-drift region 7 therebetween.

[0022] Further, the trench emitter structure further has a split emitter 12-1, the split emitter 12-1 is located below the trench emitter 12, and the split emitter 12-1 and the trench emitter 12 have the trench oxide layer 6 therebetween.

[0023] Further, the N-type electric field stopping layer 8 is formed by a multi-step hydrogen implantation process.

[0024] Further, a super junction structure is introduced in the N-drift region 7, the super junction structure includes P columns 24 and N columns 25, the P columns 24 and the N columns 25 are located in the N-drift region 7 and side faces contact each other, the P columns 24 are connected with the floating P region 13, the N columns 25 are above the P base region 4, and the contact surface of the P columns 24 and the N columns 25 is below the trench emitter structure.

[0025] Further, the P-type collector region 9 has an N region 26 on one side.

[0026] Further, the materials used in the device structure include silicon, silicon carbide, gallium nitride, gallium oxide or diamond, etc., and the Schottky contact diode metal layer 14 is made of titanium, nickel, copper or aluminum.

[0027] To solve the above technical problems, the embodiment of the present application provides a manufacturing method of the self-biased split gate bipolar transistor, which comprises the following steps:

[0028] Step 1: selecting an N-type lightly doped FZ silicon wafer as the N-drift region 7 of the device;

[0029] Step 2: growing a field oxide layer 27 on the surface of the silicon wafer, using a photolithography process, and forming the floating P region 13 of the device by high-temperature ion implantation of P-type impurities and annealing in the N-drift region 7, and growing a pre-oxidation layer 28 on the surface of the silicon wafer;

[0030] Step 3: using a photolithography process to form a first trench and a second trench, and forming a trench oxide layer 6 on the side walls and bottom of the first trench and the second trench by a thermal oxidation process;

[0031] Step 4: depositing N-doped polysilicon in the first trench and the second trench, forming a polysilicon trench gate 29 in the first trench, and forming a trench emitter 12 in the second trench;

[0032] Step 5: forming an oxide shielding layer by a thermal oxidation process, etching away the oxide layer on the surface of the polysilicon trench gate 29 and the polysilicon on the upper layer of the polysilicon trench gate 29 by a photolithography process, forming a split polysilicon gate 11, and forming a polysilicon gate 5 by performing thermal oxidation on the surface of the split polysilicon gate 11 to form an oxide isolation layer and then depositing again;

[0033] Step 6: using a photolithography process and forming the P base region 4 of the device by high-temperature ion implantation of P-type impurities and annealing;

[0034] Step 7: manufacturing the N+ emitter region 3 of the device by high-temperature ion implantation of N-type impurities and annealing;

[0035] Step 8: manufacturing the emitter ohmic contact P+ region 2 of the device by high-temperature ion implantation of P-type impurities and annealing.

[0036] Step 9: Al metal deposition to form emitter metal 1;

[0037] Step 10: Schottky metal deposition to form Schottky contact diode metal layer 14;

[0038] Step 11: Turn over the silicon wafer, thin the silicon wafer, implant N-type impurities by high-energy ion implantation on the back of the silicon wafer, implant P-type impurities by ion implantation and anneal to form N-type field stop layer 8 and P-type collector region 9 on the surface thereof;

[0039] Step 12: Deposit metal on the back of the silicon wafer to form collector metal 10 on the surface of P-type collector region 9.

[0040] The working principle of the present application is that when the polysilicon gate 5 is connected to a high potential higher than the threshold voltage of the device, the collector metal 10 is connected to a high potential, and the emitter metal 1 is connected to a low potential, the device works in the on state, the P-type collector region 9 injects holes into the N-drift region 7, and the N+ emitter region 3 injects electrons into the N-drift region 7, the existence of electron-hole pairs causes the occurrence of conductance modulation effect in the drift region.

[0041] When an external diode is connected in series between the split polysilicon gate 11 and the floating P region 13, the N-type region of the diode is connected to the split polysilicon gate 11, the P-type region of the diode is connected to the floating P region 13, and an external capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1, the floating P region 13 obtains a relatively stable potential through active region clamping, which makes the external diode open and charges the external capacitor. Since the split polysilicon gate 11 is connected to the capacitor, the N region of the diode maintains a stable value, and since the diode N region is connected to the split gate 11, the split gate also has a stable potential, which attracts electrons near the split gate to accumulate and form an electron accumulation layer, which improves the injection efficiency of the channel and further enhances the conductance modulation effect of the drift region, thereby reducing the forward on-state voltage drop of the device.

[0042] When the floating P region 13 forms a Schottky diode with the metal layer 14, the potential below the floating P region 13 is clamped by the reverse-biased PN junction composed of the P-type base region 4 and the N-drift region 7, which charges the integrated capacitor through the Schottky diode. Since the diode can maintain the charge on the capacitor and the floating P region 13 has a relatively stable clamping voltage, the metal layer 14 of the Schottky diode maintains a stable value, and since the metal layer 14 of the Schottky diode is connected to the split gate 11, the split gate 11 also has a stable potential, which attracts electrons near the split gate 11 to accumulate and form an electron accumulation layer, which improves the injection efficiency of the channel and further enhances the conductance modulation effect of the drift region, thereby reducing the forward on-state voltage drop of the device.

[0043] The beneficial effects of the present application are:

[0044] The present application utilizes the potential of the floating P region 13 to provide a bias potential for the split polysilicon gate 11, thereby forming an electron accumulation capability under the trench, enhancing the conductance modulation effect, and thus enhancing the forward conduction capability of the device. Compared with the conventional split gate structure, the introduction of the self-bias structure is beneficial to simultaneously improving the conduction capability and switching performance of the device, eliminating the negative effects brought by the split gate, improving the switching loss and switching speed, and also optimizing the forward conduction capability of the device, improving the compromise characteristics between the forward conduction voltage drop and the off-state loss of the device.

[0045] The gate oxide layer 6 around the split polysilicon gate 11 is not limited by the threshold voltage design, so its thickness can be further increased to improve the voltage resistance and oxide layer reliability of the device, and improve the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 A schematic diagram of a cell structure of a conventional trench gate IGBT;

[0047] Figure 2 A schematic diagram of a cell structure of a conventional shield gate trench IGBT;

[0048] Figure 3 A schematic diagram of a cell structure of a self-bias split gate bipolar transistor according to the first embodiment of the present application;

[0049] Figure 4 A schematic diagram of a cell structure of a self-bias split gate bipolar transistor according to the second embodiment of the present application;

[0050] Figure 5 An equivalent circuit diagram of a self-bias split gate bipolar transistor according to the second embodiment of the present application;

[0051] Figure 6 A schematic diagram of a cell structure of a self-bias split gate bipolar transistor according to the third embodiment of the present application;

[0052] Figure 7 A schematic diagram of a cell structure of a self-bias split gate bipolar transistor according to the fourth embodiment of the present application;

[0053] Figure 8 A schematic diagram of a cell structure of a self-bias split gate bipolar transistor according to the fifth embodiment of the present application;

[0054] Figure 9 A schematic diagram of a cell structure of a self-bias split gate bipolar transistor according to the sixth embodiment of the present application;

[0055] Figure 10 A schematic diagram of a cell structure of a self-biased split-gate bipolar transistor according to an eighth embodiment of the present application;

[0056] Figure 11 A schematic diagram of a cell structure of a self-biased split-gate bipolar transistor according to an eighth embodiment of the present application;

[0057] Figure 12 A schematic diagram of a cell structure of a self-biased split-gate bipolar transistor according to an eighth embodiment of the present application;

[0058] Figure 13 A schematic diagram of a cell structure of a self-biased split-gate bipolar transistor according to an eighth embodiment of the present application;

[0059] Figures 14-26 A schematic diagram of a cell structure of a self-biased split-gate bipolar transistor according to an eighth embodiment of the present application;

[0060] In the drawings, the components represented by the reference numerals are listed as follows:

[0061] 1, emitter metal, 2, emitter ohmic contact P+ region, 3, N+ emitter region, 4, P-type base region, 5, polysilicon gate, 6, trench oxide layer, 7, N- drift region, 8, N-type field stop layer, 9, P-type collector region, 10, collector metal, 11, split polysilicon gate, 12, trench emitter, 13, floating P region, 14, Schottky contact diode metal layer, 15, N-type region of PN junction 15, 16, ohmic contact metal layer of PN junction, 17, P+ region, 18, metal layer, 19, field oxide layer of polysilicon diode structure, 20, P-type region of polysilicon diode, 21, N-type region of polysilicon diode, 22, N-type carrier storage layer, 23, P-type region, 24, P column, 25, N column, 26, N region, 27, field oxide layer, 28, pre-oxidation layer, 29, polysilicon trench gate. DETAILED DESCRIPTION

[0062] The principles and features of the present application are described below in conjunction with the accompanying drawings, which are provided only for explanation of the present application and are not intended to limit the scope of the present application.

[0063] As Figure 3As shown, the first embodiment of the present application provides a self-biased split IGBT, which has a cell structure including: a collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top;

[0064] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are located on the top layer of the P-type base region 4 and contact each other, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2.

[0065] The trench emitter structure includes a trench emitter 12 and a trench oxide layer 6 located on the side and bottom of the trench emitter 12; the split gate structure includes a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 is located on the split polysilicon gate 11, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3.

[0066] A diode is connected in series between the split polysilicon gate 11 and the floating P region 13, the N-type region of the diode is connected with the split polysilicon gate 11, the P-type region of the diode is connected with the floating P region 13, and a capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0067] In the embodiment, the doping concentration of the P-type base region 4 is 3×10 16 cm -3 ~2×10 17 cm -3 , and the depth is 3-3.5 μm; the doping concentration of the N+ emitter region 3 is 5×10 18 cm -3 ~1×10 21 cm -3 , and the depth is 0.2-0.5 μm; the thickness of the gate dielectric layer 6 is 80-120 nm; the depth of the trench gate electrode 5 is 4-6 μm; the depth of the split gate electrode 11 is 0.5-2 μm; the depth of the trench emitter 12 is 5-8 μm; and the doping concentration of the N-drift region 7 is 5×1012 cm -3 ~2×10 14 cm -3 The thickness is 60–700 μm; the doping concentration of the N-type electric field blocking layer 8 is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness is 5–20 μm; the doping concentration of the P-type collector region 9 is 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The thickness is 0.5–5 μm; the cell width is 20–40 μm.

[0068] like Figures 4-5 As shown, the second embodiment of the present invention provides a self-biased split-gate bipolar transistor, the cell structure of which includes: collector metal 10, P-type collector region 9, N-type electric field blocking layer 8, N-drift region 7, P-type base region 4, N+ emitter region 3, emitter ohmic contact P+ region 2, floating P region 13, trench emitter structure, split gate structure and emitter metal 1; collector metal 10, P-type collector region 9, N-type electric field blocking layer 8 and N-drift region 7 are stacked sequentially from bottom to top;

[0069] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P-region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P-region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are in side contact with each other and are located on the top layer of the P-type base region 4, the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P-region 13 has a Schottky contact diode metal layer 14 on the side away from the trench emitter structure; the Schottky contact diode metal layer 14 is connected to the split polysilicon gate 11;

[0070] The trench emitter structure includes a trench emitter 12 and trench oxide layers 6 located on its sides and bottom; the split gate structure includes a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 being located on the split polysilicon gate 11, and a trench oxide layer 6 being present between the split polysilicon gate 11 and the polysilicon gate 5, and a trench oxide layer 6 being present between the split polysilicon gate 11 and the polysilicon gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3; an external capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0071] In the above embodiment, the floating P region 13 and the metal layer 14 form a Schottky diode, and the potential of the floating P region 13 is taken as the capacitor charging, so as to improve the capacitor voltage and realize the self-bias of the split gate. Thus, the structure can improve the forward conduction characteristic on the basis of the traditional split gate structure, and is compatible with the control circuit of the traditional IGBT.

[0072] As shown in Figure 6 The third embodiment of the present application provides a self-biased split gate bipolar transistor, and the cell structure thereof comprises a collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top.

[0073] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are located on the top layer of the P-type base region 4 and are in contact with each other, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P region 13 has an N-type region 15 with a PN junction on the top layer of the side away from the trench emitter structure, and the N-type region 15 with the PN junction has an ohmic contact metal layer 16 with a PN junction on the N-type region 15 with the PN junction;

[0074] The trench emitter structure comprises a trench emitter 12 and a trench oxide layer 6 located on the side and bottom of the trench emitter 12; the split gate structure comprises a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 is located on the split polysilicon gate 11, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3; the split polysilicon gate 11 is connected with the ohmic contact metal layer 16 with the PN junction; an external capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0075] In the above embodiment, the N-type region 15 is introduced inside the floating P region 13 to form a PN junction clamped diode, and an ohmic contact 16 is made above the N-type region 15, and the ohmic contact is connected with the split gate 11. The integration of the PN junction inside the IGBT is realized, and compared with the Schottky diode, the leakage current is smaller, the capacitor potential is kept more stable, and thus the electron accumulation effect of the split gate 11 is maintained relatively stable.

[0076] As shown in Figure 7 The fourth embodiment of the present application provides a self-biased split gate bipolar transistor, and the cell structure thereof comprises: a collector metal 10, a P-type collector region 9, an N-type electric field stopping layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a trench emitter structure, a split gate structure, and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type electric field stopping layer 8, and the N-drift region 7 are sequentially stacked from bottom to top;

[0077] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 side-by-side contact each other on the top layer of the P-type base region 4, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P region 13 has a P+ region 17 in the top layer of the side away from the trench emitter structure, and the P+ region 17 has a metal layer 18 thereon; the floating P region 13 between the trench emitter structure and the P+ region 17 has a field oxide layer 19 of a polysilicon diode structure thereon, the field oxide layer 19 has a P-type region 20 of a polysilicon diode and an N-type region 21 of a polysilicon diode side-by-side contact each other thereon, and the side of the P-type region 20 of the polysilicon diode contacts the side of the metal layer 18;

[0078] The trench emitter structure comprises a trench emitter 12 and a trench oxide layer 6 on the side and bottom of the trench emitter 12; the split gate structure comprises a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 is located on the split polysilicon gate 11, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween, and the split polysilicon gate 11 and the polysilicon gate 5 have the trench oxide layer 6 therebetween and the N-drift region 7, the P-type base region 4, and the N+ emitter region 3; the split polysilicon gate 11 is connected with the N-type region 21; an external capacitor is connected in series between the split polysilicon gate 11 and the emitter metal 1.

[0079] In the above embodiment, the P+ region 17 is formed above the P-type floating region 13, the P-type region 17 is connected with the polysilicon diode 20, 21 through the metal layer 18, and the N-type region 21 of the polysilicon diode is connected with the split gate 11. Compared with the Schottky diode structure, the polysilicon diode structure is integrated on the surface, and it is easier to set the size and the dopant amount, so it has higher design flexibility and process adjustability.

[0080] As shown in Figure 8 the fifth embodiment of the present application provides a self-biased split gate bipolar transistor, which is based on the second embodiment, and the P-type base region 4 is provided with an N-type carrier storage layer 22 below.

[0081] The above embodiment can block the holes from the drift region 7 to be extracted by the P-type base region 4, increase the carrier concentration in the drift region 7, and enhance the conductance modulation effect.

[0082] As shown in Figure 9 the sixth embodiment of the present application provides a self-biased split gate bipolar transistor, which is based on the fifth embodiment, and the N-type carrier storage layer 22, the trench emitter structure and the floating P region 13 are provided with a P-type region 23 below, and the split gate structure and the P-type region 23 are provided with an N-type drift region 7.

[0083] The above embodiment can shield the influence of the N-type carrier storage layer 22 on the structure voltage resistance, and at the same time, cooperate with the trench emitter 12 to provide an extraction path for the holes in the drift region 7 at the off state, so as to accelerate the off speed.

[0084] As shown in Figure 10 the seventh embodiment of the present application provides a self-biased split gate bipolar transistor, which is based on the second embodiment, and the trench emitter structure is further provided with a split emitter 12-1, the split emitter 12-1 is located below the trench emitter 12, and the split emitter 12-1 and the trench emitter 12 are provided with a trench oxide layer 6.

[0085] In the above embodiment, the thickness of the emitter 12-1 at the bottom of the trench is consistent with the thickness of the split gate electrode 11, which is 0.5-2 μm, and the thickness of the emitter 12 at the top is consistent with the thickness of the trench gate electrode 5, which is 4-6 μm.

[0086] In the embodiment, the emitter trench and the gate trench are symmetrical, and can be realized through a unified process step.

[0087] As shown in Figure 11 the eighth embodiment of the present application provides a self-biased split gate bipolar transistor, which is based on the second embodiment, and the N-type field stop layer 8 is formed by a multi-step hydrogen implantation process.

[0088] In the above embodiments, a gradually changing field cutoff layer can be achieved by four different doses and different injection energies, or by N-type silicon epitaxy, or by co-implantation of phosphorus and hydrogen.

[0089] By introducing a thick FS layer 8 for hydrogen implantation between the N-drift region and the P+ collector region, the hydrogen implantation process is well-suited to replace the high-temperature pre-diffusion process for deep implantation of IGBTs due to its advantages of large implantation depth at lower energies and low annealing temperatures. The number of high-energy H implantations on the back side is set to four, each using 1×102... 12 cm -3 -1×10 15 cm -3 Selection of injection dose within the range and injection energy from 20 to 200 keV.

[0090] Compared with Example 1, the N-drift region formed by the hydrogen-injected field stop layer and the NN-junction of the N+FS layer have a gentler concentration gradient, which can effectively increase the dynamic avalanche tolerance of the device.

[0091] like Figure 12 As shown, the ninth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor, which is based on the second embodiment, by introducing a superjunction structure in the N-drift region 7. The superjunction structure includes P-pillar 24 and N-pillar 25. The P-pillar 24 and N-pillar 25 are located in the N-drift region 7 with their sides in contact with each other. The P-pillar 24 is connected to the floating P-region 13. The P-type base region 4 is above the N-pillar 25. The contact surface of the P-pillar 24 and N-pillar 25 is located below the trench emitter structure.

[0092] In the above embodiment, the N-drift region 7 is replaced with a superjunction structure of N / P pillars with a higher concentration. The N pillar 25 serves as the substrate, and the P pillar 24 is achieved through trench filling or multiple epitaxial growth followed by ion implantation, with similar concentrations. The doping concentration is set to 1×10⁻⁶. 14 cm -3 -5×10 16 cm -3 The column width is 2μm-12μm, and the thickness of the drift region is reduced by 20-30% according to the pressure resistance requirements.

[0093] Compared with Example 1, the introduction of the superjunction structure is beneficial to improving the device's breakdown voltage and trade-off performance. At the same time, the laterally depleted drift pillar region assists in the longitudinal depletion layer expansion during device switching, further improving the device's switching speed.

[0094] like Figure 13 As shown, the tenth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor, which is based on the second embodiment, by having an N region 26 in one side of the P-type collector region 9.

[0095] The above embodiment introduces a portion of the N-region 26 into the collector region P-region 9 to realize an RC-IGBT structure, thereby integrating the diodes within the IGBT module into the IGBT structure. The N-region 26 is achieved through back-side implantation with a doping concentration of 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 .

[0096] Compared to Example 1, the introduction of the N-region collector integrates the diodes within the IGBT module into the IGBT structure, thereby improving the module integration.

[0097] Optionally, the Schottky contact diode metal layer 14 is made of titanium, nickel, copper or aluminum.

[0098] The eleventh embodiment of the present invention provides a method for fabricating the above-described self-biased split insulated gate bipolar transistor, comprising the following steps:

[0099] Step 1: Select an N-type lightly doped FZ silicon wafer as the N-drift region 7 of the device, such as... Figure 14 As shown;

[0100] Step 2: A field oxide layer 27 is grown on the silicon wafer surface using photolithography. Following high-temperature ion implantation of P-type impurities in the N-drift region 7 and annealing, a floating P-region 13 of the device is formed. Figure 15 As shown, a pre-oxidized layer 28 is grown on the surface of the silicon wafer;

[0101] Step 3: Using photolithography, form the first and second trenches, such as... Figure 16 As shown, a trench oxide layer 6 is formed on the sidewalls and bottom of the first and second trenches through a thermal oxidation process.

[0102] Step 4: N-doped polysilicon is deposited in the first and second trenches. A polysilicon trench gate 29 is formed in the first trench, and a trench emitter 12 is formed in the second trench. Figure 17 As shown;

[0103] Step 5: An oxide shielding layer is formed using a thermal oxidation process. The oxide layer on the surface of the polysilicon trench gate 29 and the polysilicon layer on top of the polysilicon trench gate 29 are etched away using a photolithography process to form a split polysilicon gate 11. An oxide isolation layer is then formed on the surface of the split polysilicon gate 11 through thermal oxidation and further deposition to form the polysilicon gate 5. Figures 18-19 As shown;

[0104] Step 6: Using photolithography, and after high-temperature ion implantation of P-type impurities followed by annealing, the P-type base region 4 of the device is formed, as shown below. Figure 20 As shown;

[0105] Step 7: Fabricate N+ emitter region 3 of the device by high temperature ion implantation of N-type impurities and annealing, as shown in Figure 21 ;

[0106] Step 8: Fabricate emitter ohmic contact P+ region 2 of the device by high temperature ion implantation of P-type impurities and annealing, as shown in Figure 22 ;

[0107] Step 9: Perform Al metal deposition to form emitter metal 1, as shown in Figure 23 ;

[0108] Step 10: Perform Schottky metal deposition to form Schottky contact diode metal layer 14, as shown in Figure 24 ;

[0109] Step 11: Turn over the silicon wafer, thin the silicon wafer, and form N-type field stop layer 8 and P-type collector region 9 on the back surface of the silicon wafer by high energy ion implantation of N-type impurities and ion implantation of P-type impurities and annealing, as shown in Figure 25 ;

[0110] Step 12: Deposit metal on the back surface of the silicon wafer to form collector metal 10 on the surface of P-type collector region 9, as shown in Figure 26 .

[0111] The present application obtains a higher potential on the back surface of the silicon wafer at the time of IGBT turn-off by series connection of a diode between split polysilicon gate 11 and floating P region 13, connection of the cathode of the diode to split polysilicon gate 11, connection of the anode of the diode to floating P region 13, series connection of a capacitor between split gate 11 and emitter metal 1, and clamping of floating P region 13 by the active region, and the potential makes the diode open, thereby charging the capacitor and making the capacitor obtain a stable potential. Split gate 11 is connected to the capacitor, so that split gate also has a stable potential, which attracts electrons near the split gate to accumulate and form an electron accumulation layer, which improves the injection efficiency of the channel and further improves the drift region conductance modulation effect, thereby reducing the forward on-state voltage drop of the device.

[0112] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0113] In addition, the terms "first", "second", etc. are used only for the purpose of description and do not imply or imply relative importance or imply the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified.

[0114] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0115] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature. The first and second features can be in direct contact, or the first and second features can be indirectly contacted through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be the first feature directly above or obliquely above the second feature, or only indicate that the first feature is higher than the second feature in horizontal height. The first feature "below", "below" and "below" the second feature can be the first feature directly below or obliquely below the second feature, or only indicate that the first feature is lower than the second feature in horizontal height.

[0116] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or features of different embodiments or examples described in the present application without contradiction.

[0117] The above is only the preferred embodiment of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A self-biased split-gate insulated-gate bipolar transistor, characterized in that, Its cellular structure includes: collector metal (10), P-type collector region (9), N-type electric field blocking layer (8), N-drift region (7), P-type base region (4), N+ emitter region (3), emitter ohmic contact P+ region (2), floating P region (13), trench emitter structure, split gate structure and emitter metal (1); collector metal (10), P-type collector region (9), N-type electric field blocking layer (8) and N-drift region (7) are stacked sequentially from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7), the floating P region (13) is located on the other side of the top layer of the N-drift region (7), the trench emitter structure is located on the top layer of the N-drift region (7) between the split gate structure and the floating P region (13), the P-type base region (4) is located on the top layer of the N-drift region (7) between the trench emitter structure and the split gate structure, the N+ emitter region (3) and the emitter ohmic contact P+ region (2) are in contact with each other on the top layer of the P-type base region (4), and the emitter metal (1) is located on the N+ emitter region (3) and the emitter ohmic contact P+ region (2); The trench emitter structure includes a trench emitter (12) and trench oxide layers (6) located on its sides and bottom; the split gate structure includes a split polysilicon gate (11) and a polysilicon gate (5), the polysilicon gate (5) being located on the split polysilicon gate (11), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5) and the N-drift region (7), the P-type base region (4) and the N+ emitter region (3); An external diode is connected in series between the split polysilicon gate (11) and the floating P region (13). The N-type region of the diode is connected to the split polysilicon gate (11), and the P-type region of the diode is connected to the floating P region (13). An external capacitor is connected in series between the split polysilicon gate (11) and the emitter metal (1).

2. The self-biased split-gate bipolar transistor according to claim 1, characterized in that, Below the P-type base region (4) is an N-type carrier storage layer (22).

3. A self-biased split-gate bipolar transistor according to claim 2, characterized in that, The N-type carrier storage layer (22), the trench emitter structure and the floating P-region (13) have a P-type region (23) below them, and the split gate structure has an N-drift region (7) between it and the P-type region (23).

4. A self-biased split-gate bipolar transistor according to claim 1, characterized in that, The trench emitter structure also has a split emitter (12-1), which is located below the trench emitter (12), and a trench oxide layer (6) is present between the split emitter (12-1) and the trench emitter (12).

5. A self-biased split-gate bipolar transistor according to claim 1, characterized in that, The N-type electric field blocking layer 8 is formed using a multi-step hydrogen implantation process.

6. A self-biased split-gate bipolar transistor according to claim 1, characterized in that, A superjunction structure is introduced in the N-drift region (7). The superjunction structure includes a P-pillar (24) and an N-pillar (25). The P-pillar (24) and the N-pillar (25) are located in the N-drift region (7) with their sides in contact with each other. The P-pillar (24) is connected to the floating P-region (13). The P-type base region 4 is above the N-pillar (25). The contact surface of the P-pillar (24) and the N-pillar (25) is located below the trench emitter structure.

7. A self-biased split-gate bipolar transistor according to claim 1, characterized in that, The P-type collector region (9) has an N-region (26) on one side.

8. A self-biased split-gate insulated-gate bipolar transistor, characterized in that, Its cell structure includes: collector metal (10), P-type collector region (9), N-type electric field blocking layer (8), N-drift region (7), P-type base region (4), N+ emitter region (3), emitter ohmic contact P+ region (2), floating P region (13), trench emitter structure, split gate structure, emitter metal (1) and Schottky contact diode metal layer (14); collector metal (10), P-type collector region (9), N-type electric field blocking layer (8) and N-drift region (7) are stacked sequentially from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7), the floating P region (13) is located on the other side of the top layer of the N-drift region (7), the trench emitter structure is located on the top layer of the N-drift region (7) between the split gate structure and the floating P region (13), the P-type base region (4) is located on the top layer of the N-drift region (7) between the trench emitter structure and the split gate structure, the N+ emitter region (3) and the emitter ohmic contact P+ region (2) are in contact with each other on the top layer of the P-type base region (4), the emitter metal (1) is located on the N+ emitter region (3) and the emitter ohmic contact P+ region (2); the floating P region (13) has a Schottky contact diode metal layer (14) on the side away from the trench emitter structure; the Schottky contact diode metal layer (14) is connected to the split polysilicon gate (11); The trench emitter structure includes a trench emitter (12) and trench oxide layers (6) located on its sides and bottom; the split gate structure includes a split polysilicon gate (11) and a polysilicon gate (5), the polysilicon gate (5) being located on the split polysilicon gate (11), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5) and the N-drift region (7), the P-type base region (4) and the N+ emitter region (3); an external capacitor is connected in series between the split polysilicon gate (11) and the emitter metal (1).

9. A self-biased split-gate bipolar transistor according to claim 8, characterized in that, Below the P-type base region (4) is an N-type carrier storage layer (22).

10. A self-biased split-gate bipolar transistor according to claim 9, characterized in that, The N-type carrier storage layer (22), the trench emitter structure and the floating P-region (13) have a P-type region (23) below them, and the split gate structure has an N-drift region (7) between it and the P-type region (23).

11. A self-biased split-gate bipolar transistor according to claim 8, characterized in that, The trench emitter structure also has a split emitter (12-1), which is located below the trench emitter (12), and a trench oxide layer (6) is present between the split emitter (12-1) and the trench emitter (12).

12. A self-biased split-gate bipolar transistor according to claim 8, characterized in that, The N-type electric field blocking layer 8 is formed using a multi-step hydrogen implantation process.

13. A self-biased split-gate bipolar transistor according to claim 8, characterized in that, A superjunction structure is introduced in the N-drift region (7). The superjunction structure includes a P-pillar (24) and an N-pillar (25). The P-pillar (24) and the N-pillar (25) are located in the N-drift region (7) with their sides in contact with each other. The P-pillar (24) is connected to the floating P-region (13). The P-type base region 4 is above the N-pillar (25). The contact surface of the P-pillar (24) and the N-pillar (25) is located below the trench emitter structure.

14. A self-biased split-gate bipolar transistor according to claim 8, characterized in that, The P-type collector region (9) has an N-region (26) on one side.

15. A self-biased split-gate insulated-gate bipolar transistor, characterized in that, Its cellular structure includes: collector metal (10), P-type collector region (9), N-type electric field blocking layer (8), N-drift region (7), P-type base region (4), N+ emitter region (3), emitter ohmic contact P+ region (2), floating P region (13), trench emitter structure, split gate structure and emitter metal (1); collector metal (10), P-type collector region (9), N-type electric field blocking layer (8) and N-drift region (7) are stacked sequentially from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7), the floating P region (13) is located on the other side of the top layer of the N-drift region (7), the trench emitter structure is located on the top layer of the N-drift region (7) between the split gate structure and the floating P region (13), the P-type base region (4) is located on the top layer of the N-drift region (7) between the trench emitter structure and the split gate structure, the N+ emitter region (3) and the emitter ohmic contact P+ region (2) are in contact with each other on the top layer of the P-type base region (4), the emitter metal (1) is located on the N+ emitter region (3) and the emitter ohmic contact P+ region (2); the floating P region (13) has an N-type region (15) of a PN junction in the top layer on the side away from the trench emitter structure, and the N-type region (15) of the PN junction has an ohmic contact metal layer (16) of a PN junction. The trench emitter structure includes a trench emitter (12) and trench oxide layers (6) located on its sides and bottom; the split gate structure includes a split polysilicon gate (11) and a polysilicon gate (5), the polysilicon gate (5) being located on the split polysilicon gate (11), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5) and the N-drift region (7), the P-type base region (4) and the N+ emitter region (3); the split polysilicon gate (11) is connected to the ohmic contact metal layer (16) of the PN junction; an external capacitor is connected in series between the split polysilicon gate (11) and the emitter metal (1).

16. A self-biased split-gate bipolar transistor according to claim 15, characterized in that, Below the P-type base region (4) is an N-type carrier storage layer (22).

17. A self-biased split-gate bipolar transistor according to claim 16, characterized in that, The N-type carrier storage layer (22), the trench emitter structure and the floating P-region (13) have a P-type region (23) below them, and the split gate structure has an N-drift region (7) between it and the P-type region (23).

18. A self-biased split-gate bipolar transistor according to claim 15, characterized in that, The trench emitter structure also has a split emitter (12-1), which is located below the trench emitter (12), and a trench oxide layer (6) is present between the split emitter (12-1) and the trench emitter (12).

19. A self-biased split-gate bipolar transistor according to claim 15, characterized in that, The N-type electric field blocking layer 8 is formed using a multi-step hydrogen implantation process.

20. A self-biased split-gate bipolar transistor according to claim 15, characterized in that, A superjunction structure is introduced in the N-drift region (7). The superjunction structure includes a P-pillar (24) and an N-pillar (25). The P-pillar (24) and the N-pillar (25) are located in the N-drift region (7) with their sides in contact with each other. The P-pillar (24) is connected to the floating P-region (13). The P-type base region 4 is above the N-pillar (25). The contact surface of the P-pillar (24) and the N-pillar (25) is located below the trench emitter structure.

21. A self-biased split-gate bipolar transistor according to claim 15, characterized in that, The P-type collector region (9) has an N-region (26) on one side.

22. A self-biased split-gate insulated-gate bipolar transistor, characterized in that, Its cellular structure includes: collector metal (10), P-type collector region (9), N-type electric field blocking layer (8), N-drift region (7), P-type base region (4), N+ emitter region (3), emitter ohmic contact P+ region (2), floating P region (13), trench emitter structure, split gate structure and emitter metal (1); collector metal (10), P-type collector region (9), N-type electric field blocking layer (8) and N-drift region (7) are stacked sequentially from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7), the floating P region (13) is located on the other side of the top layer of the N-drift region (7), the trench emitter structure is located on the top layer of the N-drift region (7) between the split gate structure and the floating P region (13), the P-type base region (4) is located on the top layer of the N-drift region (7) between the trench emitter structure and the split gate structure, the N+ emitter region (3) and the emitter ohmic contact P+ region (2) are in contact with each other on the top layer of the P-type base region (4), and the emitter metal (1) is located on the top layer of the N+ emitter region (7). 3) and the emitter ohmic contact P+ region (2); the floating P region (13) has a P+ region (17) in the top layer on the side away from the trench emitter structure, and the P+ region (17) has a metal layer (18); the floating P region (13) between the trench emitter structure and the P+ region (17) has a field oxide layer (19) of a polycrystalline silicon diode structure, and the field oxide layer (19) has a P-type region (20) of a polycrystalline diode and an N-type region (21) of a polycrystalline diode that are in side contact with each other, and the side of the P-type region (20) of the polycrystalline diode is in contact with the side of the metal layer (18); The trench emitter structure includes a trench emitter (12) and trench oxide layers (6) located on its sides and bottom; the split gate structure includes a split polysilicon gate (11) and a polysilicon gate (5), the polysilicon gate (5) being located on the split polysilicon gate (11), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5) and the N-drift region (7), the P-type base region (4) and the N+ emitter region (3); the split polysilicon gate (11) is connected to the N-type region (21); an external capacitor is connected in series between the split polysilicon gate (11) and the emitter metal (1).

23. A self-biased split-gate bipolar transistor according to claim 22, characterized in that, Below the P-type base region (4) is an N-type carrier storage layer (22).

24. A self-biased split-gate bipolar transistor according to claim 23, characterized in that, The N-type carrier storage layer (22), the trench emitter structure and the floating P-region (13) have a P-type region (23) below them, and the split gate structure has an N-drift region (7) between it and the P-type region (23).

25. A self-biased split-gate bipolar transistor according to claim 22, characterized in that, The trench emitter structure also has a split emitter (12-1), which is located below the trench emitter (12), and a trench oxide layer (6) is present between the split emitter (12-1) and the trench emitter (12).

26. A self-biased split-gate bipolar transistor according to claim 22, characterized in that, The N-type electric field blocking layer 8 is formed using a multi-step hydrogen implantation process.

27. A self-biased split-gate bipolar transistor according to claim 22, characterized in that, A superjunction structure is introduced in the N-drift region (7). The superjunction structure includes a P-pillar (24) and an N-pillar (25). The P-pillar (24) and the N-pillar (25) are located in the N-drift region (7) with their sides in contact with each other. The P-pillar (24) is connected to the floating P-region (13). The P-type base region 4 is above the N-pillar (25). The contact surface of the P-pillar (24) and the N-pillar (25) is located below the trench emitter structure.

28. A self-biased split-gate bipolar transistor according to claim 22, characterized in that, The P-type collector region (9) has an N-region (26) on one side.

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