A kind of MOS anti-radiation device of the complex structure of PN junction and preparation method

Abstract

The application discloses a kind of compound structure MOS anti-radiation devices of PN junction and preparation method, including substrate, substrate is formed with P well area by doping P-type impurity 3*10 18 cm ‑3 P well area upper surface is deposited with SiO2 layer, substrate, P well area and SiO2 layer side are inverted trapezoidal groove, inverted trapezoidal groove is shallow trench isolation structure, SiO2 layer top is gate, gate outside is set to symmetrically as sacrificial protective layer, gate and sacrificial protective layer are successively from bottom to top as intrinsic silicon, p-type semiconductor, n-type semiconductor and lead-out metal AI between, the inside of shallow trench isolation structure is low-energy shallow-junction arsenic LDD and source-drain region, source-drain region is closely attached to intrinsic silicon above, and the lead-out metal AI is grounded.In the sidewall of source-drain electrode gate, symmetric structure PN junction is increased, and intrinsic Si layer is sequentially arranged above source-drain region closely, PN junction, lead-out metal is grounded, and the whole device is realized on Si substrate, compatible with Si process, conducive to integration and cost control.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuit, and particularly relates to a PN-junction composite structure MOS anti-radiation device and a preparation method thereof. BACKGROUND

[0002] The working environment of an aerospace system is in space, and it is always affected by a large amount of space particle radiation, which is often the main cause of failure of the integrated circuit equipment of the aerospace system. When a semiconductor device is bombarded by a single high-energy particle from outside, an electron-hole pair is generated by ionization on the trajectory of the particle, the electric field in the depletion layer is distorted to extend to the lower part of the depletion layer, the funnel effect increases the charge collection depth, and the original logic level of the semiconductor device is reversed or the device is permanently damaged. Therefore, corresponding anti-radiation reinforcement measures must be taken in the design process of the semiconductor device to improve the reliability of the device.

[0003] At present, when a space circuit system is designed, a special circuit structure reinforcement measure is mainly taken at the circuit level to improve the anti-radiation performance of the circuit. The reinforcement method for single particle effect mainly improves the critical charge when a sensitive point is in a transient state, and adopts a redundancy mechanism. The measure for improving the critical charge is mainly feedback resistance reinforcement, that is, a feedback branch is designed by adding a resistance during circuit design, and the resistance is connected to the capacitor of the gate to form a low-pass filter to achieve the purpose of circuit reinforcement. The redundancy mechanism is divided into spatial redundancy and time redundancy. The spatial redundancy is to multiply the same circuit from the perspective of probability statistics to achieve the purpose of reinforcement, and the time redundancy is to divide the signal into multiple branches from the perspective of time sampling and send them to a voter after different time delays, and therefore it is also called time sampling technology.

[0004] Ultimately, the circuit level design will inevitably increase the chip area, and the reliability needs to be traded for the area. If the anti-radiation function can be realized on the device itself as the basic unit of the circuit, the reliability problem of the semiconductor device under radiation conditions can be fundamentally solved. Therefore, designing and manufacturing a composite structure MOS anti-radiation device compatible with the current Si process and low in cost has become one of the hotspots in the field of semiconductor research and solution. SUMMARY

[0005] In order to overcome the deficiencies of the prior art, the purpose of the present application is to provide a PN-junction composite structure MOS anti-radiation device and a preparation method thereof. A symmetric structure PN junction is added on the sidewall of the source-drain electrode and the gate, and an intrinsic Si layer, a PN junction and a grounding metal are sequentially arranged above the source-drain region. The whole device is realized on a Si substrate, is compatible with the Si process, and is conducive to integration and cost control.

[0006] In order to achieve the above object, the technical scheme adopted by the present application is:

[0007] A PN junction composite structure MOS anti-radiation device comprises a substrate, a P well region is formed on the substrate by doping P type impurities 3*10 18 cm -3 A SiO2 layer is deposited on the upper surface of the P well region 11, the substrate, the P well region and the SiO2 layer are provided with inverted trapezoidal grooves, the inverted trapezoidal grooves are shallow trench isolation structures (STI), the top of the SiO2 layer is a gate electrode, the outer side of the gate electrode is a sacrificial protective layer, LDD light doping drain injection is performed on the region not protected by photoresist with the sacrificial protective layer as a mask, source and drain regions are formed by doping, intrinsic silicon, p-type semiconductor, n-type semiconductor and lead-out metal AI are sequentially arranged from bottom to top between the gate electrode and the sacrificial protective layer, the drain region is closely attached to the intrinsic silicon, and the lead-out metal AI is grounded.

[0008] A preparation method of a PN junction composite structure MOS anti-radiation device comprises the following preparation methods.

[0009] S101, a substrate is provided, the substrate is P type impurities 1.5*10 15 cm -3 ;

[0010] S102, a P well region is formed on the substrate by doping P type impurities 3*10 18 cm -3 ;

[0011] S103, a shallow trench isolation (STI) is made;

[0012] S104, a gate electrode is generated, generally, an LPCVD process is mainly used, polysilicon is deposited by thermal decomposition of silane at 580 DEG C to 650 DEG C to generate the gate electrode;

[0013] S105, gate protection; a protective layer is deposited before source and drain injection;

[0014] S106, LDD light doping drain injection; photoetching, photoresist is coated and selected regions are exposed, arsenic ion injection is performed on the region not protected by the photoresist to form low-energy shallow junction arsenic LDD light doping drain injection, the interval of the low-energy shallow junction arsenic LDD is 16 nm;

[0015] S107, source and drain injection;

[0016] S108, a composite PN junction is generated;

[0017] S109, silicon nitride and silicon oxide on the gate electrode are etched away by ions and strong corrosive chemicals, and finally the PN junction composite structure MOS anti-radiation device is formed.

[0018] S103 is specifically:

[0019] S103-1, deposit a thin SiO2 layer on the substrate 10, with a thickness of about 2.2 nm; as an isolation layer to protect the active area from chemical contamination during nitride removal;

[0020] S103-2, nitride deposition; grow a thin layer of silicon nitride on the surface of the thin SiO2 layer, which helps to protect the active area during STI oxide deposition, and can act as a polishing barrier material;

[0021] S103-3, STI trench etching and oxide filling; after etching away the silicon nitride, silicon oxide and substrate with ion and strong corrosive chemicals, a reverse trapezoidal trench is formed, and the reverse trapezoidal trench is filled with CVD oxide to form a shallow trench isolation structure (STI);

[0022] S103-4, remove the nitride by chemical mechanical polishing.

[0023] S105 is specifically:

[0024] S105-1, deposit a thin SiO2 layer on the gate surface, with a thickness of about 2.2 nm;

[0025] S105-2, deposit a Si3N4 layer with a thickness of 20-30 nm as a sacrificial protective layer by CVD method, which acts as a mask for subsequent LDD light doping implantation;

[0026] S105-3, etch away the SiO2 and Si3N4 layers except the gate.

[0027] S107 is specifically:

[0028] S107-1, deposit Si3N4 by CVD method, which protects the gate from damage during source and drain area etching, and does not affect the self-alignment process of source and drain ion implantation;

[0029] S107-2, photoetching, glue coating and selective area exposure; the photoresist in the center reserved area is etched away, and the photoresist around it is etched away;

[0030] S107-3, using the sidewall as a mask, using a self-alignment process, with a doping concentration of about 4.02×10 20 cm -3 , to form the source and drain area.

[0031] S108 is specifically:

[0032] S108-1, remove the photoresist and etch away the part of Si3N4 inside the gate based on the sidewall by wet etching method;

[0033] S108-2, depositing intrinsic Si; depositing intrinsic silicon in the left-right symmetrical structure to prevent the diffusion of impurities in the PN junction from affecting the source-drain region;

[0034] S108-3, sequentially depositing a p-type semiconductor, an n-type semiconductor and an extraction metal Al22 in the left-right symmetrical structure, wherein the thickness of the P region of the PN junction is 10 nm.

[0035] Advantages of the present application:

[0036] The PN junction composite structure MOS proposed in the present application solves the problem of single particle effect leading to the inversion of the original logic level of the semiconductor device under irradiation conditions.

[0037] The PN junction composite structure MOS anti-irradiation device structure scheme proposed in the present application is novel, has high device integration and low process cost.

[0038] The PN junction composite structure MOS anti-irradiation device of the present application eliminates the funnel effect of the channel region caused by high-energy particle bombardment, increases the electron-hole discharge path, plays a role of adjusting the electric field and reducing the charge collection, and improves the anti-irradiation capability of the device. The application of intrinsic Si material near the source-drain region suppresses the influence of impurity diffusion in the PN junction on the source-drain region, ensuring the normal working current of the device under non-irradiation conditions. The entire device is realized on a Si substrate, which is compatible with Si technology, so that the designed device has excellent performance indicators and cost advantages. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The figure is a schematic diagram of a substrate.

[0040] Figure 2 The figure is a schematic diagram of a P-type impurity doped 3*10 18 cm -3 The figure is a schematic diagram of a P-well region formed.

[0041] Figure 3 The figure is a schematic diagram of depositing a thin SiO2 layer on the surface of the gate.

[0042] Figure 4 The figure is a schematic diagram of nitride deposition.

[0043] Figure 5 The figure is a schematic diagram of STI groove etching and oxide filling.

[0044] Figure 6 The figure is a schematic diagram of polishing to remove nitride. Figure 5

[0045] Figure 7 The figure is a schematic diagram of generating a gate. ​

[0046] Figure 8 This is a schematic diagram of a SiO2 layer deposited on the gate surface.

[0047] Figure 9 This is a schematic diagram of the sacrificial protective layer.

[0048] Figure 10 This is a schematic diagram of etching the SiO2 and Si3N4 layers excluding the gate.

[0049] Figure 11 This is a schematic diagram of lightly doped drain implantation in LDD.

[0050] Figure 12 This is a schematic diagram of Si3N4 deposited on the gate surface.

[0051] Figure 13 This is a schematic diagram of photoresist.

[0052] Figure 14 This is a schematic diagram of the source and drain regions.

[0053] Figure 15 A schematic diagram of Si3N4 with the gate cover removed.

[0054] Figure 16 This is a schematic diagram of intrinsic Si deposition.

[0055] Figure 17 This diagram illustrates the deposition of p-type and n-type semiconductors and the formation of lead-out metals (AI).

[0056] Figure 18 This is a schematic diagram of the structure of the present invention.

[0057] Figure 19 This is a schematic diagram illustrating the effect of the present invention. Detailed Implementation

[0058] The present invention will now be described in further detail with reference to the accompanying drawings.

[0059] This invention provides a method for fabricating NMOS devices. The fabrication process for this device is as follows:

[0060] S101, such as Figure 1 A substrate 10 is provided, wherein the substrate 10 is a P-type impurity 1.5*10⁻⁶. 15 cm -3 ;

[0061] S102, such as Figure 2 The substrate 10 is doped with 3*10 P-type impurities. 18 cm -3 A P-well region 11 is formed;

[0062] S103, fabricated using Shallow Trench Isolation (STI) technology;

[0063] S103-1, as Figure 3 A thin SiO2 layer 12 is deposited on the surface of the gate, with a thickness of about 2.2 nm; it can be used as an isolation layer to protect the active region from chemical contamination during the removal of the nitride;

[0064] S103-2, as Figure 4 The nitride is deposited. A thin layer of silicon nitride 13 is grown on the silicon surface, which helps to protect the active region during the deposition of the STI oxide, and can be used as a polishing barrier material;

[0065] S103-3, as Figure 5 STI trench etching and oxide filling. After etching the silicon nitride, silicon oxide and silicon with ions and strong corrosive chemicals, the trench is filled with CVD oxide to form a shallow trench isolation structure (STI) 110;

[0066] S103-4, as Figure 6 The nitride is removed by chemical mechanical polishing;

[0067] S104, as Figure 7 The gate is formed. Typically, the LPCVD process is mainly used to decompose silane at 580-650°C to deposit polysilicon and form the gate 14;

[0068] S105, gate protection. A protective layer is deposited before source-drain implantation;

[0069] S105-1, as Figure 8 A thin SiO2 layer is deposited on the surface of the gate 14, with a thickness of about 2.2 nm;

[0070] S105-2, as Figure 9 A Si3N4 layer with a thickness of 20-30 nm is deposited as a sacrificial protective layer 15 by CVD method, which acts as a mask for subsequent LDD light-doped drain implantation;

[0071] S105-3, as Figure 10 The SiO2 and Si3N4 layers outside the gate are etched;

[0072] S106, as Figure 11 LDD light-doped drain implantation. Photolithography, glue coating and selective exposure, arsenic ion implantation in the area not protected by photoresist, forming a low-energy shallow junction arsenic LDD 16 light-doped drain implantation, with an LDD spacing of 16 nm;

[0073] S107, source-drain implantation;

[0074] S107-1, as Figure 12Si3N4 is deposited by CVD method, which can protect the gate from being damaged during etching of source and drain regions and does not affect the self-alignment process of ion implantation of source and drain regions;

[0075] S107-2, as Figure 13 photolithography, glue coating and selective exposure. The photoresist 17 is reserved in the center region and the photoresist around the center region is etched off;

[0076] S107-3, as Figure 14 using the self-alignment process, the doping concentration is about 4.02*10 20 cm -3 , and the source and drain regions 18 are formed;

[0077] S108, composite PN junction is generated;

[0078] S108-1, as Figure 15 the photoresist is removed and the Si3N4 covered by the gate is removed by wet etching;

[0079] S108-2, as Figure 16 intrinsic Si is deposited. In the left-right symmetrical structure, the intrinsic Si 19 is deposited to prevent the diffusion of impurities in the PN junction from affecting the source and drain regions;

[0080] S108-3, as Figure 17 in the left-right symmetrical structure, the p-type semiconductor 20, the n-type semiconductor 21 and the lead-out metal Al 22 are sequentially deposited, wherein the thickness of the PN junction P region is 10 nm;

[0081] S109, as Figure 18 the Si3N4 and SiO2 on the gate are etched by ions and strong corrosive chemicals, and finally the composite structure of the PN junction MOS anti-radiation device is formed.

[0082] As Figure 18 shown: a PN junction composite MOS structure is used, the symmetrical structure PN junction is added on the side wall of the gate above the source and drain regions, the intrinsic Si layer, the PN junction and the lead-out metal ground are sequentially arranged above the source and drain regions. The whole device is realized on the Si substrate, which is compatible with the Si process, and is beneficial to integration and cost control.

[0083] Working principle of the present application:

[0084] As Figure 19The application adopts the composite MOS structure of PN junction to increase the discharge path of electron-hole, to inhibit the avalanche effect caused by the collision of particles under the action of large electric field, to reduce the collection of ionized charges, to play the role of adjusting electric field, to inhibit the funnel effect, and to improve the anti-radiation capability of the device. The intrinsic Si layer is used close to the source and drain region, which is to prevent the influence of impurity diffusion in the PN junction on the source / drain region, to ensure the normal working current of the device in the non-irradiation state. The metal grounding can better realize the discharge of electron-hole.

Claims

1. A composite structure MOS radiation-hardened device with a PN junction, characterized in that, Includes a substrate (10), on which 3*10 P-type impurities are doped. 18 cm -3 A P-well region (11) is formed, and a SiO2 layer (12) is deposited on the upper surface of the P-well region (11). The sides of the substrate (10), the P-well region (11) and the SiO2 layer (12) are inverted trapezoidal trenches, which are shallow channel isolation structures (110). The top of the SiO2 layer (12) is a gate (14), and the outside of the gate (14) is a sacrificial protection layer (15). Between the gate (14) and the sacrificial protection layer (15), from bottom to top, are intrinsic silicon (19), p-type semiconductor (20), n-type semiconductor (21) and lead-out metal AI (22). The source and drain regions (18) are closely attached to the intrinsic silicon (19), and the lead-out metal AI (22) is grounded. Using the sacrificial protective layer (15) as a mask, a low-energy shallow junction arsenic LDD (16) is lightly doped and implanted into the LDD. In the region not protected by the photoresist (17), the source and drain regions (18) are formed by doping using the sacrificial protective layer (15) as a mask. Among them, a Si3N4 layer with a thickness of 20~30nm was deposited by CVD as a sacrificial protection layer (15) and used as a mask for subsequent LDD light doped drain implantation; Arsenic ion implantation is performed in the region not protected by photoresist to form a low-energy shallow junction arsenic LDD (16) lightly doped drain implantation.

2. A method for fabricating a composite structure MOS radiation-hardened device based on a PN junction as described in claim 1, characterized in that, The preparation methods include the following; S101, Provide a substrate (10), wherein the substrate (10) is a P-type impurity 1.5*10 15 cm -3 ; S102, substrate (10) is doped with 3*10 P-type impurities. 18 cm -3 A P-well region is formed (11); S103, Create shallow trench isolation (STI); S104. Generation of the gate is usually achieved by using LPCVD process, which thermally decomposes silane at 580°C~650°C to achieve polysilicon deposition and generate the gate (14). S105, Gate protection; Protective layer deposited before source / drain injection; S106, LDD lightly doped drain implantation; photolithography, photoresist coating and selective area exposure, arsenic ion implantation in the area not protected by photoresist to form low energy shallow junction arsenic LDD (16) lightly doped drain implantation, the low energy shallow junction arsenic LDD (16) spacing is 16nm; S107, source / drain injection; S108, formation of a composite PN junction; S109. The Si3N4 and SiO2 on the gate are etched away with ions and highly corrosive chemicals to finally form the composite structure MOS radiation-resistant device of the PN junction.

3. The method for fabricating a composite structure MOS radiation-hardened device with a PN junction according to claim 2, characterized in that, Specifically, S103 is: S103-1, A thin SiO2 layer (12) with a thickness of 2.2 nm is deposited on the substrate (10); S103-2, Nitride deposition; A thin layer of Si3N4 (13) is grown on the surface of a thin SiO2 layer (12), which helps to protect the active region during the STI oxide deposition process and acts as a barrier material for polishing; S103-3, STI trench etching and oxide filling, after etching away Si3N4 (13), SiO2 layer (12) and substrate (10) with ions and strong corrosive chemicals, an inverted trapezoidal trench is formed, and the inverted trapezoidal trench is filled with CVD oxide to generate a shallow channel isolation structure (110). S103-4. Nitrides are removed by chemical mechanical polishing.

4. The method for fabricating a composite structure MOS radiation-hardened device with a PN junction according to claim 2, characterized in that, Specifically, S105 is: S105-1, A thin SiO2 layer with a thickness of 2.2 nm is deposited on the surface of the gate (14); S105-2, A Si3N4 layer with a thickness of 20~30nm is deposited by CVD as a sacrificial protective layer (15), which serves as a mask for subsequent LDD light doped drain implantation. S105-3, Etch the SiO2 and Si3N4 layers except for the gate.

5. The method for fabricating a composite structure MOS radiation-hardened device with a PN junction according to claim 2, characterized in that, Specifically, S107 is: S107-1, Si3N4 is deposited by CVD method. Its function is to protect the gate from damage during the etching process of the source and drain regions, and does not affect the self-alignment process of source and drain ion implantation. S107-2, Photolithography, applying photoresist and selecting an area for exposure; retain the photoresist in the center area (17) and etch away the photoresist around the perimeter; S107-3, using the sidewalls as a mask, employs a self-aligned process with a doping concentration of 4.02 × 10⁻⁶. 20 cm -3 This forms the source / drain region (18).

6. The method for fabricating a composite structure MOS radiation-hardened device with a PN junction according to claim 2, characterized in that, Specifically, S108 is: S108-1, Remove the photoresist and use wet etching to etch away the part of Si3N4 based on the SiO2 layer (12) inside the gate; S108-2, Deposit intrinsic Si; Deposit intrinsic silicon (19) in the left-right symmetrical structure to prevent the diffusion of impurities in the PN junction from affecting the source and drain regions; S108-3. In the left-right symmetrical structure, p-type semiconductor (20), n-type semiconductor (21) and lead-out metal AI (22) are deposited sequentially, wherein the thickness of the PN junction P region is 10nm.

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