Storage device and manufacturing method thereof

Abstract

The present invention discloses a storage device and a method for manufacturing the same, wherein the storage device includes a substrate, a storage cell, and a first spacer layer. The storage cell is disposed on the substrate and includes a first electrode, a second electrode, and a storage material layer. The second electrode is disposed vertically above the first electrode, and the storage material layer is disposed vertically between the first and second electrodes. The first spacer layer is disposed on the sidewalls of the storage cell. The first spacer layer includes a first portion and a second portion. The first portion is disposed on the sidewalls of the first electrode, and the second portion is disposed on the sidewalls of the second electrode, and the horizontal thickness of the second portion is greater than the horizontal thickness of the first portion.

Description

Technical Field

[0001] The present invention relates to a storage device and a manufacturing method thereof, and in particular to a storage device with a spacer layer and a manufacturing method thereof. Background Art

[0002] Semiconductor memory is a semiconductor device used to store data in computers or electronic products. It can be broadly divided into volatile memory and non-volatile memory. Volatile memory refers to computer memory in which the stored data disappears when the operating power is interrupted. In contrast, non-volatile memory has the characteristic of not losing stored data due to power supply interruptions. For example, resistive random access memory (RRAM) is a type of non-volatile memory. Its low operating voltage, low power consumption, and high write speed make it a memory structure that can be used in many electronic devices. Summary of the Invention

[0003] The present invention provides a storage device and a method for manufacturing the same, which utilizes a spacer layer formed on the sidewall of a storage cell and makes the spacer layer on the sidewall of an upper electrode of the storage cell relatively thick, thereby enhancing the protection effect of the storage cell in subsequent manufacturing processes, thereby improving the manufacturing yield of the storage device.

[0004] One embodiment of the present invention provides a memory device comprising a substrate, a memory cell, and a first spacer layer. The memory cell is disposed on the substrate and includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed vertically above the first electrode, and the memory material layer is disposed vertically between the first and second electrodes. The first spacer layer is disposed on the sidewalls of the memory cell and includes a first portion and a second portion. The first portion is disposed on the sidewalls of the first electrode, the second portion is disposed on the sidewalls of the second electrode, and the second portion has a horizontal thickness greater than the horizontal thickness of the first portion.

[0005] One embodiment of the present invention provides a method for manufacturing a memory device, comprising the following steps: forming a memory cell on a substrate, the memory cell comprising a first electrode, a second electrode, and a memory material layer; the second electrode being disposed vertically above the first electrode, and the memory material layer being disposed vertically between the first and second electrodes; forming a first spacer layer on the sidewalls of the memory cell, the first spacer layer comprising a first portion and a second portion; the first portion being disposed on the sidewalls of the first electrode, the second portion being disposed on the sidewalls of the second electrode, the second portion being thicker in a horizontal direction than the first portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a storage device according to an embodiment of the present invention;

[0007] Figures 2 to 6 FIG. 1 is a schematic diagram of a method for manufacturing a storage device according to an embodiment of the present invention, wherein

[0008] Figure 3 for Figure 2 Schematic diagram of the situation afterwards;

[0009] Figure 4 for Figure 3 Schematic diagram of the situation afterwards;

[0010] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0011] Figure 6 for Figure 5 Schematic diagram of the situation afterwards.

[0012] Description of main component symbols

[0013] 10 base

[0014] 11 Dielectric layer

[0015] 21 Dielectric layer

[0016] 22 Metal Interconnect

[0017] 23 Stop layer

[0018] 30 Intermetallic Dielectric Layer

[0019] 40 Metal Interconnect

[0020] 41 Barrier layer

[0021] 42 metal layers

[0022] 50 storage units

[0023] 51 first electrode

[0024] 52 Storage Material Layer

[0025] 53 second electrode

[0026] 54 Mask layer

[0027] 60 first spacer layer

[0028] 72 second spacer layer

[0029] 72S spacer structure

[0030] 74 Low-k dielectric layer

[0031] 76 Stop Layer

[0032] 78 Low-k dielectric layer

[0033] 91 Finishing process

[0034] 92 Etching Process

[0035] 100 Storage Device

[0036] BP bottom part

[0037] BS bottom surface

[0038] CS1 connection structure

[0039] CS21 connection structure

[0040] CS22 connection structure

[0041] CS31 connection structure

[0042] CS32 connection structure

[0043] D1 First direction

[0044] D2 Second direction

[0045] OP Opening

[0046] OS protrusion structure

[0047] P1 Part 1

[0048] P2 Part 2

[0049] P3 Part 3

[0050] R1 Zone 1

[0051] R2 Zone 2

[0052] SW1 side wall

[0053] SW2 side wall

[0054] TS top surface

[0055] W1 width

[0056] W2 width

[0057] W3 width

[0058] W4 width DETAILED DESCRIPTION

[0059] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention.

[0060] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0061] The terms “on,” “over,” and “over” should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0062] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify claim elements. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0063] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0064] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0065] See also Figure 1 . Figure 1 FIG. 1 is a schematic diagram of a storage device 100 according to an embodiment of the present invention. Figure 1 As shown, the memory device 100 includes a substrate 10, at least one memory cell 50, and a first spacer layer 60. The memory cell 50 is disposed on the substrate 10 and includes a first electrode 51, a second electrode 53, and a memory material layer 52. The second electrode 53 is disposed in a vertical direction (e.g., Figure 1 The first electrode 51 is provided on the first electrode 51 in the first direction D1 shown in FIG, and the storage material layer 52 is provided between the first electrode 51 and the second electrode 53 in the first direction D1. The first spacer layer 60 is provided on the sidewalls of the memory cell 50 (for example, the sidewall SW1 of the first electrode 51, the sidewall SW2 of the second electrode 53, and the sidewall of the storage material layer 52). The first spacer layer 60 includes a first portion P1 and a second portion P2. The first portion P1 is provided on the sidewall SW1 of the first electrode 51, the second portion P2 is provided on the sidewall SW2 of the second electrode 53, and the second portion P2 is provided in a horizontal direction (for example, Figure 1 The thickness of the first portion P1 in the second direction D2 (shown in FIG) is greater than the thickness of the first portion P1 in the second direction D2. Covering the sidewall SW2 of the second electrode 53 with the thicker first portion P1 can enhance the protection of the second electrode 53 during the relevant manufacturing process, thereby improving the manufacturing yield of the storage device 100.

[0066] In some embodiments, the substrate 10 may be formed in a thickness direction (eg Figure 1The substrate 10 has a top surface TS and a bottom surface BS opposite each other in the first direction D1 (as shown in FIG). The memory cell 50 and the first spacer layer 60 may be disposed on one side of the top surface TS, but this is not limited thereto. A horizontal direction substantially perpendicular to the first direction D1 (e.g., the second direction D2) may be substantially parallel to the top surface TS and / or the bottom surface BS of the substrate 10, but this is not limited thereto. Furthermore, as described herein, the distance between a relatively higher position or / and component in the vertical direction (e.g., the first direction D1) and the bottom surface BS of the substrate 10 in the first direction D1 may be greater than the distance between a relatively lower position or / and component in the first direction D1 and the bottom surface BS of the substrate 10 in the first direction D1. The lower portion or bottom portion of each component may be closer to the bottom surface BS of the substrate 10 in the first direction D1 than the upper portion or top portion of the component. A component above another component may be considered to be relatively farther from the bottom surface BS of the substrate 10 in the first direction D1, while a component below another component may be considered to be relatively closer to the bottom surface BS of the substrate 10 in the first direction D1, but this is not limited thereto.

[0067] In some embodiments, the memory cell 50 may be a structure that is wide at the top and narrow at the bottom, and the thickness of the first spacer layer 60 surrounding the memory cell 50 in the horizontal direction (e.g., the second direction D2 and other directions orthogonal to the first direction D1) may gradually decrease from top to bottom, so the overall width of the memory cell 50 and the first spacer layer 60 may also have the feature of being wide at the top and narrow at the bottom. In some embodiments, the top width of the first electrode 51 (e.g., Figure 1 The width W2 shown in FIG may be greater than the bottom width of the first electrode 51 (eg Figure 1 The width W1 shown in FIG), the top width of the second electrode 53 (eg Figure 1 The width W4 shown in FIG may be greater than the bottom width of the second electrode 53 (eg Figure 1 ), the width of the second electrode 53 (e.g., width W3 and / or width W4) may be greater than the width of the first electrode 51 (e.g., width W1 and / or width W2), and the width of the storage material layer 52 may be between the width W2 of the first electrode 51 and the width W3 of the second electrode 53, but is not limited thereto. In addition, the width of each of the above components may also be considered as the length in the horizontal direction (e.g., the second direction D2). By making the memory cell 50 have a structure that is wide at the top and narrow at the bottom, it is possible to facilitate the formation of a first spacer layer 60 having a relatively thick second portion P2, and by maintaining some portions of the first spacer layer 60 relatively thin, it is possible to avoid the negative impact of a comprehensive increase in the thickness of the first spacer layer 60 on other related manufacturing processes.

[0068] In some embodiments, the memory device 100 may further include a second spacer layer 72 disposed on the first spacer layer 60, and the first spacer layer 60 may further include a bottom portion BP disposed between the substrate 10 and the second spacer layer 72 in the first direction D1. In some embodiments, the first portion P1, the second portion P2, and the bottom portion BP of the first spacer layer 60 may be directly connected to each other and may be directly connected to each other in a cross-sectional view of the memory device 100 (e.g., Figure 1 ) may have an L-shaped structure, but is not limited thereto. In addition, the thickness of the second portion P2 may be greater than the thickness of the first portion P1 and the thickness of the bottom portion BP. In some embodiments, the thickness of the second portion P2 of the first spacer layer 60 may be defined as the distance in the horizontal direction (e.g., the second direction D2) between the surface of the second portion P2 in contact with the second electrode 53 and the surface of the second portion P2 in contact with the second spacer layer 72. The thickness of the first portion P1 of the first spacer layer 60 may be defined as the distance in the horizontal direction (e.g., the second direction D2) between the surface of the first portion P1 in contact with the first electrode 51 and the surface of the first portion P1 in contact with the second spacer layer 72. The thickness of the bottom portion BP of the first spacer layer 60 may be defined as the distance in the first direction D1 between the surface of the bottom portion BP in contact with the second spacer layer 72 and the surface of the bottom portion BP facing the substrate 10. In addition, in some embodiments, the upper surface of the first spacer layer 60 may be higher than the upper surface of the second electrode 53 in the first direction D1, thereby ensuring that the second electrode 53 can be completely covered by the second portion P2 of the first spacer layer 60 in the horizontal direction (for example, the second direction D2 and other directions orthogonal to the first direction D1), but is not limited to this.

[0069] Influenced by the shapes of the memory cell 50 and the first spacer layer 60, at least a portion of the second spacer layer 72 can be considered a spacer structure 72S that is narrow at the top and wide at the bottom, while the bottom portion BP of the first spacer layer 60 can be disposed between the substrate 10 and the spacer structure 72S in the first direction D1. In some embodiments, a portion of the second spacer layer 72 and / or a portion of the spacer structure 72S can be located between the bottom portion BP of the first spacer layer 60 and the first portion P1 of the first spacer layer 60 in the first direction D1, while another portion of the second spacer layer 72 and / or another portion of the spacer structure 72S can be located between the bottom portion BP of the first spacer layer 60 and the second portion P2 of the first spacer layer 60 in the first direction D1. Furthermore, the material composition of the second spacer layer 72 can be different from that of the first spacer layer 60, thereby providing a desired etching selectivity in related fabrication processes. For example, the first spacer layer 60 may be formed of a nitride dielectric material (eg, silicon nitride) or other suitable dielectric material, and the second spacer layer 72 may be formed of an oxide dielectric material (eg, silicon oxide) or other dielectric material different from the first spacer layer 60 .

[0070] In some embodiments, the memory device 100 may include a plurality of memory cells 50 and corresponding first and second spacer layers 60 and 72. Furthermore, the memory device 100 may also include a plurality of metal interconnects 40 disposed on the substrate 10. Each metal interconnect 40 may be disposed below a memory cell 50 in a first direction D1 and electrically connected to a first electrode 51 in the memory cell 50. In some embodiments, each metal interconnect 40 may be considered a via conductor and extend primarily along a vertical direction (e.g., the first direction D1), but is not limited thereto. In some embodiments, each metal interconnect 40 may include a barrier layer 41 and a metal layer 42. The barrier layer 41 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable barrier materials, while the metal layer 42 may include tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or other suitable metal materials.

[0071] In some embodiments, the substrate 10 may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include, for example, a silicon substrate, a silicon-germanium semiconductor substrate, or a silicon-on-insulator (SOI) substrate, while the non-semiconductor substrate may include, but is not limited to, a glass substrate, a plastic substrate, or a ceramic substrate. For example, when the substrate 10 includes a semiconductor substrate, a plurality of silicon-based field-effect transistors (not shown), a dielectric layer covering the silicon-based field-effect transistors (e.g., a dielectric layer covering the silicon-based field-effect transistors) may be formed on the semiconductor substrate as needed. Figure 1 ) and the metal interconnect 22 shown in the figure, and then the above-mentioned metal interconnect 40 is formed. In some embodiments, the metal interconnect 40 can be electrically connected to part of the metal interconnect 22 respectively, and can be electrically connected to the above-mentioned silicon-based field-effect transistor downward through part of the metal interconnect 22, but is not limited thereto. In some embodiments, each metal interconnect 22 can be regarded as a trench conductor and extends mainly in the horizontal direction. In addition, in some embodiments, the substrate 10 may include a first region R1 and a second region R2, wherein the first region R1 can be regarded as a memory cell region on which the memory cell 50 is arranged, and the second region R2 can be regarded as a logic region, but is not limited thereto. In some embodiments, the area between adjacent memory cells 50 can be regarded as an area corresponding to a word line, and the metal interconnect 22 in this area may include a word line or be electrically connected to a word line, but is not limited thereto.

[0072] In some embodiments, the memory device 100 may further include a stop layer 23, an inter-metal dielectric (IMD) layer 30, a low-k dielectric layer 74, a stop layer 76, a low-k dielectric layer 78, and a plurality of connection structures (e.g., connection structure CS1, connection structure CS21, connection structure CS22, connection structure CS31, and connection structure CS32). The IMD layer 30 may be disposed on the substrate 10 and located on the dielectric layer 21, and the stop layer 23 may be disposed between the IMD layer 30 and the dielectric layer 21. The metal interconnect 40 may penetrate the IMD layer 30 and the stop layer 23 in a first direction D1, and the first spacer layer 60 and the second spacer layer 72 may be disposed on the IMD layer 30 and the metal interconnect 40. An opening OP may be disposed above the metal interconnect 22 between adjacent memory cells 50 and extend through the second spacer layer 72 and the first spacer layer 60 in the first direction D1. A low-k dielectric layer 74 may be disposed on the intermetallic dielectric layer 30 and the second spacer layer 72, with a portion of the low-k dielectric layer 74 disposed within the opening OP. A connection structure CS21 may be disposed between adjacent memory cells 50 and extend through the stop layer 23, the intermetallic dielectric layer 30, and the low-k dielectric layer 74 within the opening OP in the first direction D1 to electrically connect to the metal interconnect 22 between the adjacent memory cells 50. A connection structure CS31 may be disposed on the second region R2 and extend through the stop layer 23, the intermetallic dielectric layer 30, and the low-k dielectric layer 74 in the first direction D1 to electrically connect to the metal interconnect 22 on the second region R2.

[0073] The stop layer 76 may be disposed on the low-k dielectric layer 74, the second spacer layer 72, the first spacer layer 60, the mask layer 54, the connection structure CS21, and the connection structure CS31, and the low-k dielectric layer 78 may be disposed on the stop layer 76. The connection structure CS1 may penetrate the low-k dielectric layer 78, the stop layer 76, and the mask layer 54 on the memory cell 50 in the first direction D1 to contact and form an electrical connection with the second electrode 53. The connection structure CS22 may penetrate the low-k dielectric layer 78 and the stop layer 76 on the connection structure CS21 in the first direction D1 to contact and form an electrical connection with the connection structure CS21. The connection structure CS32 may penetrate the low-k dielectric layer 78 and the stop layer 76 on the connection structure CS31 in the first direction D1 to contact and form an electrical connection with the connection structure CS31. In some embodiments, each of the above-mentioned connection structures (e.g., connection structure CS1, connection structure CS21, connection structure CS22, connection structure CS31 or / and connection structure CS32) may respectively include a contact hole conductor and a trench conductor disposed on and connected to the contact hole conductor, but is not limited thereto.

[0074] In some embodiments, the structures of each metal interconnect 22 and each connection structure (e.g., connection structure CS1, connection structure CS21, connection structure CS22, connection structure CS31, and / or connection structure CS32) may be similar to the structure of metal interconnect 40 and may include a barrier layer (not shown) and a metal layer (not shown), respectively, but the present invention is not limited thereto. Dielectric layer 11, dielectric layer 21, and intermetallic dielectric layer 30 may each include silicon oxide, a low-k dielectric material, or other suitable dielectric materials. Low-k dielectric layer 74 and low-k dielectric layer 78 may each include a dielectric material having a dielectric constant less than 2.7, such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), methyl silesquioxane (MSQ), silicon oxycarbon hydride (SiOC-H), a porous dielectric material, or other suitable dielectric materials. The stop layer 23 and the stop layer 76 may respectively include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or other suitable insulating materials.

[0075] In some embodiments, the first electrode 51 and the second electrode 53 in each memory cell 50 may respectively include aluminum, platinum, ruthenium, iridium, nickel, cobalt, chromium, tungsten, copper, hafnium, zirconium, zinc, gold, titanium, alloys thereof, mixtures thereof, or other suitable metallic conductive materials or non-metallic conductive materials. The storage material layer 52 in each memory cell 50 may include a variable resistor material, a phase change material, or other suitable material layer capable of providing a memory operation by changing state. The variable resistor material may include a metal oxide such as a transition metal oxide, a perovskite oxide, or other suitable variable resistor material, and the phase change material may include a germanium antimony tellurium alloy (Ge2Sb2Te5, GST) or other suitable phase change material. When the storage material layer 52 is a variable resistance material, the memory cell 50 can be regarded as a resistive memory cell, and the storage material layer 52 can be regarded as a switching medium in the resistive memory cell. By applying appropriate voltages to the upper and lower electrodes in the stacked structure (for example, the first electrode 51 and the second electrode 53), the resistance value of the resistive memory cell can be changed, so that the resistive memory cell can be switched between a high resistance state (HRS) and a low resistance state (LRS), thereby realizing operating modes of the storage device such as storing data, reading data, and resetting.

[0076] See also Figures 2 to 6 as well as Figure 1 . Figures 2 to 6 The diagram shows a method for manufacturing a memory device according to an embodiment of the present invention, wherein Figure 3 Draws Figure 2 Schematic diagram of the situation afterwards, Figure 4 Draws Figure 3 Schematic diagram of the situation afterwards, Figure 5 Draws Figure 4 Schematic diagram of the situation afterwards, Figure 6 Draws Figure 5 The following diagram shows the situation: Figure 1 can be considered as depicting Figure 6 The following is a schematic diagram of the situation, but it is not limited to this. Figure 1As shown, the method for manufacturing the memory device 100 of this embodiment may include the following steps. A memory cell 50 is formed on a substrate 10, and the memory cell 50 includes a first electrode 51, a second electrode 53, and a memory material layer 52. The second electrode 53 is disposed above the first electrode 51 in a first direction D1, and the memory material layer 52 is disposed between the first electrode 51 and the second electrode 53 in the first direction D1. A first spacer layer 60 is formed on the sidewalls of the memory cell 50, and the first spacer layer 60 includes a first portion P1 and a second portion P2. The first portion P1 is disposed on the sidewall SW1 of the first electrode 51, and the second portion P2 is disposed on the sidewall SW2 of the second electrode 53. The thickness of the second portion P2 in a horizontal direction (e.g., the second direction D2) is greater than the thickness of the first portion P1 in the second direction D2.

[0077] To further illustrate, the manufacturing method of the storage device of this embodiment may include but is not limited to the following steps. First, Figure 2 As shown, a dielectric layer 11, a dielectric layer 21, a metal interconnect 22, a stop layer 23, an intermetallic dielectric layer 30, a metal interconnect 40, and a memory cell 50 are formed on a substrate 10. In some embodiments, a material stack corresponding to the memory cell 50 may be formed on the metal interconnect 40 and the intermetallic dielectric layer 30, and a mask layer 54 may be formed on this material stack. An etching process is then performed on this material stack using the mask layer 54 and / or a patterned photoresist layer (not shown) as an etching mask to form the memory cell 50. The mask layer 54 may comprise an oxide insulating material or other suitable insulating material. The etching process may comprise a reactive ion etching (RIE) process or other suitable etching method. In addition, in some embodiments, a lateral trimming process 91 may be used to etch the memory cell 50 so that the memory cell 50 has the aforementioned wide-top, narrow-bottom structure. The trimming process 91 may be performed during or / and after the etching process. For example, the trimming process 91 can be an etching step in a RIE etching process. By adjusting the etching parameters (e.g., reducing the polymer-based etching effect), the lateral etching conditions can be modified, thereby forming a memory cell 50 having a wide-top, narrow-bottom structure. In some embodiments, the materials of the first electrode 51 and the second electrode 53 can be combined with the trimming process 91 to form a memory cell 50 having a wide-top, narrow-bottom structure. In other words, the material composition of the second electrode 53 can be different from the material composition of the first electrode 51, and the etching rate of the trimming process 91 on the first electrode 51 can be slightly higher than the etching rate of the trimming process 91 on the second electrode 53, but this is not limited to this.

[0078] Then, if Figure 3As shown, a first spacer layer 60 is formed on the intermetallic dielectric layer 30, the metal interconnect 40, the memory cell 50, and the mask layer 54. In some embodiments, influenced by the memory cell 50 having a wide-top-narrow-bottom structure, the first spacer layer 60 formed on the memory cell 50 and the mask layer 54 may have an overhang structure OS. For example, the first spacer layer 60 may include a first portion P1, a second portion P2, a third portion P3, and a bottom portion BP. The first portion P1 may be disposed on the sidewall SW1 of the first electrode 51, the second portion P2 may be disposed on the sidewall SW2 of the second electrode 53, the third portion P3 may be disposed on the memory cell 50 and the mask layer 54 in the first direction D1, and the bottom portion BP may be disposed on the intermetallic dielectric layer 30 and the metal interconnect 40. The third portion P3 may be directly connected to the second portion P2, the second portion P2 may be directly connected to the first portion P1, and the first portion P1 may be directly connected to the bottom portion BP. Due to the influence of the memory cell 50 having a wide-top-narrow-bottom structure or / and by adjusting the process parameters of the film formation process for forming the first spacer layer 60, the third portion P3 and the second portion P2 can be made relatively thicker and the first portion P1 and the bottom portion BP can be made relatively thinner, and a portion of the third portion P3 and the second portion P2 can form a protrusion structure OS on the memory cell 50.

[0079] Afterwards, if Figure 4 and Figure 5 As shown, a spacer structure 72S is formed on the first spacer layer 60. The method of forming the spacer structure 72S may include but is not limited to the following steps. Figure 4 As shown, a second spacer layer 72 may be formed on the first spacer layer 60, and the second spacer layer 72 may fill the space between adjacent memory cells 50. Then, as shown in FIG. Figures 4 and 5 As shown, after the second spacer layer 72 is formed, an etching process 92 may be performed, and at least a portion of the second spacer layer 72 may be etched by the etching process 92 to form a spacer structure 72S. In some embodiments, at least one etching step in the etching process 92 may be considered an etch-back step for the second spacer layer 72, thereby removing a portion of the second spacer layer 72 (e.g., the second spacer layer 72 located above the memory cell 50 in the first direction D1) and a portion of the bottom portion BP of the first spacer layer 60 to form an opening OP. The opening OP is located between adjacent memory cells 50 in the second direction D2, and the opening OP may penetrate the second spacer layer 72 and the first spacer layer 60 in the first direction D1 to expose a portion of the intermetallic dielectric layer 30.

[0080] In some embodiments, before the etching process 92, at least a portion of the third portion P3 of the first spacer layer 60 may be located between the second spacer layer 72 and the memory cell 50 in the first direction D1, and the third portion P3 of the first spacer layer 60 may be removed by the etching process 92. Furthermore, both before and after the etching process 92, the second electrode 53 may be completely covered by the second portion P2 of the first spacer layer 60 in the horizontal direction (e.g., the second direction D2), thereby protecting the second electrode 53. Because the protrusion structure OS is relatively thick, the problem of over-etching the first spacer layer 60 during the etching process 92, which would expose the sidewalls of the second electrode 53, can be alleviated. The mask layer 54 may cover the upper surface of the second electrode 53 both before and after the etching process 92. Therefore, the first spacer layer 60 and the mask layer 54 can be used to cover the second electrode 53 to achieve a protective effect. Furthermore, since the opening OP must be formed through the etching process 92, the relatively thin bottom portion BP of the first spacer layer 60 can reduce the etching intensity required for the etching process 92, thereby relatively reducing the etching of the second portion P2 of the first spacer layer 60 and ensuring that the second electrode 53 is completely covered in the horizontal direction by the second portion P2 of the first spacer layer 60. In other words, if the thickness of the first spacer layer 60 is increased across the board, the etching intensity will be relatively increased (e.g., the etching time will be increased) in order to form the opening OP penetrating the first spacer layer 60. This will increase the risk of the first spacer layer 60 on the sidewalls of the second electrode 53 being etched, exposing the second electrode 53, and causing related process defects.

[0081] In some embodiments, the etching process 92 may also be used to remove the second spacer layer 72 and the first spacer layer 60 on the second region R2, thereby exposing the intermetallic dielectric layer 30 on the second region R2. Figure 5 and Figure 1 As shown, the low-k dielectric layer 74, the connection structure CS21, and the connection structure CS31 described above may be formed. In some embodiments, a planarization process may be performed after the low-k dielectric layer 74 is formed and before the connection structures CS21 and CS31 are formed to make the upper surface of the low-k dielectric layer 74, the upper surface of the spacer structure 72S, the upper surface of the first spacer layer 60, and the upper surface of the mask layer 54 substantially coplanar, but the present invention is not limited thereto. Then, as shown in FIG. Figure 6 and Figure 1 As shown, the stop layer 76, the low-k dielectric layer 74, the connection structure CS1, the connection structure CS22 and the connection structure CS32 can be formed to form the following structure: Figure 1 The storage device 100 is shown.

[0082] In summary, in the storage device and its manufacturing method of the present invention, a first spacer layer having a protrusion structure can be formed on the storage cell, thereby forming a relatively thick first spacer layer on the sidewall of the second electrode to enhance the protection effect of the storage cell in subsequent manufacturing processes, thereby improving the manufacturing yield of the storage device.

[0083] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A storage device comprising: substrate; A storage unit is provided on the substrate, wherein the storage unit comprises: a first electrode; a second electrode disposed vertically above the first electrode; and a storage material layer, disposed between the first electrode and the second electrode in the vertical direction; and A first spacer layer is disposed on a sidewall of the memory cell, wherein the first spacer layer comprises: a first portion disposed on a sidewall of the first electrode; and The second portion is arranged on the side wall of the second electrode, wherein the thickness of the second portion in the horizontal direction is greater than the thickness of the first portion in the horizontal direction, wherein the second electrode is completely covered by the second portion of the first spacer layer in the horizontal direction.

2. The storage device according to claim 1, further comprising: The second spacer layer is disposed on the first spacer layer, wherein the material composition of the second spacer layer is different from the material composition of the first spacer layer. 3 . The memory device according to claim 2 , wherein the first spacer layer further comprises a bottom portion disposed between the substrate and the second spacer layer in the vertical direction. 4 . The memory device as claimed in claim 3 , wherein a portion of the second spacer layer is located between the bottom portion of the first spacer layer and the first portion of the first spacer layer in the vertical direction. 5 . The memory device as claimed in claim 3 , wherein a portion of the second spacer layer is located between the bottom portion of the first spacer layer and the second portion of the first spacer layer in the vertical direction. 6 . The memory device as claimed in claim 1 , wherein a top width of the first electrode is greater than a bottom width of the first electrode. 7 . The memory device as claimed in claim 1 , wherein a top width of the second electrode is greater than a bottom width of the second electrode. 8 . The memory device as claimed in claim 1 , wherein a width of the second electrode is greater than a width of the first electrode. 9 . The memory device as claimed in claim 1 , wherein the memory material layer comprises a variable resistance material or a phase change material.

10. A method for manufacturing a storage device, comprising: A memory cell is formed on a substrate, wherein the memory cell comprises: a first electrode; a second electrode disposed vertically above the first electrode; and a storage material layer, disposed between the first electrode and the second electrode in the vertical direction; and A first spacer layer is formed on the sidewall of the memory cell, wherein the first spacer layer comprises: a first portion disposed on a sidewall of the first electrode; and The second portion is arranged on the side wall of the second electrode, wherein the thickness of the second portion in the horizontal direction is greater than the thickness of the first portion in the horizontal direction, wherein the second electrode is completely covered by the second portion of the first spacer layer in the horizontal direction. 11 . The method for manufacturing a memory device according to claim 10 , wherein the first spacer layer further comprises a third portion disposed on the memory cell in the vertical direction and connected to the second portion of the first spacer layer. 12 . The method for manufacturing a memory device according to claim 11 , wherein the third portion of the first spacer layer and a portion of the second portion of the first spacer layer form a protrusion structure on the memory cell.

13. The method for manufacturing a storage device according to claim 11, further comprising: A spacer structure is formed on the first spacer layer, wherein the method of forming the spacer structure includes: forming a second spacer layer on the first spacer layer; and After the second spacer layer is formed, an etching process is performed, wherein at least a portion of the second spacer layer is etched by the etching process to form the spacer structure.

14. The method for manufacturing a memory device as claimed in claim 13, wherein before the etching process, at least a portion of the third portion of the first spacer layer is located between the second spacer layer and the memory cell in the vertical direction, and the third portion of the first spacer layer is removed by the etching process. 15 . The method for manufacturing a memory device according to claim 13 , wherein before and after the etching process, the second electrode is completely covered by the second portion of the first spacer layer in the horizontal direction. 16 . The method for manufacturing a memory device according to claim 13 , wherein a material composition of the second spacer layer is different from a material composition of the first spacer layer. 17 . The method for manufacturing a memory device according to claim 13 , wherein the first spacer layer further comprises a bottom portion disposed between the substrate and the spacer structure in the vertical direction. 18 . The method for manufacturing a memory device according to claim 17 , wherein a portion of the spacer structure is located between the bottom portion of the first spacer layer and the first portion of the first spacer layer in the vertical direction. 19 . The method for manufacturing a memory device according to claim 17 , wherein a portion of the spacer structure is located between the bottom portion of the first spacer layer and the second portion of the first spacer layer in the vertical direction.

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