Capacitor structure, semiconductor structure and method of manufacturing thereof

Abstract

A capacitor structure is provided. The capacitor structure includes a substrate, a middle-of-line (MEOL) structure, and a metallization structure. The substrate has a first surface and a second surface opposite the first surface. The MEOL structure is on the first surface of the substrate. The MEOL structure includes a capacitor including a bottom plate and a top plate on the bottom plate. The metallization structure is on the MEOL structure. The substrate further includes a plurality of first through-vias extending from the second surface of the substrate to the bottom plate. A semiconductor structure including the capacitor structure and a method of fabricating the semiconductor structure are also provided.

Description

Technical Field

[0001] The present invention discloses a capacitor structure, a semiconductor structure and a method for manufacturing the same; in particular, the capacitor structure includes a plurality of back-side TSVs connected to the base plate of the capacitor in the capacitor structure, thereby reducing the resistance of the base plate. Background Technology

[0002] Integrated circuits (ICs) generally include various passive components. Capacitors are a common passive component, widely used in ICs for various applications, such as mixed-signal applications like filters and analog-to-digital converters. For example, switched-capacitor circuits are widely used in mixed-signal and analog-to-digital interfaces. Switched-capacitor circuits are typically used to perform various functions, including signal sampling, filtering, and digitization.

[0003] Metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors are two widely used capacitor structures in this type of circuit. Generally, MIM capacitors consist of an insulator sandwiched between two metal layers, while MOM capacitors are composed of a large number of parallel fingers or electrodes formed on multiple metal layers. Summary of the Invention

[0004] In one illustrative embodiment, the present invention provides a capacitor structure. The capacitor structure includes a substrate, a middle-of-line (MEOL) structure, and a metallization structure. The substrate has a first surface and a second surface opposite to the first surface. The MEOL structure is located on the first surface of the substrate. The MEOL structure includes a capacitor, which includes a base plate and a top plate located on the base plate. The metallization structure is located on the MEOL structure. The substrate also includes a plurality of first through-paths extending from the second surface of the substrate to the base plate.

[0005] In another illustrative embodiment, the present invention provides a semiconductor structure. The semiconductor structure includes a packaging substrate, a first capacitor structure, and a semiconductor device. The first capacitor structure is bonded to the packaging substrate. The first capacitor structure includes a capacitor, and the packaging substrate is electrically connected to the first capacitor structure through a plurality of first through-paths extending from the capacitor to the back side of the first capacitor structure. The semiconductor device is bonded to the first capacitor structure.

[0006] In yet another exemplary embodiment, the present invention provides a method for manufacturing a semiconductor structure. The method comprises the following operations: providing a substrate having a first surface and a second surface opposite to the first surface; forming a middle-of-line (MEOL) structure on the first surface of the substrate; the MEOL structure including a capacitor comprising a base plate and a top plate located on the base plate; and forming a plurality of first through-paths in the substrate and contacting the base plate. Attached Figure Description

[0007] The various embodiments disclosed herein can be best understood by reading the following description and the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of some features may be intentionally enlarged or reduced for clarity of description.

[0008] Figure 1A A cross-sectional view of a semiconductor structure according to some comparative examples of the present disclosure is shown.

[0009] Figure 1B A cross-sectional view of a capacitor structure according to some comparative examples of the present disclosure is shown.

[0010] Figure 1C A top view of a capacitor is shown, representing some comparative examples according to this disclosure.

[0011] Figure 2 A cross-sectional view of a capacitor structure according to some embodiments of the present disclosure is shown.

[0012] Figure 3 A cross-sectional view of a capacitor structure according to some embodiments of the present disclosure is shown.

[0013] Figure 4 A cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0014] Figure 5 A cross-sectional view of a capacitor structure according to some embodiments of the present disclosure is shown.

[0015] Figure 6 A cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0016] Figure 7 A cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0017] Figure 8 A cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0018] Figure 9AA cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0019] Figure 9B A cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0020] Figure 10A and 10B A cross-sectional view of a capacitor structure formed according to some embodiments of the present disclosure is shown.

[0021] Figures 11A to 11D A cross-sectional view of a capacitor structure formed according to some embodiments of the present disclosure is shown.

[0022] Figures 12A to 12C A cross-sectional view of a capacitor structure formed according to some embodiments of the present disclosure is shown.

[0023] Figures 13A to 13E A cross-sectional view of a capacitor structure formed according to some embodiments of the present disclosure is shown. Detailed Implementation

[0024] This application claims priority to U.S. Provisional Application No. 63 / 209,923, filed June 11, 2021, and U.S. Provisional Application No. 63 / 283,112, filed November 24, 2021, the entire contents of which are incorporated herein by reference.

[0025] This application is a partial continuation of U.S. Patent Application No. 17 / 511,190, filed October 26, 2021, which is a partial continuation of U.S. Patent Application No. 16 / 609,159, filed October 28, 2019, which is the national phase of International Application PCT / JP2017 / 016977, filed April 28, 2017, all of which are incorporated herein by reference in their entirety.

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and configurations are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the first member being formed above or on the second member may include embodiments where the first and second members are in direct contact, and may also include embodiments where an additional member is formed between the first and second members, so that the first and second members are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of the invention disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "above," and similar terms may be used herein to describe the relationship of one element or component to another element(s), as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and these can also be used accordingly to explain the spatial relative descriptors used herein.

[0028] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, and these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another. When terms such as "first," "second," and "third" are used in the text, it does not imply order or sequence unless explicitly indicated by the context.

[0029] Figure 1A A comparative example is illustrated, wherein the semiconductor structure 90 includes a capacitor structure 91 bonded to a semiconductor wafer 92. The semiconductor wafer 92 may be a logic SOC, and the capacitor structure 91 bonded to it can be used to reduce power supply fluctuations. For example, IC power consumption may be as high as 100 W / cm² in high-performance computing. 2 Around this point, a large number of decoupling capacitors are needed to reduce the effective series resistance (ESR) and equivalent series inductance (ESL). Ideally, the capacitors should be infinitely large (i.e., as large as possible) while the ESR and ESL should be zero (i.e., as small as possible).

[0030] exist Figure 1A and 1B In one comparative example shown, capacitor structure 91 includes a capacitor 910, such as a metal-insulator-metal (MIM) capacitor or... Figure 1BThe diagram shows a metal-oxide-metal (MOM) capacitor. The capacitor structure 91 is electrically connected to a semiconductor wafer 92 via a plurality of microbumps 93 located on one side of the capacitor structure 91. Since the capacitor structure 91 is bonded to a surface of the semiconductor wafer 92, a portion of the surface of the semiconductor wafer 92 facing a packaging substrate 94 is thus covered or shielded by the capacitor structure 91. Therefore, the semiconductor wafer 92 is packaged onto the packaging substrate 94 via a plurality of conductive bumps 95 laterally adjacent to the capacitor structure 91. In some embodiments, the conductive bumps 95 may be C4 bumps. Figure 1A As shown, the capacitor structure 91 is not directly connected to the package substrate 94. Instead, conductive bumps 95 are formed to make contact with the VSS pad 941 and VDD pad 942 of the package substrate 94 to electrically connect the semiconductor wafer 92 and the package substrate 94. In other words, there is no direct conductive connection between the capacitor structure 91 and the package substrate 94. Therefore, in this comparative example, the power and signal transmission of the semiconductor wafer 92 must pass through the conductive bumps 95 adjacent to the capacitor structure 91.

[0031] Reference Figure 1C The illustrated top view of a capacitor 910 in a capacitor structure 91 bonded to a semiconductor wafer 92 shows that, in this comparative example, the capacitor 910 includes connection terminals located on both sides thereof, for example, forming a top capacitor metal 911 and a bottom capacitor metal 912 electrically connected to the semiconductor wafer 92. In this embodiment, the area of ​​the bottom capacitor metal 912 is larger than the area of ​​the top capacitor metal 911, and the bottom capacitor metal 912 has an uncovered area 912A that is not covered by the top capacitor metal 911. Therefore, conductive channels 96 located between the semiconductor wafer 92 and the capacitor structure 91 can be formed on the entire area of ​​the top capacitor metal 911 and on the peripheral area of ​​the bottom capacitor metal 912 (i.e., the uncovered area 912A). This means that the number of conductive channels 96 (e.g., conductive channels 962) falling on the uncovered area 912A of the bottom capacitor metal 912 is generally much smaller than the number of conductive channels 96 (e.g., conductive channels 961) falling on the top surface of the top capacitor metal 911. Therefore, the area limitation of the uncovered region 912A is a bottleneck condition for reducing the base plate resistance of the bottom capacitor metal 912.

[0032] In some embodiments, the bottom capacitor metal 912 further includes one or more series regions 912B for connecting other capacitors 910. These series regions 912B are part of the uncovered region 912A, but these regions are left to form a structure for series connection.

[0033] Reference Figure 2In some embodiments of this disclosure, a capacitor structure 10 with improved base plate resistance is provided. In this embodiment, the capacitor structure 10 includes a substrate 100, a middle-of-line (MEOL) structure 102, and a back-end-of-line (BEOL) structure 104. The substrate 100 has a first surface 100A and a second surface 100B opposite to the first surface 100A. In some embodiments, the substrate 100 is made of a semiconductor material, such as silicon, germanium, diamond, or similar materials. Alternatively, composite materials may be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and similar materials. In some embodiments, the substrate 100 is made of glass.

[0034] MEOL structure 102 is the wiring portion of capacitor structure 10, formed before BEOL structure 104 (i.e., metallized structure) is formed. Definitions of what constitutes a MEOL vary, but in the embodiments disclosed herein, MEOL structure 102 refers to the structure formed on the first surface 100A of substrate 100 up to the first metal layer (M1) 1041 of BEOL structure 104. For simplicity, the upper metal layer above the first metal layer 1041 in BEOL structure 104 is not shown in the illustrations of this disclosure. In some embodiments, MEOL structure 102 is composed of a dielectric material, which may be referred to as a pre-metal dielectric (PMD). In other words, MEOL structure 102 and the substrate 100 beneath it and the BEOL structure above it can be distinguished by various process parameters, such as the choice of base material or the choice of metal used. For example, the material of MEOL structure 102 can be a low-k dielectric material with a smaller dielectric constant compared to silicon dioxide, thus distinguishing it from the material of substrate 100; similarly, tungsten is commonly used for electrical connections in MEOL structure 102, while copper is commonly used in BEOL structure 104. The above are exemplary methods for distinguishing the stacked layer structures in a capacitor structure, but this embodiment is not limited thereto.

[0035] Reference Figure 2 In some embodiments, a capacitor 106 is embedded in a MEOL structure 102. In some embodiments, the capacitor 106 may be a 3D metal-insulator, and this out-of-plane dimension can be used to advantageously increase the effective MIM area and associated capacitance density. In some embodiments, the capacitor 106 described herein may have a very high density, for example, a capacitor density greater than about 1 μF / mm².2 In some embodiments, the 3D capacitor may be cylindrical.

[0036] like Figure 2 As shown, in some embodiments, the capacitor 106 includes a base plate 108, a top plate 110 located on the base plate 108, and a plurality of capacitor cells 112 formed between the base plate 108 and the top plate 110. In some embodiments, the distance between the base plate 108 and the top plate 110 is between about 1 μm and about 2 μm.

[0037] In some embodiments, the base plate 108 and the top plate 110 are formed at different depths of the MEOL structure 102 and are arranged in parallel. In some embodiments, because the base plate 108 is formed at a first surface 100A adjacent to the substrate 100, the distance between the base plate 108 and the substrate 100 is smaller than the distance between the top plate 110 and the substrate 100. In some embodiments, viewed from above, the planar area of ​​the base plate 108 is larger than the planar area of ​​the top plate 110, and therefore, as referred to above... Figure 1B and 1C As shown in the comparative example, the peripheral area of ​​the base plate 108, or the uncovered area 108A, is not covered by the top plate 110.

[0038] In order to electrically connect capacitor 106 to other semiconductor structures or semiconductor devices, in some embodiments of this disclosure, the upper and lower sides of capacitor 106 are in contact with a plurality of conductive contacts or channels to provide electrical connection on the top surface 102A of MEOL structure 102 and the second surface 100B of substrate 100. In other words, the conductive contacts or channels used to connect to capacitor 106 of this disclosure can be formed above and below capacitor 106, which means that the space below capacitor 106 can be used efficiently.

[0039] Similarly, refer to Figure 2 The capacitor structure 10 may include a plurality of first metal contacts 114 and a plurality of second metal contacts 116 located on the capacitor 106. The first metal contacts 114 rest directly on the top surface of the top plate 110, and the second metal contacts 116 rest directly on the uncovered area 108A of the bottom plate 108 not covered by the top plate 110. In this embodiment, the vertical lengths of the first metal contacts 114 and the second metal contacts 116 are different.

[0040] Reference Figure 3In some embodiments, to reduce placement failures or incorrect offsets of the first and second metal contacts 114, 116, the MEOL structure 102 may include a first capacitor electrode structure 118 in contact with the top surface of the top plate 110, and a second capacitor electrode structure 120 in contact with the uncovered area 108A of the bottom plate 108. In some embodiments, the first capacitor electrode structure 118 and the second capacitor electrode structure 120 may provide a coplanar contact surface 122 on the capacitor 106 (see...). Figure 2 (The dotted lines shown) are used to accommodate the contacts of the first and second metal contacts 114 and 116. That is, in this embodiment, the vertical lengths of the first metal contact 114 and the second metal contact 116 are substantially equal. In some embodiments, the first capacitor electrode structure 118 or the second capacitor electrode structure 120 each includes a combination of a capacitor contact and a capacitor pad. In some embodiments, the height of the second capacitor electrode structure 120 is greater than the height of the first capacitor electrode structure 118.

[0041] like Figure 2 and Figure 3 As shown, in some embodiments, the capacitor structure 10 further includes a plurality of first through-paths 124 extending from the second surface 100B of the substrate 100 to the base plate 108. These first through-paths 124, which may be referred to as back-side silicon vias (TSVs), are formed under the capacitor 106 and can be used to improve the resistance of the base plate 108 of the capacitor 106. That is, because most of the area of ​​the base plate 108 is already covered by the capacitor cells 112 and the top plate 110 in the MEOL structure 102, this disclosure uses the back side of the base plate 108 (i.e., the side adjacent to the substrate 100) to increase the area that can be coupled with conductive channels or contacts, and thus reduce the resistance of the base plate 108.

[0042] like Figure 2 and Figure 3 As shown, the first through-path 124 is a silicon via penetrating the substrate 100. In the case where the substrate 100 is composed of a semiconductor material, an oxide substrate made of a dielectric material (e.g., an oxide material) can be formed (hereinafter referred to as...). Figure 11C (As shown) the first through-pass 124 is laterally surrounded to prevent leakage current from the substrate 100. In other cases, the substrate 100 is made of a non-conductive material such as glass, the first through-pass 124 can directly contact the substrate 100, and the formation of an oxide liner can be omitted.

[0043] Reference Figure 4In some embodiments, one end of each first through-pass 124 contacts the bottom of the capacitor 106 (i.e., the bottom surface of the base plate 108), while the other end of each first through-pass 124 is exposed through the second surface 100B of the substrate 100 of the capacitor structure 10 for electrical connection. Details of the capacitor 106 can be found in the description. Figure 2 and Figure 3 As illustrated in the embodiments. In some embodiments, the capacitor structure 10 is bonded to a semiconductor device 20 (e.g., a logic SOC, logic die, logic chip, or similar) via microbumps or other bonding techniques (e.g., hybrid bonding structures). The bonding structure can be further bonded to a package substrate 30 or an interposer by directly connecting the first through-path 124 to a plurality of conductive terminals 126. In some embodiments, the conductive terminals 126 may comprise microbumps, C4 bumps, solder balls, or similar.

[0044] Furthermore, in some embodiments, the conductive bumps 128 may be formed between the semiconductor device 20 and the package substrate 30 to directly connect the semiconductor device 20 and the package substrate 30. In some embodiments, the conductive bumps 128 may be C4 bumps. In some embodiments, the conductive bumps 128 may be used to contact the VSS pads 31 and VDD pads 32 of the package substrate 30.

[0045] Reference Figure 5 In some embodiments, a feedthrough connection structure 130 may be formed in the substrate 100 of the MEOL structure 102 and the capacitor structure 10. As shown, the feedthrough connection structure 130 is adjacent to the capacitor 106 and the first and second metal contacts 114, 116 and the first through-path 124 connected thereto. The feedthrough connection structure 130 can be used to provide a short path for electrical connection between the semiconductor device 20 and the portion located directly below the capacitor structure 10. In some embodiments, the feedthrough connection structure 130 includes a relay metal 132 flush with the base plate 108. The relay metal 132 may serve as a placement base for one or more third metal contacts 134 formed thereon. In this embodiment, the length of each second metal contact 116 is equal to the length of the third metal contact 134. In some embodiments, the feedthrough connection structure 130 includes one or more second through-paths 124a extending from the relay metal 132 to the second surface 100B of the substrate 100.

[0046] Figure 6 This is a cross-sectional view of a semiconductor structure in which the capacitor structure 10 is bonded between the semiconductor device 20 and the package substrate 30, according to some embodiments of this disclosure. Figure 5 Details of capacitor structure 10 shown and Figure 6The bonding structure shown has an upper end of the feedthrough connection structure 130 that can contact the first metal layer 1041 of the BEOL structure 104, and a lower end of the feedthrough connection structure 130 exposed to the second surface 100B of the substrate 100 to contact the conductive terminal 126 between the capacitor structure 10 and the package substrate 30.

[0047] like Figure 5 and Figure 6 In the illustrated embodiment, the VSS pad 31 and VDD pad 32 of the package substrate 30 can be directly arranged below the capacitor structure 10. For example, the VDD pad 32 can be directly arranged below the feedthrough connection structure 130 and electrically connected to the feedthrough connection structure 130 through one or more conductive terminals 126 therebetween; while the VSS pad 31 can be directly arranged below the capacitor 106 and electrically connected to it through one or more conductive terminals 126 therebetween. Therefore, by using the feedthrough connection structure 130, power can be supplied to the capacitor structure 10 and the semiconductor device 20 through the VSS pad 31 and VDD pad 32 located directly below, which means that the previous Figure 4 Some of the conductive bumps 128 are shown. When conductive bumps are not formed laterally around the capacitor structure 10, the semiconductor device 20 may have more area available for bonding to more capacitor structures 10, and thus the density and number of capacitors can be increased. In some alternative embodiments, the conductive bumps 128 may be formed between the capacitor structure 10 and the package substrate 30, that is, the connection technology applicable to the back side (i.e., the second surface 100B) of the capacitor structure 10 can have various styles.

[0048] In some alternative embodiments, reference is made to Figure 7 A redistribution layer can be formed on the second surface 100B of the substrate 100. For example, a first redistribution layer 136 can be formed to contact the first through-path 124 located below the capacitor 106, and a second redistribution layer 138 can be formed to contact the second through-path 124a of the feedthrough connection structure 130. Furthermore, a conductive bump 140 (e.g., a C4 bump, solder ball, or similar) can be used to connect the first redistribution layer 136 and the VSS pad 31. Similarly, another conductive bump 140 can be used to connect the second redistribution layer 138 and the VDD pad 32.

[0049] In some embodiments, a plurality of capacitor structures may be bonded between the semiconductor device 20 and the packaging substrate 30. (Refer to...) Figure 8A first capacitor structure 10a and a second capacitor structure 10b are arranged and bonded between the semiconductor device 20 and the packaging substrate 30. The first capacitor structure 10a and the second capacitor structure 10b can be capacitor microchip structures cut from a capacitor wafer having a plurality of capacitor microchip structures. In some embodiments, it is not necessary to cut the capacitor structures 10a and 10b from the capacitor wafer, because they can be bonded between the semiconductor device 20 and the packaging substrate 30 as a single device.

[0050] exist Figure 8 In the illustrated embodiment, the pads of the package substrate 30 can be designed to interact with the capacitor wafer structure bonded thereto. As shown, VSS pads 31 can be arranged to be electrically connected to capacitor 106 through conductive structures located therebetween, while VDD pads 32 located under the first capacitor structure 10a are electrically connected to feedthrough connection structure 130. Unlike the first capacitor structure 10a, the pads 34 of the package substrate 30 adjacent to the feedthrough connection structure 130 in the second capacitor structure 10b are pads for signal transmission. That is, by forming TSVs (e.g., first through-path 124 and / or feedthrough connection structure 130) on the back side of capacitor structures 10a, 10b, these conductive paths can serve as a power rail or provide signal connections to / from semiconductor device 20 (e.g., logic SOC). In this embodiment, the first redistribution layer 136 is insulated from the second redistribution layer 138, and the electrical path including the second redistribution layer 138 can have the shortest distance between the semiconductor device 20 and the package substrate 30. This enables a high-speed, high-bandwidth, and low-resistance connection between the semiconductor device 20 and the package substrate 30. In other words, the feedthrough connection structure 130 in the first capacitor structure 10a, for example, is insulated from the capacitor 106 in the first capacitor structure 10a, so that signals or power do not pass through the capacitor 106 in the first capacitor structure 10a.

[0051] Therefore, based on these conductive paths, circuit designs for electrical connections between capacitor wafer structures, semiconductor devices, and / or packaging substrates can be more flexible. For example, when the feedthrough connection structure 130 in capacitor structures 10a and 10b is used as a power rail or a signal line, respectively, the semiconductor device 20 can be separated from the conductive bumps laterally adjacent to the capacitor structures 10a and 10b (e.g., as described above). Figure 4 The conductive bump 128 shown is a contact. Furthermore, because the length of the conductive path can be reduced, the delay and power consumption of the semiconductor device can also be improved.

[0052] Reference Figure 9A and Figure 9BIn some embodiments, the feedthrough connection structure in the capacitor structure 10 is formed as a uniform structure. For example, the feedthrough connection structure consists of a feedthrough path 142 of a layer 1041, which extends from the second surface 100B of the substrate 100 to the first metal layer 1041 of the BEOL structure 104. Generally, due to the manufacturing method, the first through-path 124 and the feedthrough path 142 have a tapered profile in cross-section. By utilizing different methods to form the feedthrough path 142, a narrow end of the feedthrough path 142 can be adjacent to the second surface 100B of the substrate 100 (see reference). Figure 9A (as shown in the embodiment) or the first metal layer 1041 adjacent to the BEOL structure 104 (refer to) Figure 9B (Example shown).

[0053] In summary, the embodiments of the capacitor structures described in this disclosure include a plurality of electrical connections on one side of the substrate. These electrical connections provide additional electrical paths to the base plate of the capacitor in each capacitor structure. Due to the coverage of the metal top plate, the number of metal contacts that can fall on the upper side of the metal base plate is significantly reduced, and therefore, in the embodiments of this disclosure, a plurality of back-side TSVs penetrating the capacitor structure substrate are used to contact the lower side of the base plate of the capacitor. Therefore, the resistance of the base plate of the capacitor in each capacitor structure can be managed and adjusted by adding these back-side TSVs. In other words, in this disclosure, the resistance of the base plate of the capacitor in the capacitor structure is reduced by implementing these back-side TSVs, and these back-side TSVs can also change the power supply path of the capacitor and / or the semiconductor device bonded to the capacitor. Furthermore, additional feedthrough connections can be provided based on the technique of forming the back-side TSVs. As a result, the electrical performance of the semiconductor device can be improved due to the reduction in latency and power consumption, while the capacitor density and bandwidth are increased.

[0054] In manufacturing as described above Figure 5 When the capacitor structure 10 is shown, especially in the operation of forming the back-side TSV (i.e., the first through-path 124) extending from the back side of the capacitor structure 10 (i.e., the second surface 100B of the substrate 100), please refer to Figure 10A and 10B .like Figure 10AAs shown, a substrate 100 made of semiconductor material or glass can be received, and a first surface 100A of the substrate 100 is covered by a MEOL structure 102 formed thereon. Before forming a capacitor in the MEOL structure 102, a plurality of first through-paths 124 are pre-formed in the substrate 100. Since initially the thickness of the substrate 100 is much greater than the length of the first through-paths 124, the bottom end of each first through-path 124 is embedded within the substrate 100. The top end of each first through-path 124 contacts a base plate 108 of the capacitor 106. When a feedthrough connection structure 130 is formed in the capacitor structure 10, particularly in the feedthrough region 60 of the substrate 100, a second through-path 124a is formed in the substrate 100, and during the formation of the MEOL structure 102, a relay metal 132 is formed on the second through-path 124a. Therefore, one end of the second through-path 124a contacts the relay metal 132. The relay metal 132 is flush with the base plate 108 of the capacitor 106.

[0055] Furthermore, a plurality of first metal contacts 114 and a plurality of second contacts 116 are formed on the capacitor 106. In some embodiments, a plurality of third metal contacts 134 are formed on the relay metal 132 and flush with the capacitor cell 112. In some embodiments, a first metal layer (M1) 1041 of the BEOL structure 104 is formed on the capacitor 106 and the third metal contacts 134. In some embodiments, Figure 10A The substrate 100 shown is part of a wafer, and the MEOL structure 102 and BEOL structure 104 are layer structures formed on the wafer. The wafer can be diced in subsequent processes to obtain a plurality of capacitor structures 10.

[0056] Reference Figure 10B After receiving the substrate 100 on which the MEOL structure 102 and BEOL structure 104 are formed, a back-side thinning process can be performed to expose the bottom end of each first through-passage 124. For example, the bottom end of the first through-passage 124 can be exposed by polishing or grinding from the second surface 100B of the substrate 100. Figure 10A and 10B In the method shown, since the first through-pass 124 is pre-formed in the substrate 100, the method used to form the back-side TSV can be called the through-pass mid-process.

[0057] After the capacitor structure 10 has been fabricated, the semiconductor device 20 can be bonded to the BEOL structure of the capacitor structure 10. The substrate 100 of the capacitor structure 10 and the semiconductor device 20 can be mounted on the packaging substrate 30 through a plurality of conductive terminals 126 or conductive bumps 140 located between the first through-paths 124, the second through-paths 124a and a packaging substrate 30. The bonded semiconductor structure can be referred to above. Figure 6 or Figure 7 The example shown.

[0058] As mentioned above Figure 7 In some embodiments of the structure shown, before the substrate 100 of the capacitor structure 10 is mounted onto the package substrate 30, a first redistribution layer 136 may be formed in the capacitor region 62 of the substrate 100 on the second surface 100B of the substrate 100 (see [link to documentation]). Figure 10A The second redistribution layer 138 can be formed in the feedthrough region 60 of the substrate 100 on the second surface 100B of the substrate 100 (see [reference]). Figure 10A The first redistribution layer 136 is insulated from the second redistribution layer 138.

[0059] Unlike Figure 10A and 10B In other embodiments, the back-side TSV can be fabricated after capacitor 106 is formed. (See reference...) Figures 11A to 11D The post-drilling process shown can receive a substrate 100 made of semiconductor material or glass, and the first surface 100A of the substrate 100 is covered by a MEOL structure 102 and a first metal layer (M1) 1041 of a BEOL structure 104 formed thereon, wherein there are no first through-paths 124 inside the substrate 100. (Refer to...) Figure 11A (With the capacitor structure 10 inverted for illustration), a photoresist layer 40 can be formed on the second surface 100B of the substrate 100, and then the photoresist layer 40 is patterned to form the first through-path 124. Next, refer to... Figure 11B A plurality of trenches 500 can be formed on the second surface 100B of the substrate 100 via a via etching operation to form the first through-path 124. If the thickness of the substrate 100 is not suitable for the via etching operation, the substrate 100 can be thinned beforehand. The spacing between the trenches 500 used to form the first through-path 124 can be tens of micrometers or tens of micrometers. Generally, the density and critical size of the first through-path 124 can be determined by the capabilities of the semiconductor process. On the other hand, since the TSV aspect ratio is related to the via etching technology, generally speaking, the thinner the substrate 100, the narrower the trenches 500 formed to form the first through-path 124 can be, and thus the array of the first through-path 124 formed has a higher density.

[0060] After the via etching operation, a via filling operation can be performed subsequently. For example... Figure 11D As shown, a plurality of first through-passages 124 can be formed by filling the trench 500 with metal. In some embodiments, such as Figure 11C As shown, an oxide liner 502 can be formed on the inner surface of each trench 500 before the via filling operation. The oxide liner 502 is used to prevent leakage current in the substrate 100. When the bottom of the trench 500 is covered by the oxide liner 502, an additional etching operation can be performed to clean the area used for electrical connections. When the substrate 100 is made of a non-conductive material such as glass, the via filling operation can be performed directly without forming an oxide liner. Furthermore, after the via filling operation, a chemical mechanical polishing (CMP) operation can be performed on the second surface 100B of the substrate 100 to form a flat surface, and then electrical connections can be formed thereon.

[0061] In embodiments where the received substrate 100 does not include the third metal contact 134 flush with the capacitor cell 112 and the relay metal 132, a feedthrough connection structure can be formed in a separate process, which consists of a feedthrough path 142 extending from the second surface 100B of the substrate 100 to the first metal layer 1041 of the BEOL structure 104. Figures 12A to 12C As shown (with the capacitor structure 10 inverted for illustration), a photoresist layer 42 can be formed on the second surface 100B of the substrate 100, and then the photoresist layer 42 is patterned to form a feedthrough path 142 in the feedthrough region 60 of the substrate 100. The feedthrough region 60 is different from... Figure 12A The capacitor region 62 of the substrate 100 shown. Next, as... Figure 12B As shown, trench 504 is formed through a via etching operation, and trench 504 penetrates the substrate 100 and extends toward the MEOL structure 102. The trench 504 is positioned to bypass the capacitor 106, so that the subsequently formed through-path will not overlap with the capacitor 106. Trench 504 can then be filled through a via filling operation. Figure 12C As shown, depending on the material of the substrate 100, an oxide liner 502 may be formed prior to the via filling operation.

[0062] In other embodiments, the feedthrough path 142 can be formed from the front side of the capacitor structure 10. For example, refer to... Figures 13A to 13E A photoresist layer 44 can be formed above the first metal layer (M1) 1041 of the BEOL structure, and the photoresist layer 44 can be patterned to form a feedthrough path 142. (Refer to...) Figure 13B A trench 506 is formed by performing a path etching operation, wherein the trench 506 can penetrate the first metal layer 1041 and the MEOL structure 102, and the bottom of the trench 506 stops in the substrate 100. Then, as... Figure 13C and 13D As shown, trench 506 can then be filled by a pathway filling operation, and if necessary, an oxide liner 502 can be formed prior to the pathway filling operation for lateral insulation. Subsequently, as... Figure 13E As shown, the wafer can be flipped and a back-side thinning operation can be performed from the second surface 100B of the substrate 100 to thin the substrate 100, thereby exposing the bottom of the feedthrough 142 accordingly.

[0063] In short, according to the above embodiments, the capacitor structure disclosed herein includes a back-side TSV connected to the capacitor substrate. These back-side TSVs can provide an additional electrical path for power supply to the capacitor, thereby reducing the resistance of its substrate. Furthermore, back-side TSV technology can be used to provide feedthrough TSVs that are not directly connected to the capacitor terminals, and feedthrough TSVs can be performed to power or transmit signals to semiconductor devices bonded to the capacitor. In this way, not only are the capacitor parameters optimized, but the electrical performance of the semiconductor device can also be improved by reducing delay and power consumption.

[0064] The foregoing outlines the structure of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described in this disclosure. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

[0065] [Symbol Explanation]

[0066] 10: Capacitor Structure

[0067] 10a: First capacitor structure

[0068] 10b: Second capacitor structure

[0069] 100:Substrate

[0070] 100A: First surface

[0071] 100B: Second Surface

[0072] 102: Mid-Range Process (MEOL) Structure

[0073] 102A: Top surface

[0074] 104: Back-end process (BEOL) structure

[0075] 1041: First metal layer (M1)

[0076] 106: Capacitor

[0077] 108: Base Plate

[0078] 108A: Covered Area

[0079] 110: Top plate

[0080] 112: Single capacitor unit

[0081] 114: First metal contact

[0082] 116: Second metal contact

[0083] 118: First capacitor electrode structure

[0084] 120: Second capacitor electrode structure

[0085] 122: Coplanar contact surfaces

[0086] 124: First penetrating pathway

[0087] 124a: Second penetrating pathway

[0088] 126: Conductive terminal

[0089] 128: Conductive bump

[0090] 130: Feedthrough connection structure

[0091] 132: Relay Metal

[0092] 134: Third metal contact

[0093] 136: First redistribution layer

[0094] 138: Second redistribution layer

[0095] 140: Conductive bump

[0096] 142: Feedthrough Path

[0097] 20: Semiconductor devices

[0098] 30: Packaging substrate

[0099] 31: VSS gasket

[0100] 32: VDD gasket

[0101] 40: Photoresist layer

[0102] 42: Photoresist layer

[0103] 500: Trench

[0104] 502: Oxide Liner

[0105] 504: Trench

[0106] 506: Trench

[0107] 60: Feedthrough area

[0108] 62: Capacitor Region

[0109] 90: Semiconductor Structure

[0110] 91: Capacitor Structure

[0111] 910: Capacitor

[0112] 911: Top capacitor metal

[0113] 912: Bottom capacitor metal

[0114] 912A: Covered Area

[0115] 912B: Series Region

[0116] 92: Semiconductor wafers

[0117] 93: Microbumps

[0118] 94: Packaging substrate

[0119] 941:VSS gasket

[0120] 942: VDD gasket

[0121] 95: Conductive bump

[0122] 96: Conductive Channel

[0123] 961: Conductive Channel

[0124] 962: Conductive Channel

Claims

1. A capacitor structure comprising: A substrate having a first surface and a second surface opposite to the first surface, the substrate being a semiconductor substrate or a glass substrate; A middle-of-line (MEOL) structure is located on the first surface of the substrate. A capacitor is embedded in the MEOL structure, and the capacitor includes a base plate and a top plate extending continuously on the base plate. The capacitor also includes a plurality of capacitor cells formed between the base plate and the top plate and shared by the base plate and the top plate. The MEOL structure includes a dielectric material with a dielectric constant lower than that of silicon dioxide. A metallized structure is located on the MEOL structure; The substrate further includes a plurality of first through-paths extending from the second surface of the substrate to the base plate.

2. The capacitor structure as described in claim 1, wherein the MEOL structure further comprises: A plurality of first metal contacts extending from the top plate of the capacitor to the metallized structure; and A plurality of second metal contacts extend from the base plate of the capacitor to the metallized structure; The plurality of first metal contacts and the plurality of second metal contacts are in contact with a first metal layer (M1) of the metallized structure.

3. The capacitor structure as described in claim 1, wherein the MEOL structure further comprises: A relay metal, flush with the base plate; and Multiple third metal contacts extend from the relay metal to the metallized structure.

4. The capacitor structure of claim 3, wherein the substrate further includes a second through-path extending from the second surface of the substrate to the relay metal.

5. The capacitor structure of claim 1 further includes a feedthrough connection structure extending from the second surface of the substrate to the metallized structure.

6. The capacitor structure of claim 1 further includes a redistribution layer located on the second surface and in contact with the plurality of first through-paths.

7. The capacitor structure of claim 1, wherein each of the plurality of first through-paths includes a narrow end adjacent to the second surface of the substrate.

8. The capacitor structure of claim 1, wherein each of the plurality of first through-paths includes a narrow end adjacent to the base plate of the capacitor.

9. A semiconductor structure comprising: One packaging substrate; A first capacitor structure is bonded to the package substrate, wherein the first capacitor structure comprises: A substrate, which may be a semiconductor substrate or a glass substrate; A middle-of-line (MEOL) structure is located on the substrate, a capacitor is embedded in the MEOL structure, and the MEOL structure includes a dielectric material with a dielectric constant lower than that of silicon dioxide; and A plurality of first through-paths, the plurality of first through-paths penetrating the substrate, such that the packaging substrate is electrically connected to the capacitor of the first capacitor structure through the plurality of first through-paths; and A semiconductor device is bonded to the first capacitor structure; in, The capacitor contains: One base plate, A continuously extending top plate, which sits on the bottom plate, and A plurality of capacitor cells are formed between the base plate and the top plate, and are used together on the base plate and the top plate.

10. The semiconductor structure of claim 9, wherein a planar region of the top plate is smaller in a top-view angle than a planar region of the bottom plate.

11. The semiconductor structure of claim 9, wherein the first capacitor structure further comprises a first feedthrough connection structure adjacent to the capacitor and the first through-path.

12. The semiconductor structure of claim 11, wherein the first feedthrough connection structure comprises: A relay metal, flush with the base plate; A second through-path extends from the relay metal to a surface of the substrate; and A plurality of metal contacts are provided on the relay metal.

13. The semiconductor structure of claim 12, wherein a length of the second through-path is equal to a length of the plurality of first through-paths.

14. The semiconductor structure of claim 12, wherein the first feedthrough connection structure is insulated from the capacitor in the first capacitor structure.

15. The semiconductor structure of claim 9, wherein each of the plurality of first through-paths is laterally surrounded by an oxide liner.

16. A method for fabricating a semiconductor structure, the method comprising: A substrate is provided having a first surface and a second surface opposite to the first surface, the substrate being a semiconductor substrate or a glass substrate; A middle-of-line (MEOL) structure is formed on the first surface of the substrate. A capacitor is embedded in the MEOL structure, and the capacitor includes a base plate and a top plate extending continuously from the base plate. The capacitor also includes a plurality of capacitor cells formed between the base plate and the top plate and shared by the base plate and the top plate. The MEOL structure includes a dielectric material with a dielectric constant lower than that of silicon dioxide. A plurality of first through-paths are formed in the substrate and in contact with the base plate of the capacitor.

17. The method of claim 16, wherein the plurality of first through-passages are formed in the substrate before the MEOL structure is formed on the first surface of the substrate, and a first end of each of the plurality of first through-passages is embedded in the substrate, and a second end of each of the plurality of first through-passages is exposed from a first surface of the substrate.

18. The method of claim 17, wherein the base plate of the capacitor is in contact with the second end of each of the plurality of first through-paths, and the method further comprises: The substrate is thinned by the second surface of the substrate so that the first end of each of the plurality of first through-passes is exposed.

19. The method of claim 16, further comprising: A second through-path is formed in a feedthrough region of the substrate; and During the formation of the MEOL structure, a relay metal is formed in the second through-path, wherein the relay metal is flush with the base plate of the capacitor.

20. The method of claim 19, wherein the plurality of first through-paths are formed in the substrate after the relay metal is formed, and the plurality of first through-paths are formed by performing via etching and via filling operations on the second surface of the substrate.

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