Delay circuits and circuit systems

Abstract

A delay circuit and circuit system are disclosed, wherein the delay circuit includes a voltage-to-current conversion unit, a capacitor, and an output logic unit. The voltage-to-current conversion unit receives an input signal and generates a current based on the voltage level of the input signal, wherein the current is proportional to the voltage level of the input signal. The capacitor is electrically connected to the voltage-to-current conversion unit and receives the current generated by the voltage-to-current conversion unit for charging. The output logic unit is electrically connected to the capacitor, receives a voltage signal at one end of the capacitor, and generates an output signal based on the voltage signal, wherein the delay time between the transition point of the input signal and the transition point of the output signal is independent of the voltage level of the input signal. This invention provides a delay circuit whose delay time is unaffected by changes in the voltage level of the input signal. Its architecture is simple, eliminating the need for large-area and power-consuming comparators and various bias circuits.

Description

Technical Field

[0001] The invention relates to a delay circuit, and more particularly to a delay circuit whose delay time is not affected by input voltage variations, and a circuit system using said delay circuit. Background Technology

[0002] Delay circuits are used to delay the arrival of an output signal at a specific voltage in response to an input signal. When the input signal's voltage level is the same as the supply voltage, the delay circuit can be used as a power soft-start circuit, commonly found in automotive electronics, computers, and various electronic products. Since a delay time is required to convert the output signal to a specific voltage, the power soft-start circuit allows the connected circuits, devices, or apparatuses to receive the specific voltage output by the circuit only after the circuit has stabilized, thus preventing damage or reduced lifespan to the connected circuits, devices, or apparatuses. However, existing delay circuits have varying delay times depending on the input signal's voltage level, indicating room for improvement.

[0003] Please refer to Figure 1 , Figure 1 This is a circuit diagram of a known delay circuit. The delay circuit 1 includes a voltage source 11, a resistor R, and a capacitor C, wherein the resistor R is electrically connected between the capacitor C and the voltage source 11. The voltage source 11 provides a voltage level equal to the supply voltage V. DD The input signal is used to charge capacitor C, causing a voltage level V to be generated at one end of capacitor C. C The output signal. Figure 1 The delay time of delay circuit 1 is an RC delay time, and the specific voltage V C With supply voltage V DD The relationship between them is V C =V DD (1-e -t / RC Therefore, to make the output signal reach a specific voltage V, C The time delay is t = -RCln(1 - VC / VDD). Clearly, the delay time is related to the voltage level of the input signal (i.e., the supply voltage VDD). DD The delay time is related to the voltage level of the input signal (i.e., the voltage level of the supply voltage V), therefore the delay time will vary depending on the voltage level of the input signal (i.e., the voltage level of the supply voltage V). DD The voltage level changes accordingly.

[0004] Please refer to Figure 2 , Figure 2 This is a circuit diagram of a delay circuit using another known technique. The delay circuit 2 includes a current source 21, a capacitor C, and a comparator 22, wherein the current source 21 receives a capacitor C with a supply voltage V. DDThe input signal is electrically connected to capacitor C, and the positive and negative input terminals of comparator 22 are electrically connected to capacitor C and reference voltage V, respectively. REF Current source 21 is used to provide a fixed current I. C This charges capacitor C. The voltage across capacitor C is charged to V. REF Afterwards, the voltage level of the output signal CMP_OUT of comparator 21 will switch to the supply voltage V. DD A fixed current I is passed through. C Charging capacitor C and using comparator 22 allow the output signal CMP_OUT of delay circuit 2 after power-on to transition to the supply voltage V. DD The delay time is a fixed delay time. However, Figure 2 This approach requires a large number of circuit components, including current and voltage bias circuits, comparators, and bias circuits for quiescent current, which leads to technical problems of large circuit area and high power consumption. Summary of the Invention

[0005] According to the purpose of this invention, an embodiment of the invention provides a delay circuit, which includes a voltage / current conversion unit, a capacitor, and an output logic unit. The voltage / current conversion unit receives an input signal and generates a current based on the voltage level of the input signal, wherein the current is proportional to the voltage level of the input signal. The capacitor is electrically connected to the voltage / current conversion unit and receives the current generated by the voltage / current conversion unit for charging. The output logic unit is electrically connected to the capacitor, receives a voltage signal at one end of the capacitor, and generates an output signal based on the voltage signal, wherein the delay time between the transition point of the input signal and the transition point of the output signal is independent of the voltage level of the input signal.

[0006] According to the above delay circuit, when the voltage level of the voltage signal is equal to half the voltage level of the input signal, the output logic unit outputs the transition output signal.

[0007] According to the above delay circuit, the output logic unit includes at least one inverter.

[0008] Based on the aforementioned delay circuit, the output logic unit consists of two inverters connected in series.

[0009] According to the above delay circuit, the input signal is the supply voltage, the output logic unit receives the operating voltage, and the operating voltage is related to the supply voltage.

[0010] According to the above delay circuit, the voltage / current conversion unit includes a transistor that forms a source attenuation resistor, wherein the gate of the transistor is electrically connected to ground voltage, the drain of the transistor is electrically connected to a capacitor, and the source attenuation resistor is electrically connected between the source of the transistor and the input signal.

[0011] Based on the aforementioned delay circuit, the transistor is a P-type MOS transistor.

[0012] According to the above delay circuit, the resistance value of the source attenuation resistor is much greater than the reciprocal of the transconductance of the small-signal model of the transistor.

[0013] According to the aforementioned delay circuit, the voltage / current conversion unit further includes a resistor, which is positioned between the source attenuation resistor and the input signal, and the resistance value of the resistor is much greater than the reciprocal of the transconductance of the small-signal model of the transistor.

[0014] According to the purpose of this invention, an embodiment of the invention provides a circuit system comprising any of the aforementioned delay circuits and a load electrically connected to the delay circuit, wherein the load is used to receive an output signal.

[0015] In summary, the embodiments of the present invention provide a delay circuit whose delay time is not affected by the voltage level variation of the input signal. Its architecture is simple and does not require large-area and power-consuming comparators and various bias circuits.

[0016] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0017] The present invention can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is a circuit diagram of a delay circuit based on a known technique.

[0019] Figure 2 This is a circuit diagram of a delay circuit using another known technique;

[0020] Figure 3 This is a circuit diagram of the delay circuit according to an embodiment of the present invention; and

[0021] Figure 4 This is a circuit diagram of a delay circuit according to another embodiment of the present invention.

[0022] Icon labels:

[0023] 1-4: Delay circuits;

[0024] 11: Voltage source;

[0025] 21: Current source;

[0026] 22: Comparator;

[0027] 31, 41: Voltage / current conversion unit;

[0028] 32, 42: Output logic units;

[0029] C: Capacitor;

[0030] CMP_OUT, D_OUT: Output signals;

[0031] IC, ID: Current;

[0032] INV1, INV2: Inverters;

[0033] MP: Transistor;

[0034] R: Resistance;

[0035] VC: Specific voltage;

[0036] VDD: Supply voltage;

[0037] VS: Voltage;

[0038] And RS: source attenuation resistor. Detailed Implementation

[0039] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same component reference numerals are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the invention.

[0040] This invention provides a delay circuit with a small chip area and low power consumption, whose delay time is unaffected by fluctuations in the voltage level of the input signal. The delay circuit does not require comparators or various bias circuits, its architecture is simple and easy to implement, and it has the advantage of relatively low manufacturing cost. The delay circuit mainly uses a voltage / current conversion unit whose generated current is proportional to the voltage level of the input signal to generate an output current to charge a capacitor. An output logic unit is used to obtain the voltage at one end of the capacitor to generate an output signal, thereby compensating for the impact of voltage level fluctuations in the input signal on the delay time, thus achieving the purpose of a delay circuit with a fixed delay time. The output logic unit is composed of at least one inverter, and preferably, an even number of inverters connected in series (e.g., two).

[0041] First, please refer to Figure 3 , Figure 3This is a circuit diagram of the delay circuit according to an embodiment of the present invention. The delay circuit 3 includes a voltage / current conversion unit 31, a capacitor C, and an output logic unit 32, wherein the voltage / current conversion unit 31 receives a voltage level equal to the supply voltage V. DD The input signal is connected to the first terminal of capacitor C, and the second terminal of capacitor C is connected to a low voltage (ground voltage). The input terminal of output logic unit 32 is connected to the first terminal of capacitor C, and the output terminal of output logic unit 32 is used to generate the output signal D_OUT. The current generated by voltage / current conversion unit 31 is proportional to the voltage level of the input signal, and the current generated by voltage / current conversion unit 31 charges capacitor C. Output logic unit 32 receives a voltage level equal to the supply voltage V. DD The input signal is used as the operating voltage, and in this embodiment, the output logic unit 32 is implemented by two inverters INV1 and INV2 connected in series. Note that the operating voltage received by the output logic unit 32 may not be equal to the supply voltage V. DD Instead, it is related to the input signal. For example, the operating voltage received by the output logic unit 32 is the buck converter supply voltage V. DD The generated operating voltage.

[0042] Generally, the transition point of inverters INV1 and INV2 (or output logic unit 32) is approximately half of the supply voltage V. DD (that is, V) DD / 2), therefore, the first terminal of capacitor C is charged to half of the supply voltage V. DD The required time is T = (C / I) × (V) DD / 2). The delay time of the delay circuit 3 is the time difference between the transition point of the input signal and the transition point of the output signal (i.e., time T plus the delay of the output logic unit 32), which charges the first end of the capacitor C to half of the supply voltage V. DD The required time is a portion of the delay time of delay circuit 3. The delay of output logic unit 32 is essentially fixed, but the time T changes with the voltage level and current of the input signal. Therefore, with the capacitance value of capacitor C fixed, as long as the current generated by voltage / current conversion unit 31 (i.e., I) and the supply voltage V are equal, the delay can be reduced. DD Proportional, time T eventually becomes a fixed value. Note that output logic unit 32 can be implemented using only one inverter, or it can be implemented using more than two inverters, and this invention is not limited thereto. The above assumes that the transition point of inverters INV1 and INV2 (or output logic unit 32) is approximately half the supply voltage V. DD This is just an example, but the invention is not limited thereto, as long as the current (i.e., I) generated by the voltage / current conversion unit 31 is equal to the supply voltage V.DD It is proportional to the voltage level of the input signal, meaning that the time T in the delay time is independent of the voltage level of the input signal (i.e., the delay time is independent of the voltage level of the input signal).

[0043] Next, please refer to Figure 4 , Figure 4 This is a circuit diagram of a delay circuit according to another embodiment of the present invention. The delay circuit 4 includes a voltage / current conversion unit 41, a capacitor C, and an output logic unit 42, wherein... Figure 4 The capacitor C and the output logic unit 42 are respectively connected to Figure 3 The capacitor C is exactly the same as that of the output logic unit 32, so it will not be described in detail. Figure 4 The voltage / current conversion unit 41 is Figure 3 This is one implementation of the voltage / current conversion unit 31, but the present invention is not limited thereto.

[0044] In this embodiment, the voltage / current conversion unit 41 includes a transistor M. P Among them, transistor M P Forming an active degeneration resistor R S Source attenuation resistor R S The first terminal receives the input signal, and the source attenuation resistor R S The second terminal is electrically connected to transistor M P The source of the transistor M P The gate electrical connection to ground voltage, and transistor M P The drain of transistor M is electrically connected to the first terminal of capacitor C. In this embodiment, transistor M... P It is a P-type MOS transistor.

[0045] In this embodiment, the source attenuation resistor R S The resistance value is much greater than that of transistor M. P Transduction of small-signal model g m When the reciprocal of (R) S >>1 / g m ), flowing through transistor M P The drain current (i.e., the current generated by the voltage / current conversion unit 41) ID = V SG / R S V SG For transistor M P The source-gate voltage difference (in this embodiment, it is voltage V) S ), and voltage V S =V DD -I D R S Therefore, I can be calculated. D =VDD / 2R S That is, current I D Proportional to the supply voltage V DD Additionally, as mentioned earlier, the transition point of inverters INV1 and INV2 (or output logic unit 32) (i.e., the input threshold voltages of inverters INV1 and INV2) is approximately half of the supply voltage V. DD (that is, V) DD / 2), therefore, the time T in the delay time of delay circuit 4 is (C / I) D )×(V DD / 2)=CR S And with the supply voltage V DD Completely irrelevant. Incidentally, if the source degeneration resistor R... S If the resistor is not large enough, in other embodiments, a large resistor can be directly connected to transistor M. P Between the source and the input signal, and the resistance of the external resistor is much greater than the transconductance g. m The reciprocal of.

[0046] In addition, embodiments of the present invention also provide a circuit system, which can be particularly a circuit system with a load that is easily damaged by receiving high voltage when not in a ready state, but the present invention is not limited thereto. The circuit system includes a delay circuit and a load of any of the foregoing embodiments and variations thereof, and the load is used to electrically connect to the output terminal of the delay circuit to receive the output signal output by the delay circuit, wherein the load can be various types of functional circuits, such as precision microelectromechanical chips, sensing instruments or automotive electronic chips, etc., and the present invention is not limited to the type of load.

[0047] In summary, the embodiments of the present invention provide a delay circuit with a small chip area and low power consumption, and its delay time is not affected by the voltage level variation of the input signal. The delay circuit does not require comparators and various bias circuits (voltage, current bias circuits, and bias circuits for quiescent current, etc.), its architecture is simple and easy to implement, and it has the advantage of relatively low manufacturing cost.

[0048] It will be understood that the above embodiments are cited by way of example only, and the invention is not limited to what has been specifically shown and described above. Instead, the scope of the invention includes combinations and sub-combinations of the various features described above, variations and modifications that would occur to those skilled in the art upon reading the foregoing description, and those not disclosed in known technologies. Documents incorporated herein by reference should be considered part of this application, and the definitions in this specification should be considered, except that the scope of any terms is defined in these incorporated documents in a manner that conflicts with the express or implied definitions in this specification.

Claims

1. A delay circuit, characterized by, The delay circuit comprises: a voltage / current conversion unit receiving an input signal and generating a current according to a voltage level of the input signal, wherein the current is proportional to the voltage level of the input signal; a capacitor electrically connected to the voltage / current conversion unit and receiving the current generated by the voltage / current conversion unit to be charged; an output logic unit electrically connected to the capacitor and receiving a voltage signal on one end of the capacitor to generate an output signal according to the voltage signal, wherein a delay time between a transition time point of the input signal and a transition time point of the output signal is irrelevant to the voltage level of the input signal; wherein the output logic unit outputs a transition output signal when a voltage level of the voltage signal is equal to half of the voltage level of the input signal; wherein the voltage / current conversion unit comprises: a transistor forming a source-degeneration resistance, wherein a gate of the transistor is electrically connected to a ground voltage, a drain of the transistor is electrically connected to the capacitor, and the source-degeneration resistance is electrically connected between a source of the transistor and the input signal; wherein a resistance value of the source-degeneration resistance is much greater than an inverse of a transconductance of a small signal model of the transistor, and the delay time is only related to a capacitance value of the capacitor and the resistance value of the source-degeneration resistance.

2. The delay circuit of claim 1, wherein, wherein the output logic unit comprises at least one inverter.

3. The delay circuit of claim 1, wherein, wherein the output logic unit is composed of an even number of inverters in series.

4. The delay circuit of claim 1, wherein, wherein the input signal is a supply voltage, and the output logic unit receives an operating voltage related to the supply voltage.

5. The delay circuit of claim 1, wherein, wherein the transistor is a P-type MOS transistor.

6. A delay circuit, characterized by, The delay circuit comprises: a voltage / current conversion unit receiving an input signal and generating a current according to a voltage level of the input signal, wherein the current is proportional to the voltage level of the input signal; a capacitor electrically connected to the voltage / current conversion unit and receiving the current generated by the voltage / current conversion unit to be charged; an output logic unit electrically connected to the capacitor and receiving a voltage signal on one end of the capacitor to generate an output signal according to the voltage signal, wherein a delay time between a transition time point of the input signal and a transition time point of the output signal is irrelevant to the voltage level of the input signal; wherein the output logic unit outputs a transition output signal when a voltage level of the voltage signal is equal to half of the voltage level of the input signal; wherein the voltage / current conversion unit comprises: a transistor forming a source-degeneration resistance, wherein a gate of the transistor is electrically connected to a ground voltage, a drain of the transistor is electrically connected to the capacitor, and the source-degeneration resistance is electrically connected between a source of the transistor and the input signal; a resistance disposed between the source-degeneration resistance and the input signal, and a resistance value of the resistance is much greater than an inverse of a transconductance of a small signal model of the transistor, and the delay time is only related to a capacitance value of the capacitor and the resistance value of the resistance.

7. Circuitry, characterized by The circuit system comprises: a delay circuit according to any one of claims 1 to 6; and a load electrically connected to the delay circuit to receive the output signal.

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