A clock signal purification and optimization device

Abstract

The present invention discloses a clock signal purification and optimization device, which includes a frequency difference or phase difference measurement unit, a signal processing unit, and a high-stability crystal oscillator unit. The frequency difference or phase difference measurement unit, the signal processing unit, and the high-stability crystal oscillator unit are connected in sequence, and the output end of the high-stability crystal oscillator unit is also connected to the output end of the frequency difference or phase difference measurement unit. Since the loop bandwidth, gain amplitude, control mode, and filtering mode of the signal processing process can all be flexibly configured in the present invention, a narrow-band phase-locked function that is not easily achieved by a conventional analog phase-locked loop can be realized, and the phase noise optimization interval of the input signal can be flexibly selected and configured. Moreover, the structure of the present invention is relatively simple, with low power consumption and high frequency tracking accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular, to a clock signal purification and optimization device. Background Art

[0002] There are various noises in radio frequency signals. Generally, the more critical ones are phase noise and short-term stability. Phase noise refers to the random change in the phase of the system output signal caused by various noises in the system (such as various radio frequency devices). It is an important indicator to measure the frequency stability quality of frequency standard sources (high-stability crystal oscillators, atomic frequency standards, etc.). With the continuous improvement of the performance of frequency standard sources, the corresponding noise values are getting smaller and smaller, so the measurement requirements for the phase noise spectrum are getting higher and higher; short-term stability refers to the degree of random change in the frequency of a signal within a short period of time.

[0003] Since phase noise and short-term stability can be converted into each other, only phase noise is used instead in the following text. In time and frequency equipment, the low-noise signal generated by an atomic clock or a high-stability crystal oscillator is often the core clock of the system, and other frequency signals are generated based on this reference.

[0004] Therefore, in the time and frequency field, there are very high requirements for the phase noise of signals. In order to meet the usage requirements of users, it is often necessary to effectively suppress and eliminate the noises introduced in the processes of signal generation, processing, and transmission. In the existing technologies, a phase-locked loop system is mainly used to optimize the phase noise of signals. However, the conventional phase-locked loop system has the disadvantages of a relatively wide phase-locked loop bandwidth and the inability to effectively remove the proximal noise. Summary of the Invention

[0005] In order to optimize the phase noise of signals (especially the phase noise of high-performance clock signals), the present invention proposes a clock signal purification and optimization device. By digitally measuring the input signal and the frequency of the controlled crystal oscillator, and performing digital operations and filtering on the numerical values, the high-performance temperature-controlled crystal oscillator is feedback-controlled to achieve signal purification and phase noise optimization of the input signal at a low offset frequency (below 1 Hz). It overcomes the disadvantages of the existing conventional phase-locked loop system, which has a relatively wide phase-locked loop bandwidth and the inability to effectively remove the proximal noise.

[0006] The object of the present invention is achieved by adopting the following technical solution: A clock signal purification and optimization device includes a frequency difference or phase difference measurement unit, a signal processing unit, and a high-stability crystal oscillator unit. The frequency difference or phase difference measurement unit, the signal processing unit, and the high-stability crystal oscillator unit are connected in sequence, and the output end of the high-stability crystal oscillator unit is also connected to the output end of the frequency difference or phase difference measurement unit.

[0007] Further, a frequency multiplier 1 and a mixer 1 are also provided between the frequency difference or phase difference measurement unit and the input signal F1 to be purified and refined. The input end of the frequency multiplier 1 is connected to the input signal F1, the output end is connected to the input end of the mixer 1, and the output end of the mixer 1 is connected to the input end of the frequency difference or phase difference measurement unit.

[0008] Further, the output end of the frequency difference or phase difference measurement unit is connected to the signal processing unit, and the output end of the signal processing unit is connected to the controlled source.

[0009] Further, the output end of the controlled source is connected to the power divider 1. The power divider 1 divides the output signal F0 of the controlled source into three paths. The first path is the output, the second path is connected to the frequency multiplier 2, and the third path is connected to the frequency synthesizer.

[0010] Further, the output end of the frequency multiplier 2 is connected to the input end of the frequency difference or phase difference measurement unit.

[0011] Further, a mixer 2 is also provided between the frequency multiplier 2 and the frequency difference or phase difference measurement unit.

[0012] Further, the output end of the frequency synthesizer is connected to the input end of the power divider 2. The output end of the power divider 2 is respectively connected to the input ends of the mixer 1 and the mixer 2. The output ends of the mixer 1 and the mixer 2 are both connected to the input end of the frequency difference or phase difference measurement unit.

[0013] Further, the high-stability crystal oscillator unit is a controlled source, and the controlled source is one of an analog voltage-controlled crystal oscillator and a digital frequency synthesizer.

[0014] The beneficial effects of the present invention are as follows: Since the loop bandwidth, gain amplitude, control method, and filtering method of the signal processing process of the present invention can all be flexibly configured, a narrowband phase-locked function that is not convenient to implement with a conventional analog phase-locked loop can be realized, and the phase noise optimization interval of the input signal can be flexibly selected and configured; the structure of this device is relatively simple, with low power consumption and high frequency tracking accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the structures shown in these drawings.

[0016] Figure 1 It is a principle block diagram of the present invention;

[0017] Figure 2 This is a schematic diagram of the structure of the present invention. Detailed implementation manners

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0019] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0020] The following will describe in detail some implementation manners of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0021] Embodiment 1:

[0022] Referring to Figure 1 、 Figure 2 , a clock signal purification and optimization device includes a frequency difference or phase difference measurement unit, a signal processing unit, and a high-stability crystal oscillator unit. The frequency difference or phase difference measurement unit, the signal processing unit, and the high-stability crystal oscillator unit are connected in sequence. The output end of the high-stability crystal oscillator unit is also connected to the output end of the frequency difference or phase difference measurement unit. Among them, the frequency difference or phase difference measurement unit is used to accurately measure the frequency difference data between the output signal and the local high-stability crystal oscillator; the signal processing unit is used to store, process the frequency difference data, and generate a control signal for controlling the high-stability crystal oscillator; the high-stability crystal oscillator unit is used to track the center frequency of the input signal and output a microwave signal with low noise.

[0023] In this embodiment, a frequency multiplier 1 and a mixer 1 are further provided between the frequency difference or phase difference measurement unit and the input signal F1 to be purified. Among them, the input end of the frequency multiplier 1 is connected to the input signal F1, the output end is connected to the input end of the mixer 1, and the output end of the mixer 1 is connected to the input end of the frequency difference or phase difference measurement unit. The input signal F1 to be purified can be expressed as:

[0024]

[0025] In the formula, A1 represents the amplitude of the radio frequency signal; is the phase of the radio frequency signal; w1 is the frequency of the radio frequency signal. Since the present invention focuses on discussing the phase noise of the signal, the power (amplitude) and initial phase of the signal are simplified and not considered (similarly processed for the signals hereinafter), so the signal F1 can be simply expressed as:

[0026] F1 = cos(w1t)

[0027] After the signal passes through the frequency multiplier 1 and is multiplied m times, the multiplied signal F2 is obtained:

[0028] F2 = cos(mw1t).

[0029] In this embodiment, the output end of the frequency difference or phase difference measurement unit is connected to the signal processing unit, the output end of the signal processing unit is connected to the controlled source, the output end of the controlled source is connected to the power divider 1, the power divider 1 divides the output signal F0 of the controlled source into 3 paths, where the first path is for output, the second path is connected to the frequency multiplier 2, the third path is connected to the frequency synthesizer, the output end of the frequency multiplier 2 is connected to the input end of the frequency difference or phase difference measurement unit, a mixer 2 is further provided between the frequency multiplier 2 and the frequency difference or phase difference measurement unit, the output end of the frequency synthesizer is connected to the input end of the power divider 2, the output end of the power divider 2 is respectively connected to the input ends of the mixer 1 and the mixer 2, and the output ends of the mixer 1 and the mixer 2 are both connected to the input end of the frequency difference or phase difference measurement unit.

[0030] The signal output by the local controlled source is denoted as F0:

[0031] F0 = cos(w0t)

[0032] The output signal F0 of the controlled source is divided into 3 paths by the power divider 1, one path is for output, one path is multiplied n times by the frequency multiplier 2 to generate a high-frequency signal F4, and the other path is frequency synthesized by the frequency synthesizer to generate a signal F3 whose frequency is close to those of F4 and F2.

[0033] F4 = cos(nw0t)

[0034] F3 = cos(w3t)

[0035] In the formula, w3 is relatively close to nw0 and mw1. Usually, the frequency deviation of the three frequency signals can be made less than 100 Hz. The purpose of frequency multiplying the input signal F1 and the local controlled signal F0 is to amplify the frequency deviation of the signal and improve the measurement accuracy of the frequency deviation. Theoretically, when a signal is multiplied N times, its frequency error will also be amplified N times correspondingly.

[0036] The signal F2 and the signal F3 are mixed by the mixer 1 to obtain the signal F5:

[0037] F5 = cos[(mw1 - w3)t]

[0038] Mix the signal F4 and the signal F3 through the mixer 2 to obtain the signal F6:

[0039] F6 = cos[(nw1 - w3)t].

[0040] Then, measure the frequency difference data of the two low-frequency signals F5 and F6 through the frequency difference or phase difference measurement unit. In the present invention, the signal is down-converted, and the main purpose of reducing the measured frequency difference is to reduce the error of the relative frequency measurement of the signal and improve the frequency measurement accuracy.

[0041] Usually, the frequency measurement of small-size and low-power systems uses the method of counting the clock pulses of the high-speed clock for the signal to be measured. The core idea of this method is to use the high-speed clock to measure the number of clock pulses within the unit period of the signal to be measured. There is always a truncation error of one high-speed clock period in the measurement accuracy. Taking the frequency f of the signal to be measured as an example, assume that the time difference of the sampling clock period is dT. Then, one sampling period of f can be expressed as:

[0042]

[0043] Considering the single clock error dT, the introduced relative frequency measurement error df / f can be obtained from the above formula:

[0044]

[0045] That is, for the measurement using the clock counting method, the relative frequency error of a single measurement is proportional to the magnitude of the frequency to be measured. Under the same conditions, reducing the frequency to be measured is beneficial to obtaining a better single frequency deviation measurement result.

[0046] For example, through signal frequency doubling and signal interpolation, for a 10 MHz input signal and a 10 MHz controlled crystal oscillator, when m = n = 10 and the synthesized frequency is 99.999960 MHz, the frequency difference measurement accuracy of the present invention is about 1E-13 / s, and the measurement accuracy improves with the average measurement time. This accuracy can achieve the accurate measurement of the existing commercial atomic clock signal. After obtaining the frequency difference data, the signal processing unit will perform numerical error judgment and digital filtering on the data, and generate the control signal of the controlled source based on this. In practical applications, the signal processing unit can either make the signals F0 and F1 consistent or set the frequency deviation to achieve the effects of signal tracking and frequency regulation.

[0047] In this embodiment, the high-stability crystal oscillator unit is the controlled source, and the controlled source can be an analog voltage-controlled crystal oscillator or a digital frequency synthesizer, which can be flexibly selected according to the noise purification requirements of the input signal.

[0048] Due to the flexible configuration of the loop bandwidth, gain amplitude, control method, and filtering method in the signal processing process of the present invention, the narrow-band phase-locked function that is not easily achieved by a conventional analog phase-locked loop can be realized, and the phase noise optimization interval of the input signal can be flexibly selected and configured. At the same time, the structure of the present invention is relatively simple, with low power consumption and high frequency tracking accuracy.

[0049] It should be noted that for the foregoing embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0050] In the above embodiments, the basic principles, main features, and advantages of the present invention are described. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, any modifications and changes made by those skilled in the art that do not depart from the spirit and scope of the present invention shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A clock signal purification and optimization device, characterized in that It includes a frequency difference or phase difference measurement unit, a signal processing unit and a high-stability crystal oscillator unit. The frequency difference or phase difference measurement unit, the signal processing unit and the high-stability crystal oscillator unit are connected in sequence. The output end of the high-stability crystal oscillator unit is also connected to the second input end of the frequency difference or phase difference measurement unit; The first input terminal of the frequency difference or phase difference measurement unit is connected to the input signal to be purified and refined A frequency multiplier 1 and a mixer 1 are also provided therebetween. Among them, the input terminal of the frequency multiplier 1 is connected to the input signal The output terminal is connected to the first input terminal of the mixer 1, and the output terminal of the mixer 1 is connected to the first input terminal of the frequency difference or phase difference measurement unit; The output end of the frequency difference or phase difference measurement unit is connected to the input end of the signal processing unit. The output end of the signal processing unit is connected to a controlled source, and the controlled source is the high-stability crystal oscillator unit; The output terminal of the controlled source is connected to the input terminal of the power divider 1, and the power divider 1 distributes the output signal of the controlled source into three paths. The first path is the output, the second path is connected to the frequency multiplier 2, and the third path is connected to the frequency synthesizer; the output terminal of the frequency multiplier 2 is connected to the second input terminal of the frequency difference or phase difference measurement unit; a mixer 2 is also provided between the frequency multiplier 2 and the frequency difference or phase difference measurement unit, and the first input terminal of the mixer 2 is connected to the output terminal of the frequency multiplier 2; the output terminal of the frequency synthesizer is connected to the input terminal of the power divider 2, the output terminals of the power divider 2 are respectively connected to the second input terminals of the mixer 1 and the mixer 2, and the output terminals of the mixer 1 and the mixer 2 are respectively connected to the first input terminal and the second input terminal of the frequency difference or phase difference measurement unit.

2. The clock signal purification and optimization device according to claim 1, characterized in that The high-stability crystal oscillator unit is a controlled source, and the controlled source is one of an analog voltage-controlled crystal oscillator and a digital frequency synthesizer.

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