CMOS detector debugging system and detection method

Abstract

A debugging system and detection method for a CMOS detector relates to the field of CMOS detector screening and testing, and addresses issues such as chip burnout, SPI write operation errors, and image blur that can easily occur during the power-on process of existing CMOS detectors. The system comprises an LDO power supply and current detection circuit for VDD18D, VDD18AD, and VDD5A, a charge transfer gate low-voltage power supply and current detection circuit, a pixel and reference source power supply and current detection circuit, a source follower power supply and current detection circuit, a charge transfer gate high-voltage power supply and current detection circuit, and a level conversion circuit. The present invention implements current limiting on the detector's power supply, setting a maximum output current. Simultaneously, the detector's status is diagnosed based on various abnormal phenomena that may occur during the CMOS detector's power-on process, and corresponding processing is performed to avoid the generation of abnormally high currents caused by applying all power supplies due to an erroneous state.

Description

Technical Field

[0001] The present invention relates to the field of CMOS detector screening and testing, and in particular to a debugging system and a detection method for a CMOS detector based on high reliability applications. Background Art

[0002] During screening testing of CMOS detectors, stress-free sockets are often used to facilitate testing of multiple detectors. During detector power-up, if the power-up sequence is incorrect due to poor contact on some pins, abnormally high currents may flow. Failure to disconnect the power supply in a timely manner could damage the CMOS detector or even burn out the chip. A loss of digital supply voltage during power-up can cause a transient surge in current. If this surge cannot be controlled, it could burn out the detector. SPI write errors can prevent the detector from operating as expected during power-up, and the readback SPI registers may be erroneous. Poor contact on the differential output pins of the detector can lead to insufficient stable taps (the delay value of the IODELAY delay unit in the FPGA) during serial image data training, resulting in training failure or image artifacts after successful training. Summary of the Invention

[0003] The present invention provides a debugging system and a detection method for a CMOS detector to solve the problems of chip burnout, SPI write operation errors, and image blurring that easily occur during the power-on process of the existing CMOS detector.

[0004] CMOS detector debugging system, including a controller and a detector; also includes LDO power supply and current detection circuits for VDD18D, VDD18AD and VDD5A, charge transfer gate low-voltage power supply and current detection circuits, pixel and reference source power supply and current detection circuits, source follower power supply and current detection circuits, charge transfer gate high-voltage power supply and current detection circuits and level conversion circuits;

[0005] The controller provides the detector with the system working clock of the detector, and the output signal forms the SPI and control signal after passing through the level conversion circuit; the controller simultaneously controls the LDO power supply and current detection circuit of VDD18D, VDD18AD and VDD5A, the charge transfer gate low voltage power supply and current detection circuit, the pixel and reference source power supply and current detection circuit, the source follower power supply and current detection circuit, the charge transfer gate high voltage power supply and current detection circuit and the level conversion circuit, and generates the power-on timing sequence of each part of the power supply and control signal according to the power-on timing sequence requirements of the detector;

[0006] The detector outputs serial image data, which is sent to a controller for training and then converted into parallel image data.

[0007] The present invention also provides a CMOS detector detection method, the specific process of the method is as follows:

[0008] Step 1: After power-on, sequentially detect the LDO current values ​​of VDD18D, VDD18AD, and VDD5A; the controller sends a system reset signal SYS_RST_N to the detector and reads back the value of the SPI register; judge the data value of the detector's SPI register read and write operation and detect the accompanying clock in the detector's output serial image data to ensure connectivity between the detector's pins. If no abnormalities are found, proceed to step 2;

[0009] Step 2: The controller outputs a driving control signal to the detector, which is then sent to the detector after passing through the level conversion circuit;

[0010] Step 3: The charge transfer gate low voltage power supply and current detection circuit, pixel and reference source power supply and current detection circuit start power output, and then detect the estimated current I of the charge transfer gate low voltage power supply, pixel and reference source power supply. evaluate_1 If the capacitors at the LDO output are fully charged during the power-up phase, the detected current is less than or equal to 2 times the estimated current I evaluate_1 , then go to step 4, otherwise check the power supply circuit with excessive current and handle the abnormality.

[0011] Step 4: The source follower power supply and the charge transfer gate high voltage power supply start to output power, and then detect the estimated current I of the charge transfer gate high voltage power supply and the source follower power supply circuit. evaluate_2 If the capacitors at the output of the LDO are fully charged, the detected current is less than or equal to 2 times the estimated current I evaluate_2 , then go to step 5, otherwise check the power supply circuit with excessive current and take corresponding measures.

[0012] Step 5: The controller receives the serial image data output by the detector and trains the serial image data. If the number of stable taps detected is less than half of the number of taps determined by the operating frequency, or if the trained image is blurred, the serial image data pin of the detector is checked for poor contact. If the processing is completed or there is no abnormality, step 6 is executed.

[0013] The frequency of the serial image data, the reference clock frequency of IODELAY and the maximum tap number of IODELAY are used to estimate the maximum tap number corresponding to the detected stable area;

[0014] Step 6: Output the detector's photosensitive image; by changing the incident light energy, see if the output follows the change. If it does not follow the change and the sensitivity is poor, check the relevant pins of the drive control signal.

[0015] Beneficial effects of the present invention:

[0016] 1. By powering on in an orderly and step-by-step manner, it is possible to avoid abnormal current burning the detector due to powering on under abnormal working conditions.

[0017] 2. By testing and telemetry the working status of the detector in steps, the pins that may have abnormalities can be quickly located. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a principle block diagram of the debugging system for the CMOS detector of the present invention. DETAILED DESCRIPTION

[0019] Combine Figure 1 This embodiment describes a debugging system for a CMOS detector, including a controller, a detector, an LDO power supply and current detection circuit for VDD18D, VDD18AD, and VDD5A (VDD18D, VDD18AD, and VDD5A are different names for power supply pins), a charge transfer gate low-voltage power supply and current detection circuit, a pixel and reference source power supply and current detection circuit, a source follower power supply and current detection circuit, a charge transfer gate high-voltage power supply and current detection circuit, and a level conversion circuit.

[0020] The controller provides the detector's system operating clock, and its output signals are converted into SPI and control signals after passing through the level conversion circuit. The controller also generates the power-on timing sequence for the detector's power supply and control signals by controlling the LDO power supply and current detection circuits for VDD18D, VDD18AD, and VDD5A; the charge transfer gate low-voltage power supply and current detection circuit; the pixel and reference source power supply and current detection circuits; the source follower power supply and current detection circuit; the charge transfer gate high-voltage power supply and current detection circuit; and the level conversion circuit.

[0021] The detector outputs serial image data, which is transmitted to the controller for training and then converted into parallel image data.

[0022] In this embodiment, the controllable output mode of the detector working clock is output through a double data rate output register ODDR.

[0023] In this embodiment, the method for detecting by the debugging system of the CMOS detector is to detect the detector in a safe and reliable power-on sequence. The specific process is as follows:

[0024] Step 1: Before the detector is powered on, the controller provides a low-jitter differential clock to the detector;

[0025] Step 2: The LDOs of VDD18D, VDD18AD, and VDD5A start to supply power, and then detect the LDO current values ​​I of VDD18D, VDD18AD, and VDD5A. evaluate If the capacitors at the LDO output are fully charged after power-on and the detected current does not exceed 2 times the estimated current I evaluate If the current is too high, proceed to step 3. Otherwise, check the LDO power supply circuit and take appropriate measures. After handling the abnormality, proceed to step 3. Abnormal handling includes checking for a short circuit to ground or an overheated device.

[0026]

[0027] Where U O is the expected voltage value of LDO output, R O is the resistance value of the LDO output terminal to ground.

[0028] Step 3: The controller sends a system reset signal SYS_RST_N to the detector, which is then sent to the detector through the level conversion circuit. After the internal reset of the detector is completed, the SPI register value of the detector is read back to see if they are all 0. If not, check the connectivity of the detector's system reset pin SYS_RST_N, SPI read and write operation pins, and the level conversion circuit. After handling the exception, proceed to step 4.

[0029] Step 4: Write to the detector's SPI register. After the write operation is complete, read the register and compare the read and write data values ​​to see if they are identical. If the readback data differs from the written data and is consistently 0, check whether the detector's system reset pin, SYS_RST_N, is consistently low. If the readback data differs from the written data and is not consistently 0, check the connectivity between the SPI read and write pins and the level shifter circuit. After handling any exceptions, proceed to Step 5.

[0030] Step 5: Check whether the companion clock exists in the serial image data output by the detector, and whether the frequency of the companion clock is half the frequency of the low-jitter differential clock provided by the controller to the detector. If not, check whether the differential clock pin of the detector has poor contact or whether the companion clock pin of the detector has poor contact;

[0031] Step 6: The controller starts to output the driving control signal to the detector, which is then sent to the detector after passing through the level conversion circuit;

[0032] Step 7: The charge transfer gate low voltage power supply and current detection circuit, the pixel and reference source power supply and current detection circuit start power output, and then detect the estimated current I of the charge transfer gate low voltage power supply, the pixel and reference source power supply circuit. evaluate_1If the capacitors at the LDO output are fully charged during the power-up phase, the detected current does not exceed 2 times the estimated current I evaluate_1 , then proceed to step eight, otherwise check the power supply circuit with excessive current and take corresponding measures.

[0033] Step 8: The source follower power supply and the charge transfer gate high voltage power supply start to output power, and then detect the estimated current I of the charge transfer gate high voltage power supply and the source follower power supply circuit. evaluate_2 If the capacitors at the output of the LDO are fully charged, the detected current does not exceed 2 times the estimated current I evaluate_2 , proceed to step nine, otherwise check the power supply circuit with excessive current and take appropriate measures.

[0034] Step 9: The controller receives the serial image data output by the detector and performs training on the serial image data. If the number of stable taps detected is less than half the number of taps determined by the operating frequency, or if trained image artifacts are present, the controller checks the serial image data pins of the detector for poor contact. If this is complete or no abnormalities are detected, proceed to Step 10.

[0035] Frequency f of serial image data serial_data , iodelay reference clock frequency f reference and the maximum tap number n of iodelay mp_max Estimate the maximum number of taps n corresponding to the stable region that can be detected data_mp_max ;

[0036]

[0037] Step 10: Output the detector's photosensitive image. Change the incident light energy to see if the output changes accordingly. If it does not, indicating poor sensitivity, check the pins associated with the drive control signal.

[0038] In this embodiment, the controller uses FPGA from Xilinx; the detector uses detector from Gpixel; the level conversion circuit uses 74AC164245; the power supply circuits use TPS7H1101 and TPS7H1101 from TI, AD8041 from ADI, etc.

Claims

1. A detection method for a CMOS detector, characterized by: The detection method is implemented through a CMOS detector debugging system, which includes a controller and a detector, as well as an LDO power supply and current detection circuit for VDD18D, VDD18AD and VDD5A, a charge transfer gate low-voltage power supply and current detection circuit, a pixel and reference source power supply and current detection circuit, a source follower power supply and current detection circuit, a charge transfer gate high-voltage power supply and current detection circuit and a level conversion circuit. The controller provides the detector with the system working clock of the detector, and the output signal forms the SPI and control signal after passing through the level conversion circuit; the controller simultaneously controls the LDO power supply and current detection circuit of VDD18D, VDD18AD and VDD5A, the charge transfer gate low voltage power supply and current detection circuit, the pixel and reference source power supply and current detection circuit, the source follower power supply and current detection circuit, the charge transfer gate high voltage power supply and current detection circuit and the level conversion circuit, and generates the power-on timing sequence of each part of the power supply and control signal according to the power-on timing sequence requirements of the detector; The detector outputs serial image data, which is sent to the controller for training and then converted into parallel image data; The specific steps of this method are as follows: Step 1: After power-on, sequentially detect the LDO current values ​​of VDD18D, VDD18AD, and VDD5A; the controller sends a system reset signal SYS_RST_N to the detector and reads back the value of the SPI register; judge the data value of the detector's SPI register read and write operation and detect the accompanying clock in the detector's output serial image data to ensure connectivity between the detector's pins. If no abnormalities are found, proceed to step 2; Step 2: The controller outputs a driving control signal to the detector, which is then sent to the detector after passing through the level conversion circuit; Step 3: The charge transfer gate low voltage power supply and current detection circuit, pixel and reference source power supply and current detection circuit start power output, and then detect the estimated current I of the charge transfer gate low voltage power supply, pixel and reference source power supply. evaluate_1 ; If the capacitors at the LDO output are fully charged during the power-up phase, the detected current is less than or equal to 2 times the estimated current I evaluate_1 , then go to step 4, otherwise check the power supply circuit with high current and handle the abnormality; Step 4: The source follower power supply and the charge transfer gate high voltage power supply start to output power, and then detect the estimated current I of the charge transfer gate high voltage power supply and the source follower power supply circuit. evaluate_2 If the capacitors at the output of the LDO are fully charged, the detected current is less than or equal to 2 times the estimated current I evaluate_2 , then go to step 5, otherwise check the power supply circuit with high current and take corresponding measures; Step 5: The controller receives the serial image data output by the detector and trains the serial image data. If the number of stable taps detected is less than half of the number of taps determined by the operating frequency, or if the trained image is blurred, the serial image data pin of the detector is checked for poor contact. If the processing is completed or there is no abnormality, proceed to step 6; Estimate the maximum number of taps corresponding to the detected stable region based on the frequency of the serial image data, the reference clock frequency of the IODELAY, and the maximum number of taps of the IODELAY; Step 6: Output the detector's photosensitive image; by changing the incident light energy, see if the output follows the change. If it does not follow the change and the sensitivity is poor, check the relevant pins of the drive control signal.

2. The CMOS detector detection method according to claim 1, wherein: The detector working clock adopts the controllable output mode of ODDR.

3. The CMOS detector detection method according to claim 1, wherein: Before step 1, the method further includes the controller providing a low-jitter differential clock to the detector before the detector is powered on.

4. The CMOS detector detection method according to claim 1, wherein: The specific process of step one is: Step 1: After power-on, the LDOs of VDD18D, VDD18AD, and VDD5A start to supply power, and then detect the LDO current values ​​I of VDD18D, VDD18AD, and VDD5A. evaluate If the capacitors at the LDO output are fully charged after power-on and the detected current is less than or equal to 2 times the current value I evaluate , proceed to steps 1 and 2; otherwise, check the LDO power supply circuit with excessive current and handle the abnormality. After handling the abnormality, proceed to steps 1 and 2; Step 1 and 2: The controller sends a system reset signal SYS_RST_N to the detector, which is then sent to the detector after passing through the level conversion circuit; Then, after the internal reset of the detector is completed, read back the SPI register value of the detector to confirm whether the values ​​of the SPI registers are all 0; if they are all 0, execute step 13; otherwise, check the connectivity of the detector's system reset pin SYS_RST_N, the SPI read and write operation pins, and the level conversion circuit; after the exception is handled, proceed to step 13; Step 13: Write the detector's SPI register. After the write operation is completed, read the register and compare whether the data values ​​of the read and write operations are the same. If the read-back data is different from the written data and the read-back data is always 0, check whether the system reset SYS_RST_N pin of the detector is always at a low level. If the read-back data is different from the written data and the read-back data is not always 0, check the connectivity between the SPI read and write operation pins and the level conversion circuit. After handling the exception, execute step 14. Step 14: Detect the accompanying clock in the serial image data output by the detector, and determine whether the frequency of the accompanying clock is half of the low-jitter differential clock frequency provided by the controller to the detector. If so, execute step 2; if not, detect whether the differential clock pin of the detector has poor contact or whether the accompanying clock pin of the detector has poor contact, process the part with poor contact and then execute step 2.

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